Definitive Guide to ARM (R) Cortex (R)-M0 and Cortex-M0plus Processors 2nd edition [Pehme köide]

(Senior Embedded Technology Specialist, ARM Ltd., Cambridge, UK)
  • Formaat: Paperback, 784 pages, kõrgus x laius x paksus: 235x191x38 mm, kaal: 1560 g
  • Ilmumisaeg: 25-Jun-2015
  • Kirjastus: Newnes (an imprint of Butterworth-Heinemann Ltd )
  • ISBN-10: 0128032774
  • ISBN-13: 9780128032770
Teised raamatud teemal:
  • Formaat: Paperback, 784 pages, kõrgus x laius x paksus: 235x191x38 mm, kaal: 1560 g
  • Ilmumisaeg: 25-Jun-2015
  • Kirjastus: Newnes (an imprint of Butterworth-Heinemann Ltd )
  • ISBN-10: 0128032774
  • ISBN-13: 9780128032770
Teised raamatud teemal:
The Definitive Guide to the ARM® Cortex®-M0 and Cortex-M0+ Processors, Second Edition explains the architectures underneath ARM’s Cortex-M0 and Cortex-M0+ processors and their programming techniques.Written by ARM’s Senior Embedded Technology Manager, Joseph Yiu, the book is packed with examples on how to use the features in the Cortex-M0 and Cortex-M0+ processors. It provides detailed information on the instruction set architecture, how to use a number of popular development suites, an overview of the software development flow, and information on how to locate problems in the program code and software porting.This new edition includes the differences between the Cortex-M0 and Cortex-M0+ processors such as architectural features (e.g. unprivileged execution level, vector table relocation), new chapters on low power designs and the Memory Protection Unit (MPU), the benefits of the Cortex-M0+ processor, such as the new single cycle I/O interface, higher energy efficiency, better performance and the Micro Trace Buffer (MTB) feature, updated software development tools, updated Real Time Operating System examples using Keil™ RTX with CMSIS-RTOS APIs, examples of using various Cortex-M0 and Cortex-M0+ based microcontrollers, and much more.Provides detailed information on ARM® Cortex®-M0 and Cortex-M0+ Processors, including their architectures, programming model, instruction set, and interrupt handlingPresents detailed information on the differences between the Cortex-M0 and Cortex-M0+ processorsCovers software development flow, including examples for various development tools in both C and assembly languagesIncludes in-depth coverage of design approaches and considerations for developing ultra low power embedded systems, the benchmark for energy efficiency in microcontrollers, and examples of utilizing low power features in microcontrollers

Arvustused

"...if you're new to these components,...buy the book. It will give you the insight you need to be productive on real projects." --Embedded

Muu info

This book provides an up-to-date resource on everything users need to know to get up and running on the ARM Cortex-M0 and M0+ processors
Foreword xxi
Preface xxiii
Acknowledgment xxv
Terms and Abbreviations xxvii
Conventions xxix
References xxxi
Chapter 1 Introduction
1(28)
1.1 Welcome to the World of Embedded Processors
1(3)
1.1.1 Where Are the Processors Used?
1(1)
1.1.2 Processor, CPU, Core, Microprocessor, and All These Names
2(1)
1.1.3 Programming on Embedded Systems
3(1)
1.1.4 What Type of Skills Do I Need to Start Learning Microcontroller Programming?
4(1)
1.2 Understanding Different Types of Processors
4(14)
1.2.1 Why We Need Various Types of Processors
4(1)
1.2.2 Overview of the ARM Processor Families
5(3)
1.2.3 Blurring the Boundaries
8(1)
1.2.4 ARM Cortex-M Processor Series
8(4)
1.2.5 Quick Glance on the ARM Cortex-M0 and Cortex-M0+ Processor
12(1)
1.2.6 From Cortex-M0 Processor to Cortex-M0+ Processor
13(4)
1.2.7 Applications of the Cortex-M0 and Cortex-M0+ Processor
17(1)
1.3 What Is Inside a Microcontroller
18(4)
1.3.1 Typical Elements Inside a Microcontroller
18(2)
1.3.2 Characteristics of Processors for Microcontroller Applications
20(2)
1.3.3 Silicon Technologies
22(1)
1.4 There is Something About ARM®
22(3)
1.4.1 Do ARM Make Chips?
22(1)
1.4.2 What Else Does ARM Make?
23(1)
1.4.3 Why Do Not Chip Vendors Do Their Own Processor Designs?
23(1)
1.4.4 What is Special About the ARM Ecosystem?
24(1)
1.5 Resources on Using ARM® Processors and ARM Microcontrollers
25(4)
1.5.1 On the ARM Web Pages
25(1)
1.5.2 Resources from Microcontroller Vendors
26(2)
1.5.3 Resources from Tool Vendors
28(1)
1.5.4 Other Resources
28(1)
Chapter 2 Technical Overview
29(26)
2.1 What are the Cortex®-M0 and Cortex-M0+ Processors?
29(2)
2.2 Block Diagrams
31(3)
2.3 Typical Systems
34(3)
2.4 What Is ARMv6-M Architecture?
37(1)
2.5 Software Portability Between Cortex®-M Processors
38(2)
2.6 The Advantages of the ARM® Cortex®-M0 and Cortex-M0+ Processor
40(5)
2.6.1 Low Power and Energy Efficiency
40(1)
2.6.2 High Code Density
41(1)
2.6.3 Low Interrupt Latency and Deterministic Behavior
42(1)
2.6.4 Ease of Use
42(1)
2.6.5 System-Level Features and OS Support Features
42(1)
2.6.6 Comprehensive Debug Features
43(1)
2.6.7 Configurability, Flexibility, and Scalability
43(1)
2.6.8 Software Portability and Reusability
44(1)
2.6.9 Wide Range of Product Choices
44(1)
2.6.10 Wide Ecosystem Support
45(1)
2.7 Applications of the Cortex®-M0 and Cortex-M0+ Processors
45(3)
2.7.1 Microcontrollers
45(1)
2.7.2 Sensors
46(1)
2.7.3 Sensor Hubs
47(1)
2.7.4 Power Management 1C
47(1)
2.7.5 ASSPs, ASICs
47(1)
2.7.6 Subsystems in System on Chips
47(1)
2.8 Why Using a 32-Bit Processor for Microcontroller Applications?
48(7)
2.8.1 Performance
48(1)
2.8.2 Code Density
49(3)
2.8.3 Other Benefits of ARM Architectures
52(1)
2.8.4 Software Reusability
53(2)
Chapter 3 Introduction to Embedded Software Development
55(32)
3.1 Welcome to Embedded System Programming
55(1)
3.2 Some Basic Concepts
55(9)
3.2.1 Reset
55(1)
3.2.2 Clocks
56(1)
3.2.3 Voltage Level
57(1)
3.2.4 Inputs and Outputs
57(1)
3.2.5 Introduction to Embedded Software Program Flows
58(5)
3.2.6 Programming Language Choices
63(1)
3.3 Introduction to ARM® Cortex®-M Programming
64(10)
3.3.1 C Programming---Data Types
64(1)
3.3.2 Accessing Peripherals in C
65(4)
3.3.3 What Is Inside a Program Image?
69(2)
3.3.4 Data in SRAM
71(2)
3.3.5 What Happens When a Microcontroller Starts?
73(1)
3.4 Software Development Flow
74(4)
3.5 Cortex® Microcontroller Software Interface Standard
78(7)
3.5.1 Introduction of CMSIS
78(2)
3.5.2 What Are Standardized in CMSIS-CORE?
80(1)
3.5.3 Organization of the CMSIS-CORE
81(1)
3.5.4 Using CMSIS-CORE
81(2)
3.5.5 Benefits of CMSIS
83(2)
3.6 Other Information on Software Development
85(2)
Chapter 4 Architecture
87(22)
4.1 Overview of ARMv6-M Architecture
87(2)
4.1.1 What Architecture Means
87(1)
4.1.2 Background of the ARMv6-M Architecture
87(2)
4.2 Programmer's Model
89(8)
4.2.1 Operation Modes and States
89(1)
4.2.2 Registers and Special Registers
90(6)
4.2.3 Behaviors of the APSR
96(1)
4.3 Memory System
97(3)
4.3.1 Overview
97(2)
4.3.2 Single Cycle I/O Interface
99(1)
4.3.3 Memory Protection Unit
99(1)
4.4 Stack Memory Operations
100(2)
4.5 Exceptions and Interrupts
102(2)
4.6 Nested Vectored Interrupt Controller
104(1)
4.6.1 Flexible Interrupt Management
104(1)
4.6.2 Nested Interrupt Support
104(1)
4.6.3 Vectored Exception Entry
104(1)
4.6.4 Interrupt Masking
105(1)
4.7 System Control Block
105(1)
4.8 Debug System
105(1)
4.9 Program Image and Start-up Sequence
106(3)
Chapter 5 Instruction Set
109(38)
5.1 What Is Instruction Set
109(1)
5.2 Background of ARM® and Thumb® Instruction Set
110(3)
5.3 Assembly Basics
113(6)
5.3.1 Quick Glance at Assembly Syntax
113(4)
5.3.2 Use of a Suffix
117(1)
5.3.3 Unified Assembler Language (UAL)
118(1)
5.4 Instruction List
119(25)
5.4.1 Moving Data within the Processor
120(2)
5.4.2 Memory Accesses
122(4)
5.4.3 Stack Memory Accesses
126(1)
5.4.4 Arithmetic Operations
127(4)
5.4.5 Logic Operations
131(1)
5.4.6 Shift and Rotate Operations
132(3)
5.4.7 Extend and Reverse Ordering Operations
135(2)
5.4.8 Program Flow Control
137(2)
5.4.9 Memory Barrier Instructions
139(2)
5.4.10 Exception-Related Instructions
141(1)
5.4.11 Sleep Mode Feature-Related Instructions
142(1)
5.4.12 Other Instructions
143(1)
5.5 Pseudo Instructions
144(3)
Chapter 6 Instruction Usage Examples
147(18)
6.1 Overview
147(1)
6.2 Program Control
147(6)
6.2.1 If-then-else
147(1)
6.2.2 Loop
148(1)
6.2.3 More on the Branch Instructions
148(1)
6.2.4 Typical Usages of Branch Conditions
148(2)
6.2.5 Function Calls and Function Returns
150(1)
6.2.6 Branch Table
151(2)
6.3 Data Accesses
153(4)
6.3.1 Simple Data Accesses
153(1)
6.3.2 Example of Using Memory Access Instruction
154(3)
6.4 Data Type Conversion
157(1)
6.4.1 Conversion of Data Size
157(1)
6.4.2 Endian Conversion
158(1)
6.5 Data Processing
158(7)
6.5.1 64-Bit/128-Bit Add
158(1)
6.5.2 64-Bit/128-Bit Sub
159(1)
6.5.3 Integer Divide
159(2)
6.5.4 Unsigned Integer Square Root
161(1)
6.5.5 Bit and Bit Field Computations
162(3)
Chapter 7 Memory System
165(20)
7.1 Memory Systems in Microcontrollers
165(1)
7.2 Bus Systems in the Cortex®-M0 and Corfex-M0+ Processors
166(1)
7.3 Memory Map
167(3)
7.3.1 Overview
167(1)
7.3.2 Code Region (0x00000000---0x1FFFFFFF)
168(1)
7.3.3 SRAM Region (0x20000000---0x3FFFFFFF)
168(1)
7.3.4 Peripheral Region (0x40000000---0x5FFFFFFF)
169(1)
7.3.5 RAM Region (0x60000000---0x9FFFFFFF)
169(1)
7.3.6 Device Region (OxA0000000-0xDFFFFFFF)
169(1)
7.3.7 Internal Private Peripheral Bus (0xE0000000---0xE00FFFFF)
169(1)
7.3.8 Reserved Memory Space (OxE0100000---0Xffffffff)
170(1)
7.3.9 System Level Design
170(1)
7.4 Program Memory, Boot Loader, and Memory Remapping
170(3)
7.4.1 Program Memory and Boot Loader
170(2)
7.4.2 Memory Remap
172(1)
7.5 Data Memory
173(1)
7.6 Little Endian and Big Endian Support
174(1)
7.7 Data Type
175(2)
7.8 Memory Attributes and Memory Access Permission
177(3)
7.9 Effect of Hardware Behavior to Programming
180(5)
7.9.1 Data Alignment
180(1)
7.9.2 Access to Invalid Addresses
181(1)
7.9.3 Use of Multiple Load and Store Instructions
181(1)
7.9.4 Wait States
182(3)
Chapter 8 Exceptions and Interrupts
185(34)
8.1 What are Exceptions and Interrupts?
185(2)
8.2 Exception Types on the Cortex®-M0 and Cortex-M0+ Processors
187(2)
8.2.1 Overview
187(1)
8.2.2 Non-Maskable Interrupt
187(1)
8.2.3 HardFault
188(1)
8.2.4 SVCall (Supervisor Call)
188(1)
8.2.5 Pendable Service Call
188(1)
8.2.6 System Tick Timer
188(1)
8.2.7 Interrupts
189(1)
8.3 Brief Overview of the NVIC
189(1)
8.4 Definition of Exception Priority Levels
190(2)
8.5 Vector Table
192(2)
8.6 Exception Sequence Overview
194(3)
8.6.1 Acceptance of Exception Request
194(1)
8.6.2 Stacking and Unstacking
194(1)
8.6.3 Exception Return Instruction
195(1)
8.6.4 Tail Chaining
196(1)
8.6.5 Late Arrival
196(1)
8.7 EXC_RETURN
197(3)
8.8 NVIC Control Registers for Interrupt Control
200(6)
8.8.1 Overview of NVIC Control Registers
200(1)
8.8.2 Interrupt Enable and Clear Enable
200(2)
8.8.3 Interrupt Pending Set and Clear Register
202(2)
8.8.4 Interrupt Priority Level
204(2)
8.9 Exception Masking Register (PRIMASK)
206(1)
8.10 Interrupt Inputs and Pending Behavior
207(5)
8.10.1 Simple Interrupt Process
207(1)
8.10.2 Simple Pulse Interrupt Handling
208(1)
8.10.3 Canceling of Interrupt Pending Status Before the Interrupt Is Serviced
209(1)
8.10.4 Clearing of Pending Status While Peripheral Still Asserting IRQ
209(1)
8.10.5 IRQ Remains High When ISR Completed
210(1)
8.10.6 Multiple IRQ Pulses Before Entering ISR
210(1)
8.10.7 IRQ Pulse During ISR Execution
210(1)
8.10.8 IRQ Assertion for a Disabled Interrupt
211(1)
8.11 Details of Exception Entry Sequence
212(3)
8.11.1 Stacking
212(2)
8.11.2 Vector Fetch and Update PC
214(1)
8.11.3 Registers Update
214(1)
8.12 Details of Exception Exit Sequence
215(1)
8.12.1 Unstacking of Registers
215(1)
8.12.2 Fetch and Execute From Return Address
215(1)
8.13 Interrupt Latency
215(4)
Chapter 9 System Control and Low-Power Features
219(24)
9.1 Brief Introduction of System Control Registers
219(1)
9.2 Registers in the SCBs
220(6)
9.2.1 List of Registers in the SCB
220(1)
9.2.2 CPU ID Base Register
220(1)
9.2.3 Control Registers for System Exceptions Management
221(2)
9.2.4 Vector Table Offset Register
223(1)
9.2.5 Application Interrupt and Reset Control Register
224(1)
9.2.6 System Control Register
225(1)
9.2.7 Configuration and Control Register
225(1)
9.2.8 System Handler Control and State Register
226(1)
9.3 Using the Self-Reset Feature
226(2)
9.4 Using the Vector Table Relocation Feature
228(2)
9.5 Low-Power Features
230(13)
9.5.1 Overview
230(1)
9.5.2 Sleep Modes
231(1)
9.5.3 Wait-for-Event and Wait-for-Interrupt
232(3)
9.5.4 Wake-up Conditions
235(2)
9.5.5 Sleep-On-Exit Feature
237(2)
9.5.6 Wake-up Interrupt Controller
239(4)
Chapter 10 Operating System Support Features
243(36)
10.1 Overview of OS Support Features
243(1)
10.2 Introduction to Operating Systems in Embedded World
243(2)
10.3 The SysTick Timer
245(7)
10.3.1 SysTick Registers
246(2)
10.3.2 Setting up SysTick
248(2)
10.3.3 Using SysTick Timer for Timing Measurement
250(1)
10.3.4 Using SysTick Timer in Single Shot Mode
251(1)
10.4 Process Stack and PSP
252(4)
10.5 SVCall Exception
256(2)
10.6 PendSV
258(1)
10.7 Advanced Topics: Using SVC and PendSV in Programming
259(8)
10.7.1 Using the SVC Exception
260(5)
10.7.2 Using the PendSV Exception
265(2)
10.8 Advanced Topics: Context Switching in Action
267(12)
Chapter 11 Fault Handling
279(12)
11.1 Fault Exception Overview
279(1)
11.2 What Can Cause a Fault?
279(1)
11.3 Analyze a Fault
280(2)
11.4 Accidental Switching to ARM® State
282(1)
11.5 Error Handling in Real Applications
283(1)
11.6 Error Handling During Software Development
283(3)
11.7 Lockup
286(2)
11.7.1 Causes of Lockup
286(2)
11.7.2 What Happens During a Lockup?
288(1)
11.8 Preventing Lockup
288(1)
11.9 Comparison with Fault Handling in ARMv7-M Architecture
289(2)
Chapter 12 Memory Protection Unit
291(84)
12.1 What is MPU?
291(1)
12.2 MPU Use Cases
292(2)
12.3 Technical Introduction
294(1)
12.4 MPU Registers
294(8)
12.4.1 MPU Type Register
295(1)
12.4.2 MPU Control Register
296(1)
12.4.3 MPU Region Number Register
297(1)
12.4.4 MPU Region Base Address Register
297(1)
12.4.5 MPU Region Base Attribute and Size Register
298(4)
12.5 Setting Up the MPU
302(6)
12.6 Memory Barrier and MPU Configuration
308(1)
12.7 Using Sub-Region Disable
309(1)
12.7.1 Allow Efficient Memory Separation
309(1)
12.7.2 Reduce the Total Number of Regions Needed
310(1)
12.8 Considerations When Using MPU
310(2)
12.8.1 Program Code
311(1)
12.8.2 Data Memory
311(1)
12.9 Comparing with the MPU in the Cortex®-M3/M4/M7 Processors
312(63)
Chapter 13 Debug Features
375
13.1 Software Development and Debug Features
315(2)
13.2 Debug Interface
317(3)
13.2.1 JTAG and Serial Wire Debug Communication Protocol
317(2)
13.2.2 Cortex-M Processor and CoreSight™ Debug Architecture
319(1)
13.2.3 Design Considerations with Debug Interface
320(1)
13.3 Debug Features Overview
320(1)
13.4 Debug System
321(1)
13.5 Halt Mode and Debug Events
321(3)
13.6 Instruction Tracing Support Using the MTB
324(5)
Chapter 14 Getting Started with the Keil Microcontroller Development Kit
329(80)
14.1 Introduction to Keil Microcontroller Development Kit
329(2)
14.1.1 Overview
329(1)
14.1.2 The Tools
330(1)
14.1.3 Advantages of Using Keil MDK
330(1)
14.1.4 Installation
331(1)
14.2 Typical Program Compilation Flow
331(3)
14.3 Introduction of the Hardware
334(4)
14.3.1 Freescale Freedom Board (FRDM-KL25Z)
334(1)
14.3.2 STMicroelectronics STM32L0 Discovery
335(1)
14.3.3 STMicroelectronics STM32F0 Discovery
336(1)
14.3.4 NXP LPC1114FN28
336(2)
14.4 Getting Started with μVision® IDE
338(49)
14.4.1 What Are Needed to Start
338(1)
14.4.2 Starting Keil MDK
338(1)
14.4.3 Project Setup Steps for Freescale FRDM-KL25Z
339(12)
14.4.4 Project Setup Steps for STMicroelectronics STM32L0 Discovery
351(11)
14.4.5 Project Setup Steps for STMicroelectronics STM32F0 Discovery
362(14)
14.4.6 Project Setup Steps for NXP LPC1114FN28
376(11)
14.5 Using the IDE and the Debugger
387(4)
14.6 Under the Hood
391(2)
14.6.1 CMSIS Files
391(1)
14.6.2 Clock Setup
391(1)
14.6.3 Stack and Heap Setup
391(1)
14.6.4 Compilation
392(1)
14.7 Customizations of the Project Environment
393(7)
14.7.1 Target Options
393(3)
14.7.2 Optimization Options
396(2)
14.7.3 Runtime Environment Options
398(1)
14.7.4 Project Management
398(2)
14.8 Using the Simulator
400(1)
14.9 Execution in SRAM
401(3)
14.10 Using MTB for Instruction Trace
404(5)
Chapter 15 Getting Started with IAR Embedded Workbench for ARM®
409(18)
15.1 Overview of IAR Embedded Workbench for ARM®
409(1)
15.2 Typical Program Compilation Row
410(2)
15.3 Creating a Simple Blinky Project
412(8)
15.4 Project Options
420(1)
15.5 Using MTB Instruction Trace with IAR EWARM
421(1)
15.6 Hints and Tips
422(5)
Chapter 16 Getting Started with gcc (GNU Compiler Collection)
427(32)
16.1 About the GNU Compiler Collection Tool Chain
427(1)
16.2 About the Examples in This
Chapter
427(1)
16.3 Typical Development Flow
428(3)
16.4 Creating a Simple Blinky Project
431(2)
16.5 Overview of the Command Line Options
433(3)
16.6 Flash Programming!
436(2)
16.7 Using Keil® MDK-ARM™ with GNU Tools for ARM® Embedded Processors
438(7)
16.8 Using CooCox CoIDE with GNU Tools for ARM® Embedded Processors
445(14)
16.8.1 Overview and Setup
445(2)
16.8.2 Create a New Project
447(7)
16.8.3 Using the IDE and the Debugger
454(5)
Chapter 17 Getting Started with mbed™
459(20)
17.1 What is mbed™
459(1)
17.2 How the mbed™ System Works
460(2)
17.3 Advantages of mbed™
462(1)
17.4 Setting Up Your FRDM-KL25Z Board and mbed™ Account
463(2)
17.4.1 Check Out mbed Web Page
463(1)
17.4.2 Register for an Account with mbed
463(1)
17.4.3 Additional Setup for the Personal Computer
463(2)
17.5 Creating a Blinky Program
465(2)
17.5.1 Simple Version with Just Red LED On/Off
465(2)
17.5.2 LED with Pulse Width Modulation Control
467(1)
17.6 Common Peripheral Objects Support
467(1)
17.7 Using printf
468(3)
17.8 Application Example---A Model Railway Controller
471(5)
17.9 Interrupts
476(2)
17.10 Hints and Tips
478(1)
Chapter 18 Programming Examples
479(32)
18.1 Producing Output with Universal Asynchronous Receiver/Transmitter
479(11)
18.1.1 Overview of Universal Asynchronous Receiver/Transmitter Communication
479(3)
18.1.2 Overview of UART Configurations on Microcontroller
482(1)
18.1.3 Programming the UART on FRDM-KL25Z
482(2)
18.1.4 Programming the UART on STM32L0 Discovery
484(2)
18.1.5 Programming the UART on STM32F0 Discovery
486(1)
18.1.6 Programming the UART on LPC1114FN28
487(3)
18.2 Handling printf
490(5)
18.2.1 Overview
490(1)
18.2.2 Retargeting with Keil® MDK
491(1)
18.2.3 Retargeting with IAR EWARM
492(1)
18.2.4 Retargeting with GNU Compiler Collection
493(1)
18.2.5 Semihosting with IAR EWARM
494(1)
18.2.6 Semihosting with CoIDE
495(1)
18.3 Developing Your Own Input and Output Functions
495(7)
18.3.1 Why Reinventing the Wheel?
495(5)
18.3.2 Other Interfaces
500(1)
18.3.3 Other Hints and Tips About scanf
501(1)
18.4 Interrupt Programming Examples
502(2)
18.4.1 General Overview of Interrupt Handling
502(1)
18.4.2 Overview of Interrupt Control Functions
502(2)
18.5 Application Example---Another Controller for a Model Train
504(4)
18.6 Different Versions of CMSIS-CORE
508(3)
Chapter 19 Ultralow-Power Designs
511(48)
19.1 Examples of Using Low-Power Features
511(9)
19.1.1 Overview
511(1)
19.1.2 Entering Sleep Modes
511(2)
19.1.3 WEE versus WFI
513(1)
19.1.4 Using Sleep-On-Exit Feature
514(1)
19.1.5 Using Send-Event-on-Pend Feature
515(1)
19.1.6 Using Wake-up Interrupt Controller
516(1)
19.1.7 Using Event Communication Interface
517(3)
19.2 Requirements of Low-Power Designs
520(1)
19.3 Where Does the Power Go?
521(2)
19.4 Developing Low-Power Applications
523(4)
19.4.1 Overview of Low-Power Design Practices
523(1)
19.4.2 Various Approaches to Reduce Power
524(1)
19.4.3 Selecting the Right Approach
525(2)
19.5 Debug Considerations
527(1)
19.5.1 Debug and Low-Power
527(1)
19.5.2 "Safe Mode" for Debug and Flash Programming
527(1)
19.5.3 Debug Interface and Low-Voltage Pins
527(1)
19.6 Benchmarking of Low-Power Devices
528(4)
19.6.1 Background of ULPBench™
528(1)
19.6.2 Overview of the ULPBench-CP
528(4)
19.7 Example of Using Low-Power Features on Freescale KL25Z
532(10)
19.7.1 Objective
532(1)
19.7.2 Test Setup
532(1)
19.7.3 Low-Power Modes on KL25Z
533(1)
19.7.4 Clocking Arrangement
533(2)
19.7.5 The Test Setup
535(5)
19.7.6 Measurement Results
540(2)
19.8 Example of Using Low-Power Feature on LPC1114
542(17)
19.8.1 Overview of LPC1114FN28
542(3)
19.8.2 First Experiment---Running at 12 MHz with Internal and External Crystal
545(3)
19.8.3 Second Experiment---Running at Reduced Frequencies of 1 MHz and 100 KHz
548(1)
19.8.4 Additional Improvements
549(1)
19.8.5 Using Deep Sleep on LPC1114
550(9)
Chapter 20 Programming with Embedded OS
559(48)
20.1 Introduction
559(8)
20.1.1 Background
559(1)
20.1.2 Embedded OS and RTOS
559(1)
20.1.3 Why Use an Embedded OS?
560(1)
20.1.4 Role of CMSIS-RTOS
560(2)
20.1.5 About the Keil® RTX Kernel
562(1)
20.1.6 Setting Up a Simple RTX Example with Keil MDK
563(4)
20.2 Overview of the RTX Kernel
567(30)
20.2.1 Thread
567(2)
20.2.2 RTX Configurations
569(1)
20.2.3 A Closer Look at the First Example
569(4)
20.2.4 Interthread Communciation Overview
573(1)
20.2.5 Signal Event Communication
574(4)
20.2.6 Mutual Exclusive (Mutex)
578(2)
20.2.7 Semaphore
580(3)
20.2.8 Message Queue
583(2)
20.2.9 Mail Queue
585(3)
20.2.10 Memory Pool Management Feature
588(2)
20.2.11 Generic Wait Function and Time-Out Value
590(1)
20.2.12 Timer Feature
590(3)
20.2.13 Adding SVC Services for Unprivileged Threads
593(4)
20.3 Using RTX in an Application
597(3)
20.4 Debugging an Application with RTX
600(1)
20.5 Trouble Shooting
601(3)
20.5.1 Stack Size Requirements
602(1)
20.5.2 Privileged Level
602(1)
20.5.3 Utilize OS Error Reporting Support
603(1)
20.5.4 OS Feature Configurations
603(1)
20.5.5 Miscellaneous
603(1)
20.6 Other Hints and Tips
604(3)
20.6.1 Customization of RTX_Config_CM.c
604(1)
20.6.2 Thread Priority
604(1)
20.6.3 A Short Waiting Time
604(1)
20.6.4 Additional Information
605(2)
Chapter 21 Mixed Language Projects (C/C++ with Assembly)
607(28)
21.1 Use of Assembly in Project Developments
607(1)
21.2 Recommended Practices in Assembly Programming and AAPCS
608(2)
21.3 Overview of an Assembly Function
610(3)
21.3.1 ARM® Tool Chains
610(1)
21.3.2 Gcc Tool Chains
611(1)
21.3.3 IAR Embedded Workbench for ARM
612(1)
21.3.4 Structure of an Assembly Function
612(1)
21.4 Inline Assembly
613(3)
21.4.1 ARM® Tool Chains (Keil® MDK7DS-5)
613(2)
21.4.2 GNU Compiler Collection
615(1)
21.5 Embedded Assembler Feature (ARM® Tool Chain)
616(1)
21.6 Mixed Language Projects
617(2)
21.6.1 Overview
617(1)
21.6.2 Calling C Functions from Assembly Codes
617(1)
21.6.3 Calling Assembly Functions from C Codes
618(1)
21.7 Creating Assembly Projects in Keil® MDK-ARM
619(5)
21.7.1 A Small Project
619(1)
21.7.2 Hello World
620(1)
21.7.3 Additional Text Output Functions
621(3)
21.8 Generic Assembly Code for Interrupt Control
624(4)
21.8.1 Enable and Disable Interrupts
624(1)
21.8.2 Set and Clear Interrupt Pending Status
625(1)
21.8.3 Setting Up Interrupt Priority Level
626(2)
21.9 Other Programming Techniques for Assembly Language
628(3)
21.9.1 Allocating Data Space for Variables
628(2)
21.9.2 Complex Branch Handling
630(1)
21.10 Accessing Special Instructions
631(4)
21.10.1 CMSIS-CORE
631(1)
21.10.2 Idiom Recognitions
632(3)
Chapter 22 Software Porting
635(26)
22.1 A Overview
635(1)
22.2 Porting Software from 8-Bit/16-Bit Microcontrollers to ARM® Cortex®-M
635(6)
22.2.1 Common Modifications
635(2)
22.2.2 Memory Requirements
637(1)
22.2.3 Nonapplicable Optimizations for 8-Bit or 16-Bit Microcontrollers
638(1)
22.2.4 Example---Migrate from 8051 to ARM Cortex-M0/Cortex-M0+
639(2)
22.3 Differences between ARM7TDMI™ and Cortex®-M0/M0+ Processor
641(4)
22.3.1 Overview of Classic ARM® Processors
641(1)
22.3.2 Operation Mode
642(1)
22.3.3 Registers
643(1)
22.3.4 Instruction Set
644(1)
22.3.5 Interrupts
644(1)
22.4 Porting Software from ARM7TDMI™ to the Cortex®-M0/Cortex-M0+ Processors
645(3)
22.4.1 Start-up Code and Vector Table
645(1)
22.4.2 Interrupt
645(1)
22.4.3 C Program Code
646(1)
22.4.4 Assembly Code
647(1)
22.4.5 Atomic Access
647(1)
22.4.6 Optimizations
647(1)
22.5 Differences between Various Cortex®-M Processors
648(8)
22.5.1 Overview
648(1)
22.5.2 Programmer's Model
649(1)
22.5.3 NVIC and Exceptions
650(3)
22.5.4 Instruction Set
653(1)
22.5.5 System Level Features
653(2)
22.5.6 Debug and Trace Features
655(1)
22.6 General Software Modifications when Porting between Cortex®-M Processors
656(1)
22.7 Porting Software between Cortex®-M0/M0+ and Cortex-M1
656(1)
22.8 Porting Software between Cortex®-M0/M0+ and Cortex-M3
657(2)
22.9 Porting Software between Cortex®-M0/M0+ and the Cortex-M4/M7 Processor
659(2)
Chapter 23 Advanced Topics
661(18)
23.1 Bit Data Handling in C Programming
661(2)
23.2 Startup Code in C
663(5)
23.3 Stack Overflow Detection
668(3)
23.3.1 What is Stack Overflow?
668(1)
23.3.2 Stack Analysis by Tool Chain
669(1)
23.3.3 Stack Analysis by Trial
669(1)
23.3.4 Stack Limit Using Memory Protection Unit
670(1)
23.3.5 Stack Checking in OS Context Switching
670(1)
23.4 Reentrant Interrupt Service Routine
671(2)
23.5 Semaphore Implementation
673(1)
23.6 Memory Ordering and Memory Barriers
674(5)
Appendix A Instruction Set Quick Reference 679(4)
Appendix B Exception Type Quick Reference 683(2)
Appendix C CMSIS-CORE Quick Reference 685(6)
Appendix D NVIC, SCB, and SysTick Registers Quick Reference 691(8)
Appendix E Debug Registers Quick Reference 699(12)
Appendix F Debug Connector Arrangements 711(4)
Appendix G Trouble Shooting 715(14)
Appendix H A Breadboard Project with an ARM® Cortex®-MO Microcontroller 729(4)
Index 733
Joseph Yiu joined ARM in 2001 and has been involved in a wide range of projects including development of ARM Cortex-M processors and various on-chip system level and debug components. In addition to in-depth knowledge of the processors and microcontroller system design, Joseph also has extensive knowledge in related areas including software development for the ARM Cortex-M microcontrollers, FPGA development and System-on-Chip design technologies.