Computer Organization: Basic Processor Structure [Pehme köide]

(Bowie State University MD USA)
  • Formaat: Paperback / softback, 372 pages, kõrgus x laius: 235x156 mm, kaal: 544 g, 74 Tables, black and white; 138 Illustrations, black and white
  • Ilmumisaeg: 23-Feb-2018
  • Kirjastus: Productivity Press
  • ISBN-10: 1498799515
  • ISBN-13: 9781498799515
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  • Formaat: Paperback / softback, 372 pages, kõrgus x laius: 235x156 mm, kaal: 544 g, 74 Tables, black and white; 138 Illustrations, black and white
  • Ilmumisaeg: 23-Feb-2018
  • Kirjastus: Productivity Press
  • ISBN-10: 1498799515
  • ISBN-13: 9781498799515
Teised raamatud teemal:
Computer Organization: Basic Processor Structure is a class-tested textbook, based on the author's decades of teaching the topic to undergraduate and beginning graduate students. The main questions the book tries to answer are: how is a processor structured, and how does the processor function, in a general-purpose computer? The book begins with a discussion of the interaction between hardware and software, and takes the reader through the process of getting a program to run. It starts with creating the software, compiling and assembling the software, loading it into memory, and running it. It then briefly explains how executing instructions results in operations in digit circuitry. The book next presents the mathematical basics required in the rest of the book, particularly, Boolean algebra, and the binary number system. The basics of digital circuitry are discussed next, including the basics of combinatorial circuits and sequential circuits. The bus communication architecture, used in many computer systems, is also explored, along with a brief discussion on interfacing with peripheral devices. The first part of the book finishes with an overview of the RTL level of circuitry, along with a detailed discussion of machine language. The second half of the book covers how to design a processor, and a relatively simple register-implicit machine is designed. ALSU design and computer arithmetic are discussed next, and the final two chapters discuss micro-controlled processors and a few advanced topics.
Introduction and Remarks xvii
Chapter 1 Overview 1(22)
1.1 High-Level, Assembly, And Machine Languages
2(3)
1.1.1 High-Level Languages
2(1)
1.1.2 Machine Language
3(1)
1.1.3 Assembly Language
4(1)
1.2 Compilers And Assembly Language
5(2)
1.2.1 Assembly Language Translation
5(1)
1.2.2 The Translation Process
6(1)
1.3 The Assembler And Object Code
7(3)
1.3.1 External References
7(2)
1.3.2 Compiler versus Assembler
9(1)
1.4 The Linker And Executable Code
10(2)
1.4.1 Resolving External References
10(1)
1.4.2 Searching Libraries
10(1)
1.4.3 Relocation
11(1)
1.5 The Loader
12(3)
1.5.1 Processes and Workspaces
13(1)
1.5.2 Initializing Registers
14(1)
1.6 Summary Of The Translation Process
15(1)
1.7 The Processor
15(4)
1.7.1 Processor Behavior
16(1)
1.7.2 Processor Structure
17(7)
1.7.2.1 The Data Path, Registers, and Computational Units
17(1)
1.7.2.2 Control Circuitry
18(1)
1.8 Digital Circuitry
19(2)
1.9 Summary
21(1)
1.10 Exercises
21(2)
Chapter 2 Number and Logic Systems 23(28)
2.1 Numbers
24(8)
2.1.1 Hexadecimal Numbers
26(1)
2.1.2 Adding Binary Numbers
27(1)
2.1.3 Representing Negative Integers
28(4)
2.2 Boolean Algebra
32(15)
2.2.1 Boolean Functions
32(2)
2.2.2 Boolean Expressions and Truth Tables
34(2)
2.2.3 Don't Care Conditions
36(1)
2.2.4 Boolean Simplification Using Identities
37(4)
2.2.4.1 Boolean Identities
38(1)
2.2.4.2 DeMorgan's Law
39(1)
2.2.4.3 Simplifying the XOR Function
39(1)
2.2.4.4 Example Simplification Using Identities
39(2)
2.2.5 Boolean Simplification Using Karnaugh-Maps
41(12)
2.2.5.1 K-Map for Functions of Two Variables
41(2)
2.2.5.2 K-Maps for Functions of Three Variables
43(3)
2.2.5.3 K-Maps for Functions of Four Variables
46(1)
2.2.5.4 Don't Care Conditions in Karnaugh-Maps
46(1)
2.2.5.5 K-Maps for Functions of More than Four Variables
47(1)
2.3 Summary
47(1)
2.4 Exercises
48(3)
Chapter 3 Digital Circuitry 51(44)
3.1 Combinational Circuits
53(14)
3.1.1 Designing with Logical Gates
53(4)
3.1.2 Common Combinational Circuits
57(10)
3.1.2.1 The Decoder
57(2)
3.1.2.2 The Encoder
59(2)
3.1.2.3 The Multiplexer
61(1)
3.1.2.4 MUX Composition
62(2)
3.1.2.5 The Adder
64(2)
3.1.2.6 The Ripple-Carry Adder
66(1)
3.2 Sequential Circuits
67(24)
3.2.1 The Clock
68(1)
3.2.2 Storage Devices
69(6)
3.2.2.1 The D-Type Storage Devices
69(1)
3.2.2.2 The D-Latch
70(2)
3.2.2.3 The D-Flip-Flop
72(1)
3.2.2.4 The J-K- Storage Device
73(1)
3.2.2.5 Flip-Flops with Extra Pins
73(2)
3.2.3 Sequential Design
75(9)
3.2.3.1 The FSM and State Diagrams
75(3)
3.2.3.2 The FSM and the State Transition Table
78(1)
3.2.3.3 State Diagrams and Transition Tables: Building One Representation from the Other
79(2)
3.2.3.4 Moore versus Mealy Machines
81(1)
3.2.3.5 Implementing a Sequential Design
81(3)
3.2.4 Sequential Circuit Analysis
84(1)
3.2.5 Common Sequential Circuits
85(12)
3.2.5.1 The Parallel-Load Register
86(1)
3.2.5.2 The Shift Register
87(1)
3.2.5.3 The Counter
88(1)
3.2.5.4 The Standard Register
89(2)
3.3 Summary
91(1)
3.4 Exercises
91(4)
Chapter 4 Devices and the Bus 95(34)
4.1 Memory
97(14)
4.1.1 Memory Operation
97(1)
4.1.2 Memory Types: ROM and RAM
98(2)
4.1.3 Memory Composition
100(3)
4.1.3.1 Horizontal Composition
100(1)
4.1.3.2 Vertical Composition
101(2)
4.1.4 Internal Memory Structure
103(2)
4.1.5 RAM Types
105(1)
4.1.6 ROM Types
106(2)
4.1.7 Word and Byte Addressing
108(2)
4.1.8 Machine Byte Order
110(1)
4.2 Peripheral Devices
111(6)
4.2.1 Peripheral Device Types
111(2)
4.2.2 Device Polling
113(1)
4.2.3 Interrupts
114(3)
4.3 THE CPU
117(1)
4.4 Bus Communication
118(6)
4.4.1 Bus Structure
118(2)
4.4.2 Bus Addressing
120(1)
4.4.3 Bus Addressing Example
121(3)
4.5 Summary
124(2)
4.6 Exercises
126(3)
Chapter 5 The Register Transfer Language Level 129(32)
5.1 Micro-Instructions As Circuits
130(9)
5.1.1 RTL Design
130(4)
5.1.2 A Larger Example
134(1)
5.1.3 RTL Analysis
135(1)
5.1.4 Transforming a Structural Description into a Behavioral Description
136(2)
5.1.5 Problems with Reverse Engineering
138(1)
5.2 Common Processor Micro-Instructions
139(7)
5.2.1 RTL Descriptions of Combinational Circuits
140(1)
5.2.2 RTL Descriptions of Sequential Circuits
140(1)
5.2.3 Processor Micro-Operations
141(5)
5.2.3.1 Arithmetic Micro-Operations
141(1)
5.2.3.2 Logic Micro-Operations
142(1)
5.2.3.3 Shift Micro-Operations
143(2)
5.2.3.4 Memory Access Micro-Operations
145(1)
5.3 Algorithmic Machines
146(6)
5.3.1 The Teapot Example
147(1)
5.3.2 Generating a Flowchart, and the Role of the Sequencer
148(2)
5.3.3 Generating RTL from the Flowchart
150(2)
5.4 RTL And Verilog
152(5)
5.5 Summary
157(1)
5.6 Exercises
158(3)
Chapter 6 Common Computer Architectures 161(60)
6.1 Instruction Set Architecture
163(18)
6.1.1 Data Transfer
164(2)
6.1.1.1 Register-to-Register Transfer
164(1)
6.1.1.2 Register-to-Memory Transfer
164(1)
6.1.1.3 Memory-to-Register Transfer
165(1)
6.1.1.4 Device Transfer
165(1)
6.1.2 Data Manipulation Instructions
166(6)
6.1.2.1 Common Data-Types
166(1)
6.1.2.2 The Integer Data-Type
166(1)
6.1.2.3 The Real Data-Type
167(1)
6.1.2.4 The Boolean Data-Type
168(1)
6.1.2.5 The Character Data-Type
168(1)
6.1.2.6 Binary Coded Decimal
169(1)
6.1.2.7 Data Manipulation Operation Types
170(1)
6.1.2.8 Arithmetic Operations
170(1)
6.1.2.9 Logic Operations
171(1)
6.1.2.10 Shift Operations
172(1)
6.1.3 Control Operations
172(11)
6.1.3.1 Unconditional Branches
173(1)
6.1.3.2 Conditional Branches
173(2)
6.1.3.3 Machine Reset Instructions
175(1)
6.1.3.4 Context Manipulation Instructions
175(6)
6.2 Instruction Format
181(2)
6.3 Addressing Modes
183(9)
6.3.1 Direct Mode
184(1)
6.3.2 Indirect Mode
184(1)
6.3.3 Register Direct Mode
185(1)
6.3.4 Register Indirect Mode
185(1)
6.3.5 Immediate Mode
185(1)
6.3.6 Implicit Mode
186(1)
6.3.7 Relative Mode
186(2)
6.3.8 Indexed Mode
188(2)
6.3.9 Addressing in Machine Language
190(2)
6.4 Alternate Machine Architectures
192(18)
6.4.1 The Register Machine
193(6)
6.4.1.1 Register Machine Instruction Format
194(3)
6.4.1.2 Register Machine Programming Example
197(2)
6.4.2 The Register Implicit Machine
199(4)
6.4.2.1 Register Implicit Machine Instruction Format
199(3)
6.4.2.2 Register Implicit Machine Programming Example
202(1)
6.4.3 The Accumulator Machine
203(3)
6.4.3.1 Accumulator Machine Instruction Format
204(1)
6.4.3.2 Accumulator Machine Programming Example
205(1)
6.4.4 The Stack Machine
206(4)
6.4.4.1 Stack Machine Instruction Format
208(1)
6.4.4.2 Stack Machine Programming Example
209(1)
6.5 ISA Design Issues
210(6)
6.5.1 Number of Registers
211(1)
6.5.2 Word Size
211(1)
6.5.3 Variable or Fixed-Length Instructions
212(1)
6.5.4 Memory Access
213(1)
6.5.5 Instruction Set Size
214(2)
6.5.5.1 RISC versus CISC Architectures
214(1)
6.5.5.2 Orthogonality and Completeness
215(1)
6.5.6 ISA
216(1)
6.6 The Brim Machine
216(1)
6.7 Summary
217(1)
6.8 Exercises
217(4)
Chapter 7 Hardwired CPU Design 221(44)
7.1 Register Implicit Machine Design
222(29)
7.1.1 The Data-Path
223(13)
7.1.1.1 Bus-Based Data-Path
223(8)
7.1.1.2 The ALU
231(3)
7.1.1.3 The Mode MUX
234(2)
7.1.2 The RIM Control Unit
236(15)
7.1.2.1 Fetching an Instruction
236(1)
7.1.2.2 Decoding an Instruction
237(1)
7.1.2.3 Executing an Instruction
237(3)
7.1.2.4 The CU Behavioral Description
240(9)
7.1.2.5 The Control Circuitry
249(2)
7.2 Control For Other Architectures
251(9)
7.2.1 Control for the Register Machine
251(3)
7.2.2 Control for the Accumulator Machine
254(3)
7.2.3 Control for the Stack Machine
257(3)
7.3 Summary
260(1)
7.4 Exercises
260(5)
Chapter 8 Computer Arithmetic 265(40)
8.1 Logic And Shift Operations
266(1)
8.2 Arithmetic Operations
267(33)
8.2.1 Unsigned and Signed Integers
267(2)
8.2.2 Unsigned Arithmetic
269(11)
8.2.2.1 Unsigned Addition
269(2)
8.2.2.2 Unsigned Subtraction
271(1)
8.2.2.3 Unsigned Multiplication
272(4)
8.2.2.4 Unsigned Division
276(4)
8.2.3 Signed Arithmetic
280(3)
8.2.3.1 Signed Addition and Subtraction
280(1)
8.2.3.2 Signed Multiplication and Division
281(2)
8.2.4 Floating-Point Data
283(17)
8.2.4.1 Converting between Floating-Point and Decimal
287(2)
8.2.4.2 Standardization
289(1)
8.2.4.3 Field Order
290(1)
8.2.4.4 Arithmetic Approximation
291(2)
8.2.4.5 Rounding
293(2)
8.2.4.6 Floating-Point Addition
295(3)
8.2.4.7 Floating-Point Multiplication
298(2)
8.3 Summary
300(2)
8.3.1 Wallace Trees
301(1)
8.3.2 ROM Lookup Tables
301(1)
8.3.3 Arithmetic Pipelines
302(1)
8.4 Exercises
302(3)
Chapter 9 Micro-Programmed CPU Design 305(30)
9.1 Micro-Instruction Format
307(4)
9.1.1 The Sequence Field
308(1)
9.1.2 The Select and Address Subfields, and the Address Selector
309(2)
9.2 Micro-Architectures
311(8)
9.2.1 Direct Control
313(1)
9.2.2 Horizontal Control
314(2)
9.2.3 Vertical Control
316(3)
9.3 Micro-Control For The Brim Machine
319(10)
9.3.1 The BRIM Micro-Program
320(5)
9.3.2 The BRIM Jump-Table and Mapper
325(2)
9.3.3 The µDec
327(2)
9.4 Summary
329(3)
9.4.1 Ease of Processor Modification
330(1)
9.4.2 Complexity of the Processor Circuitry
331(1)
9.4.3 Speed of Machine Instruction Execution
331(1)
9.5 Exercises
332(3)
Chapter 10 A Few Last Topics 335(30)
10.1 Decreasing Execution Time
336(16)
10.1.1 Cache Memory
336(8)
10.1.1.1 Direct Mapped Cache
337(5)
10.1.1.2 Writing to Cache
342(1)
10.1.1.3 Cache Performance
343(1)
10.1.2 Instruction Pipelining
344(8)
10.1.2.1 Problems with Pipelines
348(2)
10.1.2.2 Pipeline Performance
350(2)
10.2 Increasing Memory Space
352(10)
10.2.1 The Memory Hierarchy
352(2)
10.2.2 Virtual Memory
354(6)
10.2.2.1 Paging
354(4)
10.2.2.2 Page Replacement
358(1)
10.2.2.3 Disk Access
359(1)
10.2.2.4 Memory Protection
360(1)
10.3 Summary
360(2)
10.3.1 I/O Structure
361(1)
10.3.2 Parallel Architectures
362(1)
10.4 Exercises
362(3)
Suggested Readings 365(2)
Index 367
James Gil de Lamadrid has a PhD in Computer Science from the University of Minnesota. He has been a professor in Computer Science at Bowie State University since 2004.

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