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Arbitrary Modeling of TSVs for 3D Integrated Circuits 2015 ed. [Kõva köide]

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  • Formaat: Hardback, 179 pages, kõrgus x laius: 235x155 mm, kaal: 4144 g, 99 Illustrations, color; 60 Illustrations, black and white; IX, 179 p. 159 illus., 99 illus. in color., 1 Hardback
  • Sari: Analog Circuits and Signal Processing
  • Ilmumisaeg: 05-Sep-2014
  • Kirjastus: Springer International Publishing AG
  • ISBN-10: 3319076108
  • ISBN-13: 9783319076102
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Arbitrary Modeling of TSVs for 3D Integrated Circuits 2015 ed.Suurem pilt
  • Formaat: Hardback, 179 pages, kõrgus x laius: 235x155 mm, kaal: 4144 g, 99 Illustrations, color; 60 Illustrations, black and white; IX, 179 p. 159 illus., 99 illus. in color., 1 Hardback
  • Sari: Analog Circuits and Signal Processing
  • Ilmumisaeg: 05-Sep-2014
  • Kirjastus: Springer International Publishing AG
  • ISBN-10: 3319076108
  • ISBN-13: 9783319076102
Teised raamatud teemal:
Püsilink: https://www.kriso.ee/db/9783319076102.html
Märksõnad:
This book presents a wide-band and technology independent, SPICE-compatible RLC model for through-silicon vias (TSVs) in 3D integrated circuits. This model accounts for a variety of effects, including skin effect, depletion capacitance and nearby contact effects. Readers will benefit from in-depth coverage of concepts and technology such as 3D integration, Macro modeling, dimensional analysis and compact modeling, as well as closed form equations for the through silicon via parasitics. Concepts covered are demonstrated by using TSVs in applications such as a spiral inductor and inductive-based communication system and bandpass filtering.
1 Introduction: Work Around Moore's Law
1(16)
1.1 Scaling Limitations of Conventional Integration Technology: Work Around Moore's Law
1(13)
1.1.1 More Moore: New Architectures
4(2)
1.1.2 More Moore: New Materials
6(1)
1.1.3 More than Moore (MTM): New Interconnects Schemes
7(3)
1.1.4 Beyond CMOS: New Devices
10(4)
1.2 Book Organization
14(3)
References
14(3)
2 3D/TSV-Enabling Technologies
17(32)
2.1 3D/TSV Technology
17(6)
2.2 TSV Structure
23(4)
2.3 Modeling and Design Challenges for 3D-ICs
27(17)
2.3.1 Electrical Modeling Challenges
28(1)
2.3.2 Thermal Management Challenges
29(1)
2.3.3 CAD Tools Challenges
29(8)
2.3.4 Technological, Yield, and Test Challenges
37(2)
2.3.5 Design Methodology Challenges
39(2)
2.3.6 Circuit Architecture Challenges
41(2)
2.3.7 Power Delivery and Clock Distribution Challenges
43(1)
2.4 Summary
44(5)
References
45(4)
3 TSV Modeling and Analysis
49(36)
3.1 Introduction
49(1)
3.2 Modeling Methodology
50(27)
3.2.1 EM Modeling Methods
53(1)
3.2.2 Physics-Based Lumped Element Model for TSVs
53(1)
3.2.3 Nonlinearities (MOS Effect) of a TSV
54(4)
3.2.4 Comparison Between Quasi-Static and Full-Wave EM Simulations
58(1)
3.2.5 Dimensional Analysis Theory
59(1)
3.2.6 Closed-Form Expressions for TSV Model Elements Using Dimensional Analysis
60(17)
3.3 TSV Model Linearization
77(3)
3.4 Summary
80(5)
References
82(3)
4 TSV Verification
85(10)
4.1 Validation Against Electromagnetic Simulation: Frequency Domain and Time Domain
86(1)
4.2 Studying the TSV Impact on Circuit Performance
87(4)
4.3 Validation Against Device Simulation
91(2)
4.4 Summary
93(2)
References
94(1)
5 TSV Macro-Modeling Framework
95(8)
5.1 TSV Macro-Modeling Framework: Analysis and Verification
95(2)
5.2 Multi-Stacked TSV
97(2)
5.3 Summary
99(4)
References
101(2)
6 TSV Design Applications: TSV-Based On-Chip Spiral Inductor, TSV-Based On-Chip Wireless Communications, and TSV-Based Bandpass Filter
103(30)
6.1 Introduction: TSV-Based On-Chip Spiral Inductor
104(4)
6.2 TSV-Based Spiral Architecture and Analysis
108(8)
6.2.1 The TSV-Based Spiral Inductor: Analysis and Characterization
109(1)
6.2.2 Lumped Element Model for the TSV-Based Spiral Inductor and Derivation of Qmax
109(5)
6.2.3 Closed-Form Expressions for the Inductance
114(2)
6.3 TSV-Based Spiral Verification
116(2)
6.3.1 Validation Against EM Simulation
116(1)
6.3.2 Comparison with Related Work
116(2)
6.4 Introduction: TSV-Based On-Chip Wireless Communications
118(2)
6.5 The Wireless TSV Architecture
120(3)
6.5.1 The Wireless TSV: Architecture and Analysis
120(1)
6.5.2 EM Simulation Results and Discussions
121(1)
6.5.3 Closed-Form Expressions
122(1)
6.6 Wireless TSV Verification
123(2)
6.7 Resonance Wireless Communication
125(1)
6.8 Introduction: TSV-Based Bandpass Filter
126(1)
6.9 Simulation Results
126(1)
6.10 Summary
126(7)
References
129(4)
7 Imperfection in TSV Modeling
133(16)
7.1 Analysis of Coupling Capacitance Between TSVs and Metal Interconnects in 3D-ICs
133(3)
7.2 Analysis of Coupling Capacitance Between TSVs and Active Devices in 3D-ICs
136(5)
7.3 Effect of Nonuniform Substrate-Doping Profile on the Electrical Performance of a TSV
141(3)
7.4 Summary
144(5)
References
146(3)
8 New Trends in TSV
149(14)
8.1 Performance Comparison Between Air-Gap-Based Coaxial TSV and Conventional Circular TSV
149(1)
8.2 Characterization of SW-CNT-Based TSV
150(5)
8.3 Adiabatic TSV
155(6)
8.3.1 Adiabatic Theory
155(2)
8.3.2 Adiabatic Architecture for 3D Integration
157(4)
8.4 Simulations and Comparison with CMOS
161(1)
8.5 Summary
161(2)
References
161(2)
9 TSV Fabrication
163(10)
9.1 TSV Fabrication Process Overview
163(5)
9.1.1 Stacking
163(1)
9.1.2 Bonding
164(1)
9.1.3 TSV Formation
165(2)
9.1.4 Alignment
167(1)
9.1.5 Thinning
167(1)
9.2 The Fabrication Process Flow
168(3)
9.2.1 TSV Etching
168(1)
9.2.2 Oxide Deposition
168(1)
9.2.3 TSV Filling
168(1)
9.2.4 Substrate Thinning
169(2)
9.3 Summary
171(2)
References
171(2)
10 Conclusions
173(4)
Index 177