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E-raamat: Defect-Oriented Testing for Nano-Metric CMOS VLSI Circuits

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Failures of nano-metric technologies owing to defects and shrinking process tolerances give rise to significant challenges for IC testing. As the variation of fundamental parameters such as channel length, threshold voltage, thin oxide thickness and interconnect dimensions goes well beyond acceptable limits, new test methodologies and a deeper insight into the physics of defect-fault mappings are needed. In Defect-Oriented Testing for Nano-Metric CMOS VLSI Circuits state of the art of defect-oriented testing is presented from both a theoretical approach as well as from a practical point of view. Step-by-step handling of defect modeling, defect-oriented testing, yield modeling and its usage in common economics practices enables deeper understanding of concepts.The progression developed in this book is essential to understand new test methodologies, algorithms and industrial practices. Without the insight into the physics of nano-metric technologies, it would be hard to develop system-level test strategies that yield a high IC fault coverage. Obviously, the work on defect-oriented testing presented in the book is not final, and it is an evolving field with interesting challenges imposed by the ever-changing nature of nano-metric technologies. Test and design practitioners from academia and industry will find that Defect-Oriented Testing for Nano-Metric CMOS VLSI Circuits lays the foundations for further pioneering work.

The 2nd edition of defect oriented testing has been extensively updated. New chapters on Functional, Parametric Defect Models and Inductive fault Analysis and Yield Engineering have been added to provide a link between defect sources and yield. The chapter on RAM testing has been updated with focus on parametric and SRAM stability testing. Similarly, newer material has been incorporated in digital fault modeling and analog testing chapters. The strength of Defect Oriented Testing for nano-Metric CMOS VLSIs lies in its industrial relevance.
Dedication v
Preface xiii
Foreword xvii
Foreword for the First Edition xix
Acknowledgements xxi
Chapter
1. Introduction		 1
1. Evolution of CMOS Technology
1
2. The Test Complexity
5
3. Quality and Reliability Awareness
9
4. Building Quality and Reliability
11
5. Objectives of this Book
15
6. Book Organization
16
Chapter
2. Functional and Parametric Defect Models		 23
1. Brief Classification of Defects
23
1.1 Defect-Fault Relationship
26
2. Inductive Fault Analysis
28
2.1 IC Design and Layout Related Defect Sensitivity
29
2.2 Defect Sensitive Design
29
2.3 Basic Concepts of IFA
30
3. Parametric Defect and Fault Models
32
3.1 Threshold Voltage Mismatch (ΔVt) Fault Modeling
32
3.2 Sources of Threshold Voltage Variability
33
3.3 Leakage Current due to Vt Mismatch
34
3.4 Delay in Parallel-connected Networks
39
3.5 Delay Variation Model with ΔVt for Parallel Transistor Networks
41
3.6 Spot Defect Statistics: Resistive Opens
45
4. Functional Defect Models
50
4.1 Critical Areas
53
4.2 Defect Statistics
54
4.3 Average Probability of Failure of Long Interconnects
58
4.4 Average Critical Area of N Conductors
61
5. Conclusions
64
Chapter
3. Digital CMOS Fault Modeling		 69
1. Objectives of Fault Modeling
69
2. Levels of Testing
71
3. Levels of Fault Modeling
73
3.1 Logic Level Fault Modeling
73
3.2 Transistor Level Fault Modeling
81
3.3 Layout Level Fault Modeling
90
3.4 Function Level Fault Modeling
91
3.5 Delay Fault Models
92
3.6 Leakage Fault Model
97
3.7 Temporary Faults
98
4. Conclusions
102
Chapter
4. Defects in Logic Circuits and their Test Implications		 111
1. Introduction
111
2. Stuck-at Faults and Manufacturing Defects
113
2.1 Study by Galiay, Crouzet and Vergniault
114
2.2 Study by Banerjee and Abraham
115
2.3 Study by Maly, Ferguson and Shen
120
2.4 Gate Oxide Shorts: Study by Hawkins and Soden
123
3. IFA Experiments on Standard Cells
126
4. IDDQ versus Voltage Testing
130
5. Defects in Sequential Circuits
133
5.1 Undetected Defects
135
5.2 Defect Detection Technique
137
5.3 IDDQ Testable Flip-flop
139
5.4 Defects and Scan Chains
139
6. Defect Classes and their Testing
143
7. Application of IFA in Nano-metric Technologies
143
8. Conclusions
146
Chapter
5. Testing Defects and Parametric Variations in RAMs		 151
1. Introduction
151
2. Traditional RAM Fault Models
153
2.1 Stuck-at Fault Model
153
2.2 Coupling Fault Model
154
2.3 Pattern Sensitivity Fault Model
154
3. Defect Based RAM Fault Model Development
155
3.1 Defect based SRAM Fault Models and Test Algorithms
155
3.2 Subsequent Defect-oriented SRAM Test Development
160
3.3 Defect based DRAM Fault Models and Test Algorithms
163
3.4 TCAM Fault Models and Test Algorithms
176
4. Address Decoder Defects
185
4.1 Early Work on Address Decoder Faults
187
4.2 Technological Differences
187
4.3 Failure and Analysis
189
4.4 Why Non-detection by March Tests?
192
4.5 Address Decoder Open Defects
193
4.6 Supplementary Test Algorithm
195
4.7 Testability Techniques for Decoder Open Defects
197
4.8 Recent Work on Address Decoder Defects
200
5. Parametric Testing of SRAMs
200
5.1 SRAM Cell and SNM
203
5.2 Process Variation and SNM
207
5.3 Manufacturing Defects and SNM
209
5.4 Weak Cell Fault Model
210
5.5 DfT Techniques to Detect Weak Cells
211
6. IDDQ Based RAM Testing
215
7. Conclusions
215
Chapter
6. Defect-oriented Analog Testing		 225
1. Introduction
226
2. Analog Test Complexity
227
3. Previous Work
228
3.1 Estimation Method
228
3.2 Topological Method
228
3.3 Taxonomical Method
230
4. Defect Based Realistic Fault Dictionary
230
4.1 Implementation
234
5. A Case Study
240
5.1 Fault Matrix Generation
240
5.2 Stimuli Matrix
242
5.3 Simulation Results
243
5.4 Silicon Results
244
5.5 Observations and Analysis
248
5.6 IFA: Strengths and Weaknesses
249
6. Input Stimuli Generation
251
6.1 Power Supply Ramp Input Test Stimuli
252
6.2 Amplifier Specs
254
6.3 Structural vs. Functional Fault Coverage
259
6.4 Experimental Results
264
7. IFA Based Fault Grading and DfT for Analog Circuits
268
7.1 A/D Converter Testing
268
7.2 Description of the Experiment
269
7.3 Fault Simulation Issues
270
7.4 Fault Simulation Results
272
8. High Level Analog Fault Models
278
9. Conclusions
281
Chapter
7. Yield Engineering		 289
1. Mathematical Models for Yield Prediction
289
1.1 Layout Oriented Yield Prediction
300
2. Yield Engineering
301
3. Economics and Yield Forecasting
306
4. Conclusions
312
Chapter
8. Conclusion		 317
1. Test and Yield Engineering Complexity in Nano-metric Technologies
317
2. Role of Defect-oriented Testing
320
2.1 Strengths of Defect-oriented Testing
320
2.2 Limitations of Defect-oriented Testing
321
3. Future Directions
321
Index 325


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