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E-raamat: Industry Standard FDSOI Compact Model BSIM-IMG for IC Design

, (TSMC Distinguished Chair Professor Emeritus, University of California Berkeley, USA), , (Chair Professor, Department of Electrical Engineering, Indian Institute of Technolo), (Associate Professor, Macquarie University, Sydney, Australia), , ,
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Industry Standard FDSOI Compact Model BSIM-IMG for IC Design helps readers develop an understanding of a FDSOI device and its simulation model. It covers the physics and operation of the FDSOI device, explaining not only how FDSOI enables further scaling, but also how it offers unique possibilities in circuits. Following chapters cover the industry standard compact model BSIM-IMG for FDSOI devices. The book addresses core surface-potential calculations and the plethora of real devices and potential effects. Written by the original developers of the industrial standard model, this book is an excellent reference for the new BSIM-IMG compact model for emerging FDSOI technology.

The authors include chapters on step-by-step parameters extraction procedure for BSIM-IMG model and rigorous industry grade tests that the BSIM-IMG model has undergone. There is also a chapter on analog and RF circuit design in FDSOI technology using the BSIM-IMG model.

  • Provides a detailed discussion of the BSIM-IMG model and the industry standard simulation model for FDSOI, all presented by the developers of the model
  • Explains the complex operation of the FDSOI device and its use of two independent control inputs
  • Addresses the parameter extraction challenges for those using this model
List of Contributors
ix
1 Fully-Depleted Silicon on Oxide Transistor and Compact Model
1(14)
Chenming Hu
1.1 Silicon on Oxide and Pre-2010 SOI CMOS Transistor
1(2)
1.2 What Limits the Scaling of the Bulk and PDSOI CMOS Transistors?
3(2)
1.3 The Ultrathin-Body Concept and Ultrathin-Body Fully Depleted SOI
5(4)
1.4 Comparison of FDSOI with FinFET and Other Ultrathin-Body Transistors
9(1)
1.5 Compact Model--The Bridge Between FDSOI Device/Technology and IC Design
10(5)
References
13(2)
2 Core Model for Independent Multigate MOSFETs
15(20)
Juan Pablo Duarte
Sourabh Khandelwal
Huan-Lin Chang
Yen-Kai Lin
Pragya Kushwaha
Yogesh Singh Chauhan
Chenming Hu
2.1 Introduction
15(1)
2.2 Independent Multigate MOSFETs
16(2)
2.3 Core Model
18(8)
2.4 Core Model Analytical Solution
26(2)
2.5 Drain Current Model
28(5)
2.6 Terminal Charge Model 30 References
33(2)
3 Channel Current Model With Real Device Effects in BSIM-IMG
35(30)
Sourabh Khandelwal
3.1 Introduction
35(1)
3.2 Vertical Field Dependence of Carrier Mobility
35(4)
3.3 Threshold Voltage
39(12)
3.4 Drain Saturation Voltage
51(5)
3.5 Quantum Mechanical Effects
56(1)
3.6 Lateral Nonuniform Doping Model
57(1)
3.7 Output Conductance Model
57(2)
3.8 Velocity Saturation Effect
59(1)
3.9 Series Resistance Model
60(2)
3.10 Channel Current Expression
62(3)
References
62(3)
4 Leakage Current and Thermal Effects
65(24)
Sourabh Khandelwal
Pragya Kushwaha
4.1 Leakage Currents and Their Modeling
65(7)
4.2 Thermal Effects and Their Modeling
72(17)
References
86(3)
5 Model for Terminal Charges and Capacitances in BSIM-IMG
89(18)
Sourabh Khandelwal
5.1 Introduction
89(1)
5.2 Capacitance Calculation From Terminal Charges
90(3)
5.3 Intrinsic Terminal Charge Model in BSIM-IMG
93(5)
5.4 Modeling the Impact of Real Device Effects on Terminal Charges
98(4)
5.5 Extrinsic Capacitance Model in BSIM-IMG
102(5)
References
105(2)
6 Parameter Extraction With BSIM-IMG Compact Model
107(18)
Harshit Agarwal
6.1 Background
107(2)
6.2 Extraction of Large-Sized Device Parameters
109(5)
6.3 Short-Channel Device Extraction and Length Scaling
114(2)
6.4 Leakage Current Extraction
116(4)
6.5 Extraction of Temperature Dependence Parameters
120(5)
References
123(2)
7 Testing BSIM-IMG Model Quality
125(20)
Harshit Agarwal
7.1 Symmetry Tests
125(5)
7.2 Weak and Strong Inversion Test
130(4)
7.3 Test for Self-Heating Effect
134(2)
7.4 Model Validation With Germanium on Insulator FD-SOI Transistor
136(9)
References
143(2)
8 High-Frequency and Noise Models in BSIM-IMG
145(56)
Pragya Kushwaha
Yogesh Singh Chauhan
8.1 Radio-Frequency Characterization
146(4)
8.2 Radio-Frequency Modeling and Parameter Extraction
150(9)
8.3 Noise Models
159(7)
8.4 Thermal Noise Characterization
166(5)
8.5 Model Validation
171(8)
8.6 Induced Gate Thermal Noise Model
179(11)
8.7 Appendix
190(11)
References
193(8)
Index 201
Chenming Hu is TSMC Distinguished Chair Professor Emeritus at the University of California Berkeley, United States. He was the Chief Technology Officer of TSMC. He received the US Presidential Medal of Technology and Innovation from Pres. Barack Obama for developing the first 3D thin-body transistor FinFET, MOSFET reliability models and leading the development of BSIM industry standard transistor model that is used in designing most of the integrated circuits in the world. He is a member of the US Academy of Engineering, the Chinese Academy of Science, and Academia Sinica. He received the highest honor of IEEE, the IEEE Medal of Honor, and its Andrew Grove Award, Solid Circuits Award, and the Nishizawa Medal. He also received the Taiwan Presidential Science Prize and UC Berkeleys highest honor for teaching the Berkeley Distinguished Teaching Award.

Sourabh Khandelwal is an Associate Professor at Macquarie University. He is the lead author of two industry standard compact models: ASM-HEMT for GaN RF and power technology, and ASM-ESD for silicon ESD applications. He has also co-authored BSIM-CMG, BSIM-IMG and BSIM6 compact models during his tenure at the BSIM group at the University of California Berkeley. Dr Khandelwal has published 3 books and over 150 research papers. He regularly serves as consultant to multi-national semiconductor companies.

Yogesh Singh Chauhan is a Chair Professor in the Department of Electrical Engineering at the Indian Institute of Technology Kanpur, India. He is the developer of several industry standard models: ASM-HEMT, BSIM-BULK (formerly BSIM6), BSIM-CMG, BSIM-IMG, BSIM4 and BSIM-SOI models. His research group is involved in developing compact models for GaN transistors, FinFET, nanosheet/gate-all-around FETs, FDSOI transistors, negative capacitance FETs and 2D FETs. His research interests are RF characterization, modeling, and simulation of semiconductor devices.

Director of RF Innovation at Globalfoundries, USA Principal Member of Technical Staff at Globalfoundries USA Juan Pablo Duarte Sepúlveda obtained his Ph.D. at the University of California, Berkeley in 2018. He received his B.Sc. in 2010 and his M.Sc. in 2012, both in electrical engineering from the Korea Advanced Institute of Science and Technology (KAIST). He held a position as a lecturer at the Universidad Tecnica Federico Santa Maria, Valparaiso, Chile, in 2012. He has authored many papers on nanoscale semiconductor device modeling and characterization. He received the Best Student Paper Award at the 2013 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD) for the paper: Unified FinFET Compact Model: Modelling Trapezoidal Triple-Gate FinFETs.

Pragya Kushwaha is currently a Postdoctoral Researcher with Prof. Chenming Hu in the BSIM Device Modeling Group at University of California, Berkeley. She received her PhD degree from Indian Institute of Technology Kanpur, India in 2017. She has authored several national and international research papers in the area of semiconductor device modeling and characterization. During her PhD, she has developed a complete RF compact model for FDSOI transistors under the frame work of industry standard BSIM-IMG compact model. Her current research interests include modeling, simulation, and characterization of advanced semiconductor devices such as nanowires, NCFETs, PD/FDSOIs, FinFETs, tunnel FETs, high-voltage FETs, and bulk MOSFETs. Harshit Agarwal received the PhD degree from Indian Institute of Technology Kanpur, India in 2017. He is currently working as center manager and post-doc fellow at Berkeley Device Modeling Centre, BSIM group, University of California Berkeley, Berkeley, USA. He has been involved in the development of multi-gate and bulk MOSFET models. He is also involved in the modeling and characterization of advanced steep sub-threshold slope devices like negative capacitance FETs, tunnel FET etc. He has authored several papers in the field of semiconductor device modeling, simulation and characterization.