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Microarchitecture of Network-on-Chip Routers: A Designer's Perspective 2015 ed. [Kõva köide]

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  • Formaat: Hardback, 175 pages, kõrgus x laius: 235x155 mm, kaal: 4492 g, 77 Illustrations, color; 57 Illustrations, black and white; XIV, 175 p. 134 illus., 77 illus. in color., 1 Hardback
  • Ilmumisaeg: 27-Aug-2014
  • Kirjastus: Springer-Verlag New York Inc.
  • ISBN-10: 1461443008
  • ISBN-13: 9781461443001
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Microarchitecture of Network-on-Chip Routers: A Designer's Perspective 2015 ed.Suurem pilt
  • Formaat: Hardback, 175 pages, kõrgus x laius: 235x155 mm, kaal: 4492 g, 77 Illustrations, color; 57 Illustrations, black and white; XIV, 175 p. 134 illus., 77 illus. in color., 1 Hardback
  • Ilmumisaeg: 27-Aug-2014
  • Kirjastus: Springer-Verlag New York Inc.
  • ISBN-10: 1461443008
  • ISBN-13: 9781461443001
Teised raamatud teemal:
Püsilink: https://www.kriso.ee/db/9781461443001.html
Märksõnad:
This book offers an overview of network-on-chip router micro-architecture, the corresponding design opportunities and challenges, and existing solutions to overcome these challenges. Includes examples that highlight both regular and worst-case scenarios.

This book provides a unified overview of network-on-chip router micro-architecture, the corresponding design opportunities and challenges, and existing solutions to overcome these challenges. The discussion focuses on the heart of a NoC, the NoC router, and how it interacts with the rest of the system. Coverage includes both basic and advanced design techniques that cover the entire router design space including router organization, flow control, pipelined operation, buffering architectures, as well as allocators’ structure and algorithms. Router micro-architectural options are presented in a step-by-step manner beginning from the basic design principles. Even highly sophisticated design alternatives are categorized and broken down to simpler pieces that can be understood easily and analyzed. This book is an invaluable reference for system, architecture, circuit, and EDA researchers and developers, who are interested in understanding the overall picture of NoC routers' architecture, the associated design challenges, and the available solutions.
1 Introduction to Network-on-Chip Design 1(10)
1.1 The Physical Medium
2(2)
1.2 Flow Control
4(1)
1.3 Read—Write Transactions
5(1)
1.4 Transactions on the Network: The Transport Layer
6(3)
1.4.1 Network Interfaces
6(2)
1.4.2 The Network: The Physical Layer
8(1)
1.5 Putting It All Together
9(1)
1.6 Take-Away Points
10(1)
2 Link-Level Flow Control and Buffering 11(26)
2.1 Elastic Buffers
12(6)
2.1.1 Half-Bandwidth Elastic Buffer
13(2)
2.1.2 Full-Bandwidth 2-Slot Elastic Buffer
15(1)
2.1.3 Alternative Full-Throughput Elastic Buffers
16(2)
2.2 Generic FIFO Queues
18(2)
2.3 Abstract Flow Control Model
20(1)
2.4 Credit-Based Flow Control
21(1)
2.5 Pipelined Data Transfer and the Round-Trip Time
22(9)
2.5.1 Pipelined Links with Ready/Valid Flow Control
24(3)
2.5.2 Pipelined Links with Elastic Buffers
27(1)
2.5.3 Pipelined Links and Credit-Based Flow Control
28(3)
2.6 Request—Acknowledge Handshake and Bufferless Flow Control
31(1)
2.7 Wide Message Transmission
32(3)
2.8 Take-Away Points
35(2)
3 Baseline Switching Modules and Routers 37(24)
3.1 Multiple Inputs Connecting to One Output
38(7)
3.1.1 Credit-Based Flow Control at the Output Link
41(1)
3.1.2 Granularity of Buffer Allocation
42(1)
3.1.3 Hierarchical Switching
43(2)
3.2 The Reverse Connection: Splitting One Source to Many Receivers
45(1)
3.3 Multiple Inputs Connecting to Multiple Outputs Using a Reduced Switching Datapath
46(3)
3.3.1 Credit-Based Flow Control at the Output Link
47(1)
3.3.2 Adding More Switching Elements
48(1)
3.4 Multiple Inputs Connecting to Multiple Outputs Using an Unrolled Switching Datapath
49(3)
3.5 Head-of-Line Blocking
52(1)
3.6 Routers in the Network: Routing Computation
53(5)
3.6.1 Lookahead Routing Computation
55(3)
3.7 Hierarchical Switching
58(1)
3.8 Take-Away Points
59(2)
4 Arbitration Logic 61(12)
4.1 Fixed Priority Arbitration
61(4)
4.1.1 Generation of the Grant Signals
63(2)
4.2 Round-Robin Arbitration
65(3)
4.2.1 Merging Round-Robin Arbitration with Multiplexing
67(1)
4.3 Arbiters with 2D Priority State
68(3)
4.3.1 Priority Update Policies
69(2)
4.4 Take-Away Points
71(2)
5 Pipelined Wormhole Routers 73(20)
5.1 Review of Single-Cycle Router Organization
75(2)
5.1.1 Credit Consume and State Update
76(1)
5.1.2 Example of Packet Flow in the Single-Cycle Router
76(1)
5.2 The Routing Computation Pipeline Stage
77(5)
5.2.1 Idle-Cycle Free Operation of the RC Pipeline Stage
80(2)
5.3 The Switch Allocation Pipeline Stage
82(6)
5.3.1 Elementary Organization
82(2)
5.3.2 Alternative Organization of the SA Pipeline Stage
84(2)
5.3.3 Idle-Cycle Free Operation of the SA Pipeline Stage
86(2)
5.4 Pipelined Routers with RC and SA Pipeline Stages
88(3)
5.4.1 Pipelining the Router Only in the Control Path
88(1)
5.4.2 Pipelining the Router in the Control and the Datapath
89(2)
5.5 Take-Away Points
91(2)
6 Virtual-Channel Flow Control and Buffering 93(18)
6.1 The Operation of Virtual-Channel Flow Control
94(3)
6.2 Virtual-Channel Buffers
97(2)
6.3 Buffer Sharing
99(6)
6.3.1 The Organization and Operation of a Generic Shared Buffer
101(2)
6.3.2 Primitive Shared Buffer for VCs: ElastiStore
103(2)
6.4 VC Flow Control on Pipelined Links
105(4)
6.4.1 Pipelined Links with VCs Using Ready/Valid Flow Control
106(2)
6.4.2 Pipelined Links with VCs Using Credit-Based Flow Control
108(1)
6.5 Take-Away Points
109(2)
7 Baseline Virtual-Channel Based Switching Modules and Routers 111(24)
7.1 Many to One Connection with VCs
111(10)
7.1.1 State Variables Required Per-Input and Per-Output VC
112(1)
7.1.2 Request Generation for the VC Allocator
113(2)
7.1.3 Request Generation for the Switch Allocator
115(2)
7.1.4 Gathering Grants and Moving to the Output
117(1)
7.1.5 The Internal Organization of the VC Allocator for a Many-to-One Connection
117(2)
7.1.6 The Internal Organization of the Switch Allocator for a Many-to-One Connection
119(2)
7.1.7 Output-First Allocation
121(1)
7.2 Many-to-Many Connections Using an Unrolled Datapath: A Complete VC-Based Router
121(10)
7.2.1 Routing Computation
122(1)
7.2.2 Requests to VC the Allocator
123(1)
7.2.3 Requests to the Switch Allocator
123(3)
7.2.4 Gathering Grants and Moving to the Output
126(1)
7.2.5 The Internal Organization of the VC Allocator for a VC-Based Router
127(2)
7.2.6 The Internal Organization of the Switch Allocator for a VC-Based Router
129(2)
7.3 VA and SA Built with Centralized Allocators
131(2)
7.4 Take-Away Points
133(2)
8 High-Speed Allocators for VC-Based Routers 135(14)
8.1 Virtual Networks: Reducing the Complexity of VC Allocation
136(1)
8.2 Lookahead VA1
137(1)
8.3 VC Allocation Without VA2: Combined Allocation
138(3)
8.3.1 Combined Allocation with VA1 in Series to SA
139(1)
8.3.2 Combined Allocation with VA1 in Parallel to SA
139(2)
8.3.3 Combined Allocation with Lookahead VA1
141(1)
8.4 Speculative Switch Allocation
141(4)
8.4.1 Handling the Speculative and the Non-speculative Grants
143(2)
8.5 VC-Based Routers with Input Speedup
145(2)
8.6 Take-Away Points
147(2)
9 Pipelined Virtual-Channel-Based Routers 149(22)
9.1 Review of Single-Cycle VC-Based Router Organization
150(3)
9.1.1 Example 1: Two Packets Arriving at the Same Input VC
151(1)
9.1.2 Example 2: Two Packets Arriving at Different Input VCs
152(1)
9.2 The Routing Computation Pipeline Stage
153(4)
9.2.1 Pipelining the Router Only in the Control Path
154(1)
9.2.2 Pipelining the Router in the Control and the Data Path
155(2)
9.3 The VC Allocation Pipeline Stage
157(4)
9.3.1 Example 1: Two Packets Arriving at the Same Input VC
158(1)
9.3.2 Example 2: Two Packets Arriving at Different Input VCs
159(1)
9.3.3 Obstactes in Removing the Deficiency of the VA Pipeline Stage
160(1)
9.4 The Switch Allocation Pipeline Stage
161(2)
9.4.1 Credit Consume and State Update
162(1)
9.5 Multi-stage Pipelined Organizations for VC-Based Routers
163(6)
9.5.1 Three-Stage Pipelined Organization: RC|VA|SA—ST
164(2)
9.5.2 Three-Stage Pipelined Organization: RC—VA|SA|ST
166(1)
9.5.3 Four-Stage Pipelined Organization: RC|VA|SA|ST
167(2)
9.6 Take-Away Points
169(2)
References 171