Muutke küpsiste eelistusi

E-raamat: Modeling, Analysis and Optimization of Network-on-Chip Communication Architectures

,
Teised raamatud teemal:
  • Formaat - PDF+DRM
  • Hind: 110,53 €*
  • * hind on lõplik, st. muud allahindlused enam ei rakendu
  • Lisa ostukorvi
  • Lisa soovinimekirja
  • See e-raamat on mõeldud ainult isiklikuks kasutamiseks. E-raamatuid ei saa tagastada.
Modeling, Analysis and Optimization of Network-on-Chip Communication ArchitecturesSuurem pilt
Teised raamatud teemal:

DRM piirangud

  • Kopeerimine (copy/paste):

    ei ole lubatud

  • Printimine:

    ei ole lubatud

  • Kasutamine:

    Digitaalõiguste kaitse (DRM)
    Kirjastus on väljastanud selle e-raamatu krüpteeritud kujul, mis tähendab, et selle lugemiseks peate installeerima spetsiaalse tarkvara. Samuti peate looma endale  Adobe ID Rohkem infot siin. E-raamatut saab lugeda 1 kasutaja ning alla laadida kuni 6'de seadmesse (kõik autoriseeritud sama Adobe ID-ga).

    Vajalik tarkvara
    Mobiilsetes seadmetes (telefon või tahvelarvuti) lugemiseks peate installeerima selle tasuta rakenduse: PocketBook Reader (iOS / Android)

    PC või Mac seadmes lugemiseks peate installima Adobe Digital Editionsi (Seeon tasuta rakendus spetsiaalselt e-raamatute lugemiseks. Seda ei tohi segamini ajada Adober Reader'iga, mis tõenäoliselt on juba teie arvutisse installeeritud )

    Seda e-raamatut ei saa lugeda Amazon Kindle's. 

Presenting a mathematical model for on-chip routers which can be used for NoC performance analysis, this book reflects the shift from computation- to communication-based design that has resulted from the increasing complexity of so-called ‘systems-on-chip’.



Traditionally, design space exploration for Systems-on-Chip (SoCs) has focused on the computational aspects of the problem at hand. However, as the number of components on a single chip and their performance continue to increase, the communication architecture plays a major role in the area, performance and energy consumption of the overall system. As a result, a shift from computation-based to communication-based design becomes mandatory. Towards this end, network-on-chip (NoC) communication architectures have emerged recently as a promising alternative to classical bus and point-to-point communication architectures.

In this dissertation, we study outstanding research problems related to modeling, analysis and optimization of NoC communication architectures. More precisely, we present novel design methodologies, software tools and FPGA prototypes to aid the design of application-specific NoCs.

1 Introduction
1(8)
1.1 Network-on-Chip Architectures
1(2)
1.2 Advantages of NoC Architectures
3(1)
1.3 A Generic NoC Synthesis Flow
3(3)
1.4 NoC Design Space and State of the Art
6(3)
References
7(2)
2 Literature Survey
9(24)
2.1 Application Modeling and Optimization for NoC Communication
9(3)
2.1.1 Traffic Models
9(1)
2.1.2 Application Mapping
10(1)
2.1.3 Application Scheduling
11(1)
2.2 Communication Paradigm
12(5)
2.2.1 Packet Routing
12(1)
2.2.2 Switching Techniques
13(1)
2.2.3 QoS and Congestion Control
14(1)
2.2.4 Power and Thermal Management
15(1)
2.2.5 Reliability and Fault Tolerance
16(1)
2.3 Communication Infrastructure
17(4)
2.3.1 Topology Design
17(1)
2.3.2 Router Design
18(1)
2.3.3 Network Channel Design
19(1)
2.3.4 Floorplanning and Layout Design
20(1)
2.3.5 Clocking and Power Distribution
20(1)
2.4 NoC Evaluation and Validation
21(1)
2.4.1 Analysis and Simulation
21(1)
2.5 Prototyping, Testing and Verification
22(11)
References
23(10)
3 Motivational Example: MPEG-2 Encoder Design
33(6)
3.1 Overall Approach
33(1)
3.2 Evaluation of the NoC Architecture
34(2)
3.2.1 Area Evaluation
34(1)
3.2.2 Performance Evaluation
35(1)
3.2.3 Energy Consumption Evaluation
36(1)
3.3 Overall Comparison
36(3)
References
37(2)
4 Target NoC Platform
39(10)
4.1 Basic Assumptions
39(2)
4.1.1 Routing Algorithm
40(1)
4.1.2 Switching Technique
40(1)
4.2 NoC Architecture Modeling
41(2)
4.3 Application Modeling
43(1)
4.4 Technology Implications on Networks-on-Chip Platforms
43(6)
References
46(3)
5 NoC Performance Analysis
49(26)
5.1 Introduction
49(2)
5.2 Related Work
51(1)
5.3 Router Modeling for Performance Analysis
52(5)
5.3.1 Basic Assumptions and Notations
52(1)
5.3.2 Analytical Model of the Router
53(3)
5.3.3 Computation of the Contention Matrix
56(1)
5.4 Performance Analysis of Router, Shared Bus and Point-to-Point Configurations
57(6)
5.4.1 Router with Multiple Virtual Channels
58(1)
5.4.2 Performance Models for Shared Bus and Point-to-Point Architectures
58(1)
5.4.3 Analytical Performance Comparisons
59(3)
5.4.4 Using Equation 5.5 for Router Design
62(1)
5.5 Network Performance Analysis
63(4)
5.5.1 Average Buffer Utilization and Packet Latency
64(1)
5.5.2 Network Throughput
65(1)
5.5.3 Overview of the Performance Analysis Methodology
66(1)
5.6 Experimental Results
67(6)
5.6.1 Average Packet Latency
67(2)
5.6.2 Case Study: Application Mapping
69(1)
5.6.3 Network Throughput
70(1)
5.6.4 Application to Arbitrary Topologies
71(1)
5.6.5 Complexity and Run-Time Analysis
72(1)
5.7 Summary
73(2)
References
73(2)
6 Application-Specific NoC Architecture Customization Using Long-Range Links
75(30)
6.1 Introduction
75(3)
6.2 Related Work
78(1)
6.3 Long-Range Link Insertion Algorithm
78(7)
6.3.1 System Model and Basic Assumptions
78(1)
6.3.2 Problem Formulation
79(1)
6.3.3 Iterative Long-Range Link Insertion Algorithm
80(1)
6.3.4 Evaluation of the Critical Traffic Value
81(2)
6.3.5 Small-World Properties of Networks Customized Via Long-Range Links
83(2)
6.4 Routing with Long-Range Links
85(3)
6.5 Implementation of Long-Range Links
88(3)
6.5.1 Traditional CMOS Implementation
90(1)
6.5.2 Optical Interconnects for Implementing Long-Range Links
90(1)
6.6 Energy-Related Considerations
91(1)
6.7 Practical Use of Long-Range Links
92(1)
6.8 Experimental Evaluation of Long-Range Link Insertion Methodology
93(8)
6.8.1 Evaluation Using Synthetic Benchmarks
93(1)
6.8.2 Scalability Analysis
94(2)
6.8.3 Comparison with Topologies of Higher Dimensionality
96(1)
6.8.4 Experiments Involving Real Traffic
97(2)
6.8.5 One Architecture for All
99(2)
6.9 Summary
101(4)
References
102(3)
7 Analysis and Optimization of Prediction-Based Flow Control in Networks-on-Chip
105(30)
7.1 Introduction
105(1)
7.2 Overall Approach
106(1)
7.3 Related Work
107(2)
7.4 System and Traffic Source Modeling
109(4)
7.4.1 System Model and Basic Assumptions
109(1)
7.4.2 Traffic Source Model
109(3)
7.4.3 Predictive Control of Traffic Sources
112(1)
7.5 State Space Modeling of NoC Routers
113(3)
7.6 Prediction-Based Flow Controller
116(8)
7.6.1 Availability Predictor
116(3)
7.6.2 Practical Implementation of the Predictor
119(2)
7.6.3 Using Prediction for Network Control
121(1)
7.6.4 On the Stability of the Proposed Flow Control Algorithm
122(2)
7.7 Experimental Results
124(8)
7.7.1 Audio/Video System
125(2)
7.7.2 Synthetic Traffic
127(1)
7.7.3 Impact of the Local Buffer Size on Performance
128(2)
7.7.4 Scalability of the Approach
130(1)
7.7.5 Evaluation with an FPGA Prototype
131(1)
7.8 Summary
132(3)
References
132(3)
8 Design and Management of VFI Partitioned Networks-on-Chip
135(20)
8.1 Introduction
135(2)
8.2 Related Work
137(1)
8.3 VFI Partitioning and Static Voltage Assignment Problems
138(6)
8.3.1 Basic Assumptions and Methodology Overview
138(1)
8.3.2 Problem Formulations
139(2)
8.3.3 Motivational Example
141(1)
8.3.4 Partitioning Methodology
142(2)
8.4 Feedback Control of Voltage and Frequency
144(3)
8.4.1 State-Space Feedback Control
144(3)
8.5 Experimental Results
147(5)
8.5.1 Experiments with Realistic Benchmarks
147(2)
8.5.2 Experiments with a Real Video Application
149(1)
8.5.3 Evaluation of the Feedback Control Strategy
150(2)
8.6 Extensions of Basic Theory
152(1)
8.7 Summary
152(3)
References
152(3)
9 Conclusion
155(2)
Appendix A: Tools and FPGA Prototypes 157(10)
Appendix B: Experiments Using the Single-Chip Cloud Computer (SCC) Platform 167(6)
Index 173
Lisainfo e-raamatute kohta Lisainfo e-raamatute kohta
Püsilink: https://www.kriso.ee/db/97894007395812e.html
Märksõnad: