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E-raamat: Nanoelectronic Mixed-Signal System Design

  • Formaat: 832 pages
  • Ilmumisaeg: 20-Feb-2015
  • Kirjastus: McGraw-Hill Professional
  • Keel: eng
  • ISBN-13: 9780071823036
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Nanoelectronic Mixed-Signal System DesignSuurem pilt
  • Formaat: 832 pages
  • Ilmumisaeg: 20-Feb-2015
  • Kirjastus: McGraw-Hill Professional
  • Keel: eng
  • ISBN-13: 9780071823036
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Cutting-edge nanoelectronic mixed-signal system design methodsWinner of the Association of American Publishers' 2016 PROSE Award in the Textbook/Physical Sciences & Mathematics category.

Written by the director of the NanoSystem Design Laboratory at the University of North Texas, this authoritative resource discusses mixed-signal circuit and system design based on existing and emerging nanoelectronic technologies. The book features coverage of both digital and analog applications using nanoscale CMOS and post-CMOS. Key techniques required for design for excellence and manufacturability are discussed in this practice-driven text.



Nanoelectronic Mixed-Signal System Design covers:





Opportunities and challenges of nanoscale technology and systems Emerging systems designed as analog/mixed-signal system-on-chips (AMS-SoCs) Nanoelectronics issues in design for excellence Phase-locked loop component circuits Electronic signal converter circuits Sensor circuits and systems Memory in the AMS-SoCs Mixed-signal circuit and system design flow Mixed-signal circuit and system simulation Power-, parasitic-, and thermal-aware AMS-SoC design methodologies Variability-aware AMS-SoC design methodologies Metamodel-based fast AMS-SoC design methodologies
Preface xxiii
Acknowledgments xxv
Acronyms xxvii
Notation xxxv
1 Opportunities and Challenges of Nanoscale Technology and Systems 1(24)
1.1 Introduction
1(2)
1.2 Mixed-Signal Circuits and Systems
3(2)
1.2.1 Different Processors: Electrical to Mechanical
3(1)
1.2.2 Analog versus Digital Processors
3(1)
1.2.3 Analog, Digital, Mixed-Signal Circuits and Systems
3(1)
1.2.4 Two Types of Mixed-Signal Systems
4(1)
1.3 Nanoscale CMOS Circuit Technology
5(4)
1.3.1 Developmental Trend
5(1)
1.3.2 Nanoscale CMOS Alternative Device Options
5(3)
1.3.3 Advantages and Disadvantages of Technology Scaling
8(1)
1.3.4 Challenges in Nanoscale Design
8(1)
1.4 Power Consumption and Leakage Dissipation Issues in AMS-SoCs
9(2)
1.4.1 Power Consumption in Various Components in AMS-SoCs
9(1)
1.4.2 Power and Leakage Trend in Nanoscale Technology
9(1)
1.4.3 The Impact of Power Consumption and Leakage Dissipation
10(1)
1.5 Parasitics Issue
11(1)
1.5.1 Types of Parasitics
11(1)
1.5.2 The Impact of Parasitics
11(1)
1.5.3 Challenges to Account Parasitics during Design
12(1)
1.6 Nanoscale Circuit Process Variation Issues
12(1)
1.6.1 Types of Process Variation
12(1)
1.6.2 The Impact of Process Variation
12(1)
1.7 The Temperature Variation Issue
13(2)
1.7.1 The Issue of Temperature
13(1)
1.7.2 The Impact of Temperature
14(1)
1.7.3 Challenges to Account through PVT-Aware Design
14(1)
1.8 Challenges in Nanoscale CMOS AMS-SoC Design
15(1)
1.8.1 AMS-SoC Design Flow
15(1)
1.8.2 AMS-SoC Unified Optimization
15(1)
1.9 Tools for Mixed-Signal Circuit Design
16(2)
1.9.1 The AMS-SoC Design Issue
16(1)
1.9.2 Languages for AMS-SoC Design
16(1)
1.9.3 Tools for AMS-SoC Design and Simulation
17(1)
1.9.4 Transistor Models
18(1)
1.10 Questions
18(1)
1.11 References
19(6)
2 Emerging Systems Designed as Analog/Mixed-Signal System-on-Chips 25(40)
2.1 Introduction
25(1)
2.2 Atomic Force Microscope
25(2)
2.2.1 What Is It?
25(1)
2.2.2 Background
25(1)
2.2.3 What Is Inside?
26(1)
2.3 Biosensor Systems
27(4)
2.3.1 What Is It?
27(2)
2.3.2 Background
29(1)
2.3.3 What Is Inside?
30(1)
2.4 Blu-Ray Player
31(1)
2.4.1 What Is It?
31(1)
2.4.2 Home Video Systems Background: From Video Cassette Player to Blu-Ray Player
31(1)
2.4.3 What Is Inside?
31(1)
2.5 Drug-Delivery Nano-Electro-Mechanical Systems
32(2)
2.5.1 What Is It?
32(1)
2.5.2 Background
32(1)
2.5.3 What Is Inside?
33(1)
2.6 Digital Video Recorder
34(1)
2.6.1 What Is It?
34(1)
2.6.2 Background
34(1)
2.6.3 What Is Inside?
35(1)
2.7 Electroencephalogram System
35(1)
2.7.1 What Is It?
35(1)
2.7.2 Background
35(1)
2.7.3 What Is Inside?
35(1)
2.8 GPS Navigation Device
36(1)
2.8.1 What Is It?
36(1)
2.8.2 Background
36(1)
2.8.3 What Is Inside?
37(1)
2.9 GPU-CPU Hybrid System
37(3)
2.9.1 What Is It?
37(1)
2.9.2 Background
38(1)
2.9.3 What Is Inside?
38(2)
2.10 Networked Media Tank
40(1)
2.10.1 What Is It?
40(1)
2.10.2 Background
40(1)
2.10.3 What Is Inside?
41(1)
2.11 Net-Centric Multimedia Processor
41(3)
2.11.1 What Is It?
41(1)
2.11.2 Background
42(1)
2.11.3 What Is Inside?
43(1)
2.12 Radiation Detection System
44(2)
2.12.1 What Is It?
44(1)
2.12.2 Background
45(1)
2.12.3 What Is Inside?
45(1)
2.13 Radio Frequency Identification Chip
46(3)
2.13.1 What Is It?
46(1)
2.13.2 Background
47(1)
2.13.3 What Is Inside?
47(2)
2.14 Secure Digital Camera
49(1)
2.14.1 What Is It?
49(1)
2.14.2 Background
49(1)
2.14.3 What Is Inside?
50(1)
2.15 Set-Top Box
50(2)
2.15.1 What Is It?
50(1)
2.15.2 Background
50(1)
2.15.3 What Is Inside?
51(1)
2.16 Slate Personal Computer
52(2)
2.16.1 What Is It?
52(1)
2.16.2 Background: The Developmental Trend of General-Purpose Computer Reaches Slate PC
52(1)
2.16.3 What Is Inside?
53(1)
2.17 Smart Mobile Phone
54(2)
2.17.1 What Is It?
54(1)
2.17.2 Background
55(1)
2.17.3 What Is Inside?
55(1)
2.18 Software-Defined Radio
56(1)
2.18.1 What Is It?
56(1)
2.18.2 Background
56(1)
2.18.3 What Is Inside?
56(1)
2.19 TV Tuner Card for PCs
57(2)
2.19.1 What Is It?
57(1)
2.19.2 Background
58(1)
2.19.3 What Is Inside?
58(1)
2.20 Universal Remote Control
59(1)
2.20.1 What Is It?
59(1)
2.20.2 Background
59(1)
2.20.3 What Is Inside?
59(1)
2.21 Questions
60(1)
2.22 References
60(5)
3 Nanoelectronics Issues in Design for Excellence 65(92)
3.1 Introduction
65(1)
3.2 Design for eXcellence
65(2)
3.3 Different Types of Nanoelectronic Devices
67(24)
3.3.1 Nanoscale Classical SiO2/Polysilicon FET
68(2)
3.3.2 High-κ and Metal-Gate Nonclassical FET
70(2)
3.3.3 Multiple Independent Gate FET
72(7)
3.3.4 Carbon Nanotube FET
79(2)
3.3.5 Graphene FET
81(3)
3.3.6 Single-Electron Transistor
84(1)
3.3.7 Thin-Film Transistor
85(1)
3.3.8 Tunnel FET
86(2)
3.3.9 Vibrating Body FET
88(1)
3.3.10 Memdevices: Memristor, Memcapacitor, and Meminductor
88(3)
3.4 Nanomanufacturing: The Origin and Source of Process Variations
91(7)
3.4.1 Classical CMOS Fabrication Process
93(2)
3.4.2 Carbon Nanotube FET Fabrication Process
95(1)
3.4.3 FinFET Fabrication Process
95(1)
3.4.4 Graphene FET Fabrication Process
96(1)
3.4.5 Tunnel FET Fabrication Process
97(1)
3.4.6 Memristor Fabrication Process
98(1)
3.5 The Issue of Process Variation
98(9)
3.5.1 Types of Process Variation
99(1)
3.5.2 Impact on Device Parameters
100(3)
3.5.3 Design Phase Incorporation of Process Variation
103(4)
3.6 The Yield Issue
107(2)
3.7 The Power Issue in Nanoelectronic Circuits
109(13)
3.7.1 Power Dissipation in Nanoscale Classical CMOS Circuits
111(9)
3.7.2 Power Dissipation in Nanoscale High-κ and Metal-Gate FET
120(1)
3.7.3 Power Dissipation in Double-Gate FinFET
121(1)
3.8 The Issue of Parasitics in Nanoelectronic Circuits
122(11)
3.8.1 Different Types of Parasitics
122(1)
3.8.2 Device Parasitics
122(3)
3.8.3 Interconnect Parasitics
125(8)
3.9 The Thermal Issue
133(2)
3.10 The Reliability Issue
135(6)
3.10.1 Hot Carrier Injection
135(2)
3.10.2 Negative Bias Temperature Instability
137(1)
3.10.3 Latchup Effect
137(1)
3.10.4 Time-Dependent Dielectric Breakdown
138(1)
3.10.5 Electromigration
139(2)
3.10.6 Thermal Stress
141(1)
3.11 The Trust Issue
141(4)
3.11.1 Information Protection Issue
142(1)
3.11.2 Information Leakage Issue
143(1)
3.11.3 Chip Intellectual Property Protection Issue
143(1)
3.11.4 Malicious Design Modifications Issue
144(1)
3.12 Questions
145(1)
3.13 References
145(12)
4 Phase-Locked Loop Component Circuits 157(58)
4.1 Introduction
157(1)
4.2 Phase-Locked Loop System Types
158(2)
4.3 Phase-Locked Loop System: A Broad Overview
160(4)
4.3.1 Definition
160(1)
4.3.2 Block-Level Representation
160(1)
4.3.3 Characteristics, or Performance Metrics
161(2)
4.3.4 Theory in Brief
163(1)
4.4 Oscillator Circuits
164(7)
4.4.1 Oscillator Types
164(1)
4.4.2 Oscillator Characteristics, or Performance Metrics
165(5)
4.4.3 Comparison of Oscillators
170(1)
4.5 Ring Oscillators
171(6)
4.5.1 Basics
171(1)
4.5.2 45-nm CMOS
171(2)
4.5.3 Multigate FET
173(2)
4.5.4 Carbon Nanotube
175(2)
4.6 Current-Starved Voltage Controlled Oscillators
177(7)
4.6.1 Basics
177(1)
4.6.2 Circuit Design
177(2)
4.6.3 90-nm CMOS
179(1)
4.6.4 50-nm CMOS
179(1)
4.6.5 45-nm CMOS
179(4)
4.6.6 45-nm Double-Gate FinFET
183(1)
4.7 LC-Tank Voltage-Controlled Oscillator
184(6)
4.7.1 Basics
184(2)
4.7.2 180-nm CMOS
186(1)
4.7.3 CNTFET
187(1)
4.7.4 Memristor
188(2)
4.8 Relaxation Oscillators
190(3)
4.8.1 Low-Power Relaxation Oscillator
191(1)
4.8.2 Memristor Relaxation Oscillator
191(1)
4.8.3 Memristor-Based Schmitt Trigger Oscillator
192(1)
4.9 Phase-Frequency Detectors
193(2)
4.9.1 D Flip-Flop-Based PFD
194(1)
4.9.2 XOR Gate-Based PFD
194(1)
4.10 Charge Pumps
195(3)
4.10.1 Basics
195(1)
4.10.2 180-nm CMOS
196(2)
4.11 Loop Filters
198(2)
4.12 Frequency Dividers
200(3)
4.12.1 Basics
200(1)
4.12.2 DFF-Based 180-nm CMOS
200(1)
4.12.3 JK Flip-Flop-Based 45-nm CMOS
200(3)
4.13 Design and Characterization of a 180-nm CMOS PLL
203(1)
4.14 All Digital Phase-Locked Loop
204(2)
4.14.1 Basics
204(1)
4.14.2 A Simple ADPLL Using an NCO
204(1)
4.14.3 A High-Resolution ADPLL Using Double DCO
205(1)
4.15 Delay-Locked Loop
206(3)
4.15.1 Basics
206(1)
4.15.2 An Analog DLL for Variable Frequency Generation
207(1)
4.15.3 A Digital DLL
208(1)
4.16 Questions
209(1)
4.17 References
210(5)
5 Electronic Signal Converter Circuits 215(48)
5.1 Introduction
215(1)
5.2 Types of Electronic Signal Converters
216(2)
5.2.1 Concrete Applications
216(1)
5.2.2 Signal Converter Types
217(1)
5.3 Selected ADC Architectures: Brief Overview
218(7)
5.3.1 Overview
218(1)
5.3.2 Ramp-Compare ADC or Ramp Run-Up ADC
219(1)
5.3.3 Flash ADC or Direct Conversion ADC
219(1)
5.3.4 Successive-Approximation ADC
220(1)
5.3.5 Integrating ADC
220(1)
5.3.6 Pipeline ADC or Subranging ADC
221(1)
5.3.7 Sigma-Delta ADC or Oversampling ADC
221(1)
5.3.8 Time-Interleaved ADC
222(1)
5.3.9 Folding ADC
222(1)
5.3.10 Tracking ADC or Counter-Ramp ADC or Delta-Encoded ADC
223(1)
5.3.11 Architecture Selection
224(1)
5.4 Selected DAC Architectures: Brief Overview
225(6)
5.4.1 Binary-Weighted DAC
225(2)
5.4.2 Thermometer-Coded DAC
227(1)
5.4.3 Pulse-Width Modulator DAC
227(1)
5.4.4 R-2R Ladder DAC
227(1)
5.4.5 Segmented DAC
228(1)
5.4.6 Oversampling or Interpolating DAC
229(1)
5.4.7 Sigma-Delta DAC
229(1)
5.4.8 Successive-Approximation or Cyclic or Algorithmic DAC
229(1)
5.4.9 Multiplying DAC
230(1)
5.4.10 Pipeline DAC
230(1)
5.5 Characteristics for Data Converters
231(7)
5.5.1 Characteristics for ADC
231(5)
5.5.2 Characteristics for DAC
236(2)
5.6 A 90-nm CMOS-Based Flash ADC
238(7)
5.6.1 Comparator Bank
238(2)
5.6.2 1 of N Code Generator
240(1)
5.6.3 NOR ROM
240(1)
5.6.4 Physical Design and Characterization of 90-nm ADC
241(1)
5.6.5 Post-Layout Simulation and Characterization
241(4)
5.7 A 45-nm CMOS-Based Flash ADC
245(4)
5.7.1 Comparator Bank
245(1)
5.7.2 1 of N Code Generator
245(1)
5.7.3 NOR ROM
246(1)
5.7.4 Functional Simulation and Characterization
246(3)
5.8 Single-Electron-Based ADC
249(1)
5.8.1 Single-Electron Circuitry-Based ADC
249(1)
5.8.2 Single-Electron Transistor-Based ADC
249(1)
5.9 Organic Thin-Film Transistor-Based ADCs
250(2)
5.9.1 Organic Thin-Film Transistor VCO-Based ADC
250(1)
5.9.2 Complementary Organic Thin-Film Transistor-Based Successive-Approximation ADC
250(2)
5.10 Sigma-Delta Modulator-Based ADC
252(4)
5.10.1 Broad Prospective
252(1)
5.10.2 Architecture Overview
252(2)
5.10.3 Architecture Components
254(2)
5.11 Sigma-Delta Modulator-Based Digital-to-Analog Converter
256(1)
5.12 Single Electron Transistor-Based Digital-to-Analog Converter
257(1)
5.13 Questions
258(1)
5.14 References
259(4)
6 Sensor Circuits and Systems 263(52)
6.1 Introduction
263(1)
6.2 Nanoelectronics-Based Biosensors
264(2)
6.2.1 Spintronic-Memristor-Based Biosensors
264(1)
6.2.2 Tunnel-FET-Based Biosensors
265(1)
6.2.3 Graphene-FET-Based Biosensors
265(1)
6.3 Thermal Sensors for Mixed-Signal Circuits and Systems
266(6)
6.3.1 Performance Metrics for Thermal Sensors
267(1)
6.3.2 A Concrete Example: A 45-nm CMOS Ring Oscillator-Based Thermal Sensor
268(3)
6.3.3 A Concrete Example: Spintronic-Memristor Temperature Sensor
271(1)
6.4 Solar Cells
272(6)
6.4.1 Operation and Performance of Cells
273(2)
6.4.2 Selected Solar Cell Designs
275(1)
6.4.3 Solar Cell Models for Circuit Simulations
276(2)
6.5 Piezoelectric Sensors
278(2)
6.6 Image Sensors
280(14)
6.6.1 Types of Image Sensors
281(4)
6.6.2 Characteristics of the Image Sensors
285(4)
6.6.3 A Concrete Example: 32-nm CMOS APS Design
289(2)
6.6.4 Smart Image Sensors
291(2)
6.6.5 Secure Image Sensors
293(1)
6.7 Nanoelectronics-Based Gas Sensors
294(1)
6.7.1 CNTFET-Based Gas Sensor
294(1)
6.7.2 CNTFET-Based Chemical Sensor
294(1)
6.8 Body Sensors
295(2)
6.9 Epileptic Seizure Sensors
297(1)
6.10 Humidity Sensors
297(2)
6.10.1 A Diode-Based Humidity Sensor
298(1)
6.10.2 A CMOS Device—Based Humidity Sensor
298(1)
6.11 Motion Sensors
299(1)
6.12 Sense Amplifiers
300(7)
6.12.1 Types of Sense Amplifiers
301(1)
6.12.2 Performance Metrics for the Sense Amplifiers
302(2)
6.12.3 A Concrete Example: 45-nm CMOS Clamped Bitline Sense Amplifier
304(3)
6.13 Questions
307(1)
6.14 References
308(7)
7 Memory in the AMS-SoCs 315(50)
7.1 Introduction
315(2)
7.2 Static Random-Access Memory
317(21)
7.2.1 SRAM Array
317(1)
7.2.2 Different Types of SRAM
318(1)
7.2.3 Traditional Six-Transistor SRAM
318(3)
7.2.4 Four-Transistor SRAM
321(1)
7.2.5 Five-Transistor SRAM
321(1)
7.2.6 Seven-Transistor SRAM
322(2)
7.2.7 Eight-Transistor SRAM
324(2)
7.2.8 Nine-Transistor SRAM
326(1)
7.2.9 Ten-Transistor SRAM
326(1)
7.2.10 Performance Metrics of SRAM
327(4)
7.2.11 Characterization of Specific SRAMs
331(7)
7.3 Dynamic Random-Access Memory
338(9)
7.3.1 DRAM Array
339(1)
7.3.2 Different Types of DRAM
339(1)
7.3.3 Selected DRAM Designs Based on Topology
340(3)
7.3.4 DRAMs Based on Modes of Operation
343(1)
7.3.5 Synchronous DRAMs
344(1)
7.3.6 Video or Graphics DRAM
344(1)
7.3.7 Ferroelectric DRAM
345(1)
7.3.8 Characteristics of DRAM
346(1)
7.4 Twin-Transistor Random-Access Memory
347(1)
7.5 Thyristor Random-Access Memory
348(1)
7.6 Read-Only Memory
349(2)
7.6.1 Programmable Read-Only Memory
349(1)
7.6.2 Erasable Programmable Read-Only Memory
349(1)
7.6.3 Electrically Erasable Programmable Read-Only Memory
350(1)
7.7 Flash Memory
351(1)
7.8 Resistive Random-Access Memory
352(3)
7.8.1 Nonvolatile Resistive RAM for Storage
352(1)
7.8.2 Conductive Metal-Oxide Memory
353(1)
7.8.3 Memristor-Based Nonvolatile SRAM
354(1)
7.9 Magnetic or Magnetoresistive Random-Access Memory
355(1)
7.10 Phase-Change RAM
356(2)
7.11 Questions
358(1)
7.12 References
359(6)
8 Mixed-Signal Circuit and System Design Flow 365(56)
8.1 Introduction
365(1)
8.2 AMS-SoC: A Complete Design Perspective
365(4)
8.3 Integrated Circuit Design Flow: Top-Down versus Bottom-Up
369(2)
8.4 Analog Circuit Design Flow
371(11)
8.4.1 Behavioral Simulation
372(2)
8.4.2 Transistor-Level Design or Schematic Capture
374(1)
8.4.3 Transistor-Level Simulation and Characterization
374(1)
8.4.4 Physical Design or Layout Design
374(1)
8.4.5 Design Rule Check
375(1)
8.4.6 Parasitic (RCLK) Extraction
376(1)
8.4.7 Layout versus Schematic Verification
377(1)
8.4.8 Electrical Rule Check
377(1)
8.4.9 Physical Design Characterization
378(1)
8.4.10 Variability Analysis
379(1)
8.4.11 Performance Optimization
380(2)
8.5 Digital Circuit Design Flow
382(7)
8.5.1 System-Level Design
384(1)
8.5.2 Architecture-Level Design
384(1)
8.5.3 Logic-Level Design
385(1)
8.5.4 Transistor-Level Design
386(1)
8.5.5 Physical Design
386(1)
8.5.6 Physical Verification
387(1)
8.5.7 Design Signoff
387(1)
8.5.8 Engineering Change Order
388(1)
8.5.9 Circuit Fabrication, Packaging, and Testing
388(1)
8.6 Analog and Mixed-Signal Circuit Design Flow
389(4)
8.6.1 Mixed-Signal Design Flow
389(2)
8.6.2 Analog and/or Mixed-Signal Circuit Synthesis Techniques
391(2)
8.7 Design Flow Using Commercial Electronic Design Automation Tools
393(6)
8.7.1 Selected Commercial EDA Tools
393(1)
8.7.2 For Analog Design
394(1)
8.7.3 For Digital Design
395(3)
8.7.4 For Mixed-Signal System Design
398(1)
8.8 Design Flow Using Free or Open-Source EDA Tools
399(4)
8.8.1 Selected Free or Open-Source EDA Tools
399(2)
8.8.2 For Analog Design
401(1)
8.8.3 For Digital Design
402(1)
8.8.4 For Mixed-Signal Design
402(1)
8.9 Comprehensive Design Flows
403(4)
8.9.1 For Analog/Mixed-Signal Circuits and Systems
403(3)
8.9.2 For Digital Circuits and Systems
406(1)
8.10 Process Design Kit and Libraries
407(2)
8.11 EDA Tool Installation
409(2)
8.11.1 Client-Server Platform
409(1)
8.11.2 Workstation-Based Platform
410(1)
8.11.3 Mixed-Configuration Platform
410(1)
8.12 Questions
411(1)
8.13 References
412(9)
9 Mixed-Signal Circuit and System Simulation 421(92)
9.1 Introduction
421(1)
9.2 Simulation Types and Languages for Circuits and Systems
422(3)
9.2.1 Simulations Based on Abstraction Levels
422(1)
9.2.2 Simulations Based on Signal Types
423(1)
9.2.3 Simulations Based on System Models
423(1)
9.2.4 Simulations Based on Design Tasks
423(1)
9.2.5 Simulation Languages
424(1)
9.3 Behavioral Simulation using MATLAB®
425(8)
9.3.1 System- or Architecture-Level Simulations
426(4)
9.3.2 Circuit-Level Simulations
430(2)
9.3.3 Device-Level Simulations
432(1)
9.4 Simulink®- or Simscape®-Based Simulations
433(12)
9.4.1 System- or Architecture-Level Simulations
434(4)
9.4.2 Circuit-Level Simulations
438(2)
9.4.3 Device-Level Simulations
440(5)
9.5 Circuit-Level and/or Device-Level Analog Simulations
445(19)
9.5.1 SPICE Analog Simulation Background
446(1)
9.5.2 Commercial Accurate Analog Circuit Simulators
447(1)
9.5.3 Free and/or Open-Source Accurate SPICE
448(1)
9.5.4 Fast SPICE
449(1)
9.5.5 Analog-Fast SPICE
450(1)
9.5.6 High-Speed SPICE
450(1)
9.5.7 Different Types of Analysis using SPICE
450(2)
9.5.8 SPICE-Based Simulation Examples
452(3)
9.5.9 Inside of SPICE
455(5)
9.5.10 SPICE Simulation Flow
460(4)
9.6 Verilog-A-Based Analog Simulation
464(10)
9.6.1 Verilog-A-Based Circuit-Level Simulations
465(3)
9.6.2 Verilog-A-Based Device-Level Simulations
468(6)
9.7 Simulations of Digital Circuits or Systems
474(6)
9.7.1 SystemVerilog-Based Simulation
474(1)
9.7.2 VHDL-Based Simulation
475(2)
9.7.3 MyHDL-Based Simulation
477(1)
9.7.4 SystemC-Based Simulation
478(2)
9.8 Mixed-Signal HDL-Based Simulation
480(15)
9.8.1 Verilog-AMS-Based Simulation
481(8)
9.8.2 VHDL-AMS-Based Simulation
489(2)
9.8.3 OpenMAST™-Based Simulation
491(3)
9.8.4 SystemC-AMS-Based Simulation
494(1)
9.9 Mixed-Mode Circuit-Level Simulations
495(3)
9.9.1 Nanoelectronics Analog versus Mixed-Signal Simulation: A Comparative Perspective
496(1)
9.9.2 Mixed-Mode with Individual Analog and Digital Engine
497(1)
9.9.3 Mixed-Mode with Unified Analog and Digital Engine
498(1)
9.10 Models for Circuit Simulations
498(3)
9.10.1 Compact Model Generation Flow
498(2)
9.10.2 Types of Compact Models
500(1)
9.10.3 Automatic Device Model Synthesizer (ADMS)
501(1)
9.11 Questions
501(1)
9.12 References
502(11)
10 Power-, Parasitic-, and Thermal-Aware AMS-SoC Design Methodologies 513(106)
10.1 Introduction
513(1)
10.2 Power Dissipation: Key Design Constraint
513(8)
10.2.1 The Effects of High-Power Dissipation
514(1)
10.2.2 Power Dissipation Sources
515(1)
10.2.3 Power or Energy Dissipation Metrics
516(2)
10.2.4 Energy/Power Dissipation: Application Perspectives
518(2)
10.2.5 Limits to Low-Power Design
520(1)
10.3 Different Energy or Power Reduction Techniques for AMS-SoC
521(6)
10.3.1 AMS-SoC Energy or Power Reduction Techniques: An Overview
521(2)
10.3.2 Analog Circuit Power Optimization: An Overview
523(2)
10.3.3 Digital SoC Power or Energy Optimization Procedures: An Overview
525(2)
10.4 Presilicon Power Reduction Techniques
527(9)
10.4.1 Brief Discussion
527(1)
10.4.2 Dual-Threshold-Based Circuit-Level Optimization of a Universal Level Converter
528(3)
10.4.3 Dual-Oxide-Based Logic-Level Optimization of Digital Circuits
531(3)
10.4.4 Dual-Oxide-Based RTL Optimization of Digital Circuits
534(2)
10.5 Hardware-Based Postsilicon Power Reduction Techniques
536(5)
10.5.1 Brief Discussion
536(2)
10.5.2 Dynamic or Variable Frequency Clocking for Power Reduction
538(2)
10.5.3 Adaptive Voltage Scaling for Power and Energy Reduction
540(1)
10.6 Dynamic Power Reduction Techniques
541(7)
10.6.1 Brief Discussion
541(1)
10.6.2 Dual-Voltage and Dual-Frequency-Based Circuit-Level Technique
542(2)
10.6.3 Multiple Supply Voltage-Based RTL Technique
544(4)
10.7 Subthreshold Leakage Reduction Techniques
548(5)
10.7.1 Brief Discussion
548(2)
10.7.2 Dual-Threshold-Based Circuit-Level Optimization of Nano-CMOS SRAM
550(3)
10.8 Gate-Oxide Leakage Reduction Techniques
553(7)
10.8.1 Brief Discussion
553(1)
10.8.2 Dual-Oxide-Based Circuit-Level Optimization of a Current-Starved VCO
554(4)
10.8.3 Dual-Oxide-Based RTL Optimization of Digital ICs
558(2)
10.9 Parasitics: Brief Overview
560(2)
10.10 The Effects of Parasitics on Integrated Circuits
562(3)
10.10.1 Parasitics in Real-Life Example Circuits
562(1)
10.10.2 Effects of the Parasitics
562(3)
10.11 Modeling and Extraction of Parasitics
565(9)
10.11.1 Signal Propagation: In a Real Wire
565(1)
10.11.2 Parasitics Modeling and Simulation: The Key Aspects
566(1)
10.11.3 Circuit (Device+Parasitic) Extraction Process
566(2)
10.11.4 Parasitics Extraction Techniques
568(1)
10.11.5 Parasitics Modeling
569(1)
10.11.6 Parasitics Model Order Reduction
570(4)
10.12 Design Flows for Parasitic-Aware Circuit Optimization
574(8)
10.12.1 Parasitic-Aware Analog Design Flow with Multilevel Optimizations
574(1)
10.12.2 A Rapid Parasitic-Aware Design Flow for Analog Circuits
574(2)
10.12.3 Single-Manual Iteration Fast Design Flow for Parasitic-Optimal VCO
576(2)
10.12.4 Parasitic-Aware Low-Power Design of the ULC
578(4)
10.13 Temperature or Thermal Issue: An Overview
582(2)
10.14 Thermal Modeling
584(4)
10.14.1 Heat Dissipation: Structure View
584(2)
10.14.2 Compact Thermal Modeling
586(2)
10.15 Thermal Analysis or Simulation Techniques
588(6)
10.15.1 Heat Transfer Basics
588(1)
10.15.2 Thermal Analysis Basics
589(1)
10.15.3 Thermal Analysis Types
589(1)
10.15.4 A Runge-Kutta-Based Method
590(1)
10.15.5 An Integrated Space-and-Time-Adaptive Chip Thermal Analysis Framework
590(2)
10.15.6 A Fast Asynchronous Time Marching Technique
592(1)
10.15.7 Green Function-Based Method
592(2)
10.15.8 Thermal Moment Matching Method
594(1)
10.16 Temperature Monitoring or Sensing
594(1)
10.16.1 Hardware-Based Thermal Monitoring
594(1)
10.16.2 Software-Based Temperature Monitoring
594(1)
10.16.3 Hybrid Hardware- and Software-Based Thermal Monitoring
594(1)
10.17 Temperature Control or Management
595(1)
10.17.1 Basic Principle
595(1)
10.17.2 Types
596(1)
10.18 Thermal-Aware Circuit Optimization
596(6)
10.18.1 A Thermal-Aware SRAM Optimization
596(3)
10.18.2 A Thermal-Aware VCO Optimization
599(3)
10.19 Thermal-Aware Digital Design Flows
602(2)
10.19.1 Thermal-Aware Digital Synthesis
602(1)
10.19.2 Thermal-Aware Physical Design
603(1)
10.20 Thermal-Aware Register-Transfer-Level Optimization
604(1)
10.21 Thermal-Aware System-Level Design
605(1)
10.22 Questions
606(1)
10.23 References
607(12)
11 Variability-Aware AMS-SoC Design Methodologies 619(70)
11.1 Introduction
619(2)
11.2 Methods for Variability Analysis
621(22)
11.2.1 Monte Carlo Method
622(6)
11.2.2 Design of Experiments Method
628(5)
11.2.3 Corner-Based Method
633(5)
11.2.4 Fast Monte Carlo Methods
638(5)
11.3 Tool Setup for Statistical Analysis
643(1)
11.4 Methods for Variability-Aware Design Optimization
644(4)
11.4.1 Brief Concept
644(1)
11.4.2 Variability-Aware Schematic Design Optimization Flow
645(1)
11.4.3 Single Manual Layout Iteration Automatic Flow for Variability-Aware Optimization
646(2)
11.5 Variability-Aware Design of Active Pixel Sensor
648(6)
11.5.1 Impact of Variability on APS Performance Metrics
648(1)
11.5.2 Variability-Aware APS Optimization
649(5)
11.6 Variability-Aware Design of Nanoscale VCO Circuits
654(8)
11.6.1 A Conjugate-Gradient-Based Optimization of a 90-nm CMOS Current-Starved VCO
654(3)
11.6.2 A Particle Swarm Optimization Approach for a 90-nm Current-Starved VCO
657(4)
11.6.3 Process Variation Tolerant LC-VCO Design
661(1)
11.7 Variability-Aware Design of the SRAM
662(5)
11.8 Register-Transfer-Level Methods for Variability-Aware Digital Circuits
667(10)
11.8.1 Brief Overview
667(1)
11.8.2 A Simulated-Annealing-Based Statistical Approach for RTL Optimization
668(1)
11.8.3 A Taylor-Series Expansions Diagram-Based Approach for RTL Optimization
669(4)
11.8.4 Variability-Aware RTL Timing Optimization
673(2)
11.8.5 RTL Postsilicon Techniques for Variability Tolerance
675(2)
11.9 System-Level Methods for Variability-Aware Digital Design
677(1)
11.10 An Adaptive Body Bias Method for Dynamic Process Variation Compensation
678(1)
11.11 Parametric Variation Effect Mitigation in Clock Networks
679(2)
11.12 Statistical Methods for Yield Analysis
681(2)
11.13 Questions
683(2)
11.14 References
685(4)
12 Metamodel-Based Fast AMS-SoC Design Methodologies 689(76)
12.1 Introduction
689(1)
12.2 Metamodel: An Overview
689(8)
12.2.1 Concept
689(2)
12.2.2 Types
691(2)
12.2.3 Generation Flow
693(3)
12.2.4 Metamodel versus Macromodel
696(1)
12.3 Metamodel-Based Ultrafast Design Flow
697(1)
12.4 Polynomial-Based Metamodeling
698(16)
12.4.1 Theory
698(1)
12.4.2 Generation
699(2)
12.4.3 Ring Oscillator
701(1)
12.4.4 LC-VCO
702(1)
12.4.5 Verilog-AMS Integrated with Polynomial Metamodel for an OP-AMP
702(5)
12.4.6 Verilog-AMS Integrated with Polynomial Metamodel for a Memristor Oscillator
707(4)
12.4.7 Verilog-AMS Integrated with Parasitic-Aware Metamodel
711(3)
12.5 Kriging-Based Metamodeling
714(8)
12.5.1 Theory
715(2)
12.5.2 Generation
717(1)
12.5.3 Simple Kriging Metamodeling of a Clamped Bitline Sense Amplifier
718(2)
12.5.4 Ordinary Kriging Metamodeling of a Sense Amplifier
720(1)
12.5.5 Universal Kriging Metamodeling of a Phase-Locked Loop
720(2)
12.6 Neural Network-Based Metamodeling
722(11)
12.6.1 Theory
722(3)
12.6.2 Generation
725(1)
12.6.3 Neural Network Metamodel of PLL Components
726(1)
12.6.4 Intelligent Verilog-AMS
727(4)
12.6.5 Kriging Bootstrapped Training for Neural Network Metamodeling
731(2)
12.7 Ultrafast Process Variations Analysis Using Metamodels
733(4)
12.7.1 Kriging-Metamodel-Based Process Variation Analysis of a PLL
733(1)
12.7.2 Neural Network Metamodel-Based Process Variation Analysis of a PLL
733(3)
12.7.3 Kriging-Trained Neural Network-Based Process Variation Analysis of a PLL
736(1)
12.8 Polynomial-Metamodel-Based Ultrafast Design Optimization
737(10)
12.8.1 Polynomial-Metamodel-Based Optimization of a Ring Oscillator
737(2)
12.8.2 Polynomial-Metamodel-Based Optimization of a PLL
739(5)
12.8.3 Polynomial-Metamodel-Based Optimization of an OP-AMP
744(3)
12.9 Neural Network Metamodel-Based Ultrafast Design Optimization
747(5)
12.9.1 Neural Network Metamodel-Based Optimization of an OP-AMP
747(3)
12.9.2 Neural Network Metamodel-Based Variability-Aware Optimization of a PLL
750(2)
12.10 Kriging Metamodel-Based Ultrafast Design Optimization
752(6)
12.10.1 Simple Kriging Metamodel-Based Optimization of a Thermal Sensor
752(3)
12.10.2 Ordinary Kriging Metamodel-Based Optimization of a Sense Amplifier
755(3)
12.11 Questions
758(2)
12.12 References
760(5)
Index 765
Saraju Mohanty, Ph.D., is a faculty member in the Department of Computer Science and Engineering at the University of North Texas, where he directs the NanoSystem Design Laboratory (NSDL). He obtained a Ph.D. in computer science and engineering from the University of South Florida in 2003, a masters degree in systems science and automation from the Indian Institute of Science, Bangalore, India, in 1999, and a bachelors degree (honors) in electrical engineering from Orissa University of Agriculture and Technology, Bhubaneswar, India, in 1995. Dr. Mohantys research is in low-power, high-performance nanoelectronics. He is an author of hundreds of peer-reviewed journal and conference publications. Dr. Mohanty holds many U.S. patents. He has advised/co-advised many Ph.D. dissertations and numerous masters theses. Dr. Mohanty currently serves as the chair of the Technical Committee on Very Large Scale Integration (TCVLSI), IEEE Computer Society (IEEE-CS). He serves on the editorial board of many peer-reviewed international journals, including IET-CDS Journal, Elsevier Integration Journal, and Journal of Low Power Electronics. Dr. Mohanty has served as a guest editor for many journals, including ACM Journal on Emerging Technologies in Computing Systems (JETC) for an issue titled New Circuit and Architecture-Level Solutions for Multidiscipline Systems, August 2012, and IET Circuits, Devices & Systems (CDS) for an issue titled Design Methodologies for Nanoelectronic Digital and Analog Circuits, September 2013. He serves on the organizing and program committee of several international conferences. Dr. Mohanty is a senior member of the IEEE and ACM.
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