Reconfigurable computing techniques and adaptive systems are some of the most promising architectures for microprocessors. Reconfigurable and Adaptive Computing: Theory and Applications explores the latest research activities on hardware architecture for reconfigurable and adaptive computing systems.
The first section of the book covers reconfigurable systems. The book presents a software and hardware codesign flow for coarse-grained systems-on-chip, a video watermarking algorithm for the H.264 standard, a solution for regular expressions matching systems, and a novel field programmable gate array (FPGA)-based acceleration solution with MapReduce framework on multiple hardware accelerators.
The second section discusses network-on-chip, including an implementation of a multiprocessor system-on-chip platform with shared memory access, end-to-end quality-of-service metrics modeling based on a multi-application environment in network-on-chip, and a 3D ant colony routing (3D-ACR) for network-on-chip with three different 3D topologies.
The final section addresses the methodology of system codesign. The book introduces a new softwarehardware codesign flow for embedded systems that models both processors and intellectual property cores as services. It also proposes an efficient algorithm for dependent task softwarehardware codesign with the greedy partitioning and insert scheduling method (GPISM) by task graph.
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vii | |
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xiii | |
| Preface |
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xv | |
| Editors |
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xix | |
| Contributors |
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xxi | |
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Section I Reconfigurable Systems |
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Chapter 1 Effective and Efficient Design Space Exploration for Heterogeneous Microprocessor Systems-on-Chip |
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3 | (24) |
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Chapter 2 Integer DCT-Based Real-Time Video Watermarking for H.264 Encoder |
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27 | (20) |
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Chapter 3 FPGA-Accelerated Algorithm for the Regular Expressions Matching System |
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47 | (26) |
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Chapter 4 Case Study of Genome Sequencing on an FPGA: Survey and a New Perspective |
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73 | (24) |
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Section II Network-on-Chip |
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Chapter 5 Interprocess Communication via Crossbar for Shared Memory Multiprocessor Systems-on-Chip |
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97 | (24) |
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Chapter 6 Extended Quality of Service Modeling Based on Multiapplication Environment in Network-on-Chip |
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121 | (24) |
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Chapter 7 Ant Colony Routing for Latency Reduction in 3D Networks-on-Chip |
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145 | (24) |
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Luneque Del Rio Souza e Silva Jr. |
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Section III Systems Codesign |
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Chapter 8 Codem: Software/Hardware Codesign for Embedded Multicore Systems Supporting Hardware Services |
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169 | (22) |
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Chapter 9 Greedy Partitioning and Insert Scheduling Algorithm for Hardware-Software Codesign on MPSoCs |
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191 | (22) |
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| Index |
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213 | |
Nadia Nedjah is a member of the Intelligent System Research Area in the Electronics Engineering Postgraduate Program at the State University of Rio de Janeiro. Dr. Nedjah is also the editor-in-chief of the International Journal of High Performance System Architecture and Innovative Computing Applications and an associate editor of more than 10 international journals, including the International Journal of Electronics, Integration, The VLSI Journal, Microprocessors and Microsystems, and Computer & Digital Techniques. She is the author or coauthor of more than 90 journal articles and more than 150 conference papers.
Chao Wang is an associate professor in the School of Computer Science at the University of Science and Technology of China. Dr. Wang is also the technical program member for DATE, FPL, and FPT. He is the author or coauthor of more than 90 papers in international journals and conferences and an associate editor of several international journals, including Microprocessors and Microsystems, Computer & Digital Techniques, the International Journal of High Performance System Architecture, and the International Journal of Business Process Integration and Management.
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