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Robust Design of Digital Circuits on Foil [Kõva köide]

, (Katholieke Universiteit Leuven, Belgium),
  • Formaat: Hardback, 176 pages, kõrgus x laius x paksus: 254x180x13 mm, kaal: 530 g, 16 Tables, black and white; 9 Halftones, unspecified; 123 Line drawings, unspecified
  • Ilmumisaeg: 22-Sep-2016
  • Kirjastus: Cambridge University Press
  • ISBN-10: 1107127017
  • ISBN-13: 9781107127012
Teised raamatud teemal:
Robust Design of Digital Circuits on FoilSuurem pilt
  • Formaat: Hardback, 176 pages, kõrgus x laius x paksus: 254x180x13 mm, kaal: 530 g, 16 Tables, black and white; 9 Halftones, unspecified; 123 Line drawings, unspecified
  • Ilmumisaeg: 22-Sep-2016
  • Kirjastus: Cambridge University Press
  • ISBN-10: 1107127017
  • ISBN-13: 9781107127012
Teised raamatud teemal:
Püsilink: https://www.kriso.ee/db/9781107127012.html
Märksõnad:
"Covering both TFT technologies, and the theory and practice of circuit design, this book equips engineers with the technical knowledge and hands-on skills needed to make circuits on foil with organic or metal oxide based TFTs for applications such as flexible displays and RFID. It provides readers with a solid theoretical background and gives an overview of current TFT technologies including device architecture, typical parameters, and a theoretical framework for comparing different logical families. Concrete, real-world design cases, such as RFID circuits, and organic and metal oxide TFT-based 8-bit microprocessors, enable readers to grasp the practical potential of these design techniques and how they can be applied. This is an essential guide for students and professionals who need to make better transistors on foil"--

Muu info

A practical guide to the theory and applications of TFT technologies and circuit designs for those in academia and in industry.
Preface xi
List of Symbols and Abbreviations
xiii
1 Thin-Film Transistor Technologies on the Move? From Backplane Driver to Ubiquitous Circuit Enabler?
1(8)
1.1 Backplanes for Active Matrix Displays
1(6)
1.1.1 Amorphous Silicon
2(1)
1.1.2 Low-Temperature Polycrystalline Silicon
3(1)
1.1.3 Organic Thin-Film Transistors
3(1)
1.1.4 Metal-Oxide Thin-Film Transistors
4(1)
1.1.5 Current TFT Technology Overview
5(1)
1.1.6 Options for Flexible Displays
6(1)
1.2 Large Area Sensors and Circuits (On Foil)
7(2)
2 Organic and Metal-Oxide Thin-Film Transistors
9(24)
2.1 Device Configurations
9(1)
2.2 Operation Principle
10(4)
2.2.1 Operation Principle of a Single-Gate Transistor
10(3)
2.2.2 Technology Options for Multiple Threshold Voltages
13(1)
2.3 Typical Layout Rules in the Technologies Used in This Book
14(1)
2.4 Technologies Used in This Book
15(10)
2.4.1 Organic p-Type Technology of Polymer Vision
15(1)
2.4.2 Organic p-Type Dual-Gate Technology of Polymer Vision
16(3)
2.4.3 Pentacene (p-Type) Thin-Film Transistors on Al2O3 as Gate Dielectric
19(2)
2.4.4 a-IGZO (n-Type) Technology on Al2O3 as Gate Dielectric
21(1)
2.4.5 Hybrid Complementary Organic/Metal-Oxide Technology
22(1)
2.4.6 Hybrid Complementary Organic/Metal-Oxide Technology on PEN-Foil
23(2)
2.5 Trends in Circuit Integration
25(6)
2.5.1 Display Periphery
25(1)
2.5.2 Digital Logic
26(3)
2.5.3 Analog Circuits
29(2)
2.6 Summary
31(2)
3 Basic Gates
33(41)
3.1 Figures-of-Merit
33(2)
3.2 Logic Families
35(1)
3.3 Unipolar Logic
36(29)
3.3.1 Single VT, Depletion-Load, or Zero-VGS-Load Logic
37(1)
3.3.1.1 VTC of the Zero-VGS-Load Inverter
38(3)
3.3.1.2 Static Parameters of the Zero-VGS-Load Inverter
41(3)
3.3.1.3 Dynamic Behavior of the Zero-VGS-Load Inverter
44(8)
3.3.2 Dual VT, Zero-VGS-Load Logic by Dual-Gate TFTs
52(1)
3.3.2.1 VTC of a Dual- VT Zero- VGS-Load Inverter
53(1)
3.3.2.2 Dual-Gate Zero-VGS-Load Inverter
54(1)
3.3.2.3 Optimized Dual-Gate Zero-VGS-Load Inverter
55(2)
3.3.3 Single VT, Enhancement-Load, or Diode-Load Logic
57(1)
3.3.3.1 VTC of the Diode-Load Inverter
58(2)
3.3.3.2 Static Behavior of the Diode-Load Inverter
60(1)
3.3.3.3 Dynamic Behavior of the Diode-Load Inverter
61(2)
3.3.4 Dual VT, Diode-Load Logic in Dual-Gate Technologies
63(2)
3.4 Complementary Logic
65(6)
3.4.1 VTC of the Complementary Inverter
65(2)
3.4.2 Static Behavior of the Complementary Inverter
67(1)
3.4.2.1 VM
67(1)
3.4.2.2 Gain
67(1)
3.4.3 Dynamic Behavior of the Complementary Inverter
68(1)
3.4.3.1 Study of the Complementary Inverter Capacitances
68(3)
3.5 Conclusions
71(2)
3.6 Suggestions to Improve the Inverter Performance
73(1)
3.6.1 Level-Shifter
73(1)
3.6.2 Self-Aligned Technology
73(1)
4 Variability
74(18)
4.1 Classifications
74(1)
4.2 Sources of Process Variation
75(2)
4.2.1 Semiconductor
75(1)
4.2.1.1 Dielectric
76(1)
4.2.2 Contacts
76(1)
4.2.3 Foil
77(1)
4.3 Influence of Parameter Variation on the Yield of Logic Circuits
77(2)
4.4 How to Cope with WID and D2D Parameter Variations
79(11)
4.4.1 Designing with WID Variations
80(6)
4.4.2 Designing with D2D Variations -- Corner Analysis
86(1)
4.4.3 Adaptive Back-Gate Control for Threshold Voltage Compensation
87(2)
4.4.4 Variability and Large Area Electronics
89(1)
4.5 Conclusions
90(2)
5 Design Case: RFID Tags
92(32)
5.1 RFID and the Road Map for Low-Cost RFID Tags
93(4)
5.2 A Fully Integrated, 64-Bit Organic RFID Tag
97(7)
5.2.1 Technology
97(1)
5.2.2 RFID Measurement Setup
98(1)
5.2.3 Organic Transponder Chip
99(1)
5.2.4 Organic Rectifier
100(3)
5.2.5 Organic RFID Tag Using DC Load Modulation
103(1)
5.3 Adding More Complexity to the Transponder Chips
104(4)
5.4 Can We Meet the Data Rate Targets for EPC Transponder Chips?
108(6)
5.4.1 Organic Transponder Chips
109(1)
5.4.2 Metal-Oxide NFC Chips
110(2)
5.4.3 Faster Transponder Chips by Other Logic Types
112(2)
5.5 Bi-Directional Communication
114(4)
5.6 RFID Transponder Chips with Increased Robustness
118(4)
5.7 Conclusions
122(2)
6 Design Case: Organic Microprocessor
124(19)
6.1 Introduction
124(1)
6.2 Technology and Logic Family
125(2)
6.3 Architecture and Measurement Results of the Organic ALU-Foil
127(7)
6.4 Integrated Organic Microprocessor on Foil
134(1)
6.5 Second Generation Thin-Film Processor
135(6)
6.6 Conclusions
141(2)
Bibliography 143(16)
Index 159
Kris Myny is Senior Researcher in the Large Area Electronics Department at IMEC, Leuven. He received the 2010 IMEC Scientific Excellence Award, and the 20112012 IEEE SSCS Pre-doctoral Achievement Award. Jan Genoe is Senior Principal Scientist in the Large Area Electronics Department at IMEC, Leuven, Head of the Polymer and Molecular Electronics Group and a part-time professor at Katholieke Universiteit Leuven. He is a member of the ISSCC's Technology Directions International Programmes Sub-Committee and has authored and co-authored over 150 papers in refereed journals. Wim Dehaene is a professor at the Katholieke Universiteit Leuven and Head of the ESAT-MICAS Research Division. He is also a part-time Principal Scientist at IMEC, a senior member of the IEEE, a member of the Technical Program Committee of ESSCIRC, and the 2016 Short Course Chair for ISSCC.