About the Authors |
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xi | |
About the Technical Reviewers |
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xiii | |
Foreword |
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xv | |
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Preface |
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xix | |
Acknowledgments |
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xxi | |
Introduction |
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xxiii | |
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1 | (44) |
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Lack of Open System Design |
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3 | (1) |
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Misinterpretation of Firmware Definition |
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4 | (1) |
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5 | (1) |
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The Importance of Programming Knowledge |
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6 | (2) |
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8 | (37) |
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10 | (4) |
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14 | (26) |
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Distinction Between Firmware and Software |
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40 | (1) |
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Introduction of Non-Host Firmware |
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41 | (1) |
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Introduction to Device Firmware |
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42 | (1) |
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Open Source vs. Closed Source |
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43 | (1) |
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44 | (1) |
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Chapter 2 Knowing Your Hardware |
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45 | (100) |
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47 | (21) |
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Instruction Set Architecture |
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50 | (5) |
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55 | (7) |
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62 | (6) |
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68 | (41) |
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Internals of x86 Processors |
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68 | (41) |
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109 | (9) |
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109 | (3) |
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Main Memory Address Range |
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112 | (2) |
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114 | (2) |
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Main Memory Upper Address Range |
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116 | (2) |
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118 | (15) |
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Industry Standard Architecture (ISA) Bus |
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119 | (1) |
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Extended Industry Standard Architecture (EISA) Bus |
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120 | (1) |
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Peripheral Component Interconnect (PCI) Bus |
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121 | (8) |
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Peripheral Component Interconnect Express (PCIe) Bus |
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129 | (1) |
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Serial AT attachment (SATA) Bus |
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130 | (1) |
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Universal Serial Bus (USB) |
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130 | (2) |
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ARM Advanced Microcontroller Bus Architecture (AMBA) |
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132 | (1) |
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Platform Runtime Power Management |
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133 | (9) |
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135 | (2) |
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ACPI System Description Tables |
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137 | (2) |
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139 | (2) |
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141 | (1) |
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142 | (3) |
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Chapter 3 Understanding the BIOS and Minimalistic Design |
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145 | (68) |
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146 | (13) |
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Working Principle of BIOS |
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147 | (2) |
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Where Does the BIOS Reside? |
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149 | (2) |
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151 | (3) |
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154 | (5) |
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Designing a Minimalistic Bootloader |
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159 | (52) |
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Minimalistic Bootloader Design on x86 Platform |
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160 | (37) |
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Minimalistic Bootloader Design on the ARM Platform |
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197 | (14) |
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211 | (2) |
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Chapter 4 System Firmware Architecture |
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213 | (102) |
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215 | (45) |
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217 | (27) |
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Platform Initialization Specification |
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244 | (16) |
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260 | (31) |
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262 | (18) |
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280 | (11) |
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Slim Bootloader Architecture |
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291 | (21) |
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293 | (19) |
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312 | (3) |
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Chapter 5 Hybrid Firmware Architecture |
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315 | (70) |
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Understanding the System Firmware Development Model |
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319 | (5) |
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321 | (1) |
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Platform Initialization (PI) |
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321 | (3) |
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Understanding the System Firmware Supply Chain |
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324 | (3) |
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324 | (1) |
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325 | (1) |
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326 | (1) |
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Spectrum of Open and Closed Source System Firmware |
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327 | (3) |
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Current Industry Trends with Hybrid Firmware |
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330 | (7) |
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Challenges Seen by Silicon Vendors with Open Sourcing |
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337 | (6) |
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338 | (1) |
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Third-Party IP Restrictions |
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339 | (1) |
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Silicon Reference Code Development Without Compatibility |
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339 | (1) |
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Early Platform Enabling with Non-PRQ'ed Silicon |
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340 | (1) |
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Distinguished Product Features |
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340 | (1) |
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340 | (1) |
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341 | (1) |
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Documentation Is an Afterthought |
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342 | (1) |
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Importance of a Specific System Firmware Architecture |
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342 | (1) |
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Challenges Faced by the Open Community with Closed Sourcing |
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343 | (3) |
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343 | (1) |
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344 | (1) |
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344 | (1) |
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344 | (1) |
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Ungoverned Growth for Closed Source Blobs |
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345 | (1) |
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Hybrid Firmware Architecture |
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346 | (23) |
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346 | (2) |
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Firmware Development Using Hybrid Firmware Architecture |
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348 | (3) |
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Conventional Closed Source Firmware in the Hybrid Work Model |
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351 | (18) |
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Application of Hybrid Firmware Architecture |
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369 | (13) |
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382 | (3) |
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385 | (80) |
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390 | (23) |
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391 | (16) |
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407 | (2) |
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Depthcharge Code Structure |
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409 | (2) |
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411 | (2) |
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413 | (14) |
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UEFI Payload Architecture |
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415 | (7) |
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422 | (2) |
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UEFI Payload Code Structure |
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424 | (2) |
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426 | (1) |
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427 | (20) |
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429 | (10) |
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439 | (2) |
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441 | (2) |
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443 | (4) |
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Universal Payload Layer (UPL) |
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447 | (14) |
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Universal Payload Image Format |
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452 | (3) |
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Universal Payload Interface |
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455 | (3) |
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Implementation of Universal Payload Layer |
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458 | (3) |
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461 | (4) |
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465 | (114) |
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Reduce FW Booting Time Using Multi-Threaded Environment |
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467 | (24) |
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469 | (1) |
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470 | (1) |
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470 | (1) |
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470 | (1) |
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471 | (1) |
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471 | (1) |
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471 | (1) |
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472 | (1) |
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472 | (4) |
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476 | (2) |
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Boot Time Measurement with existing System Firmware Design |
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478 | (3) |
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481 | (9) |
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Firmware Boot Time Optimization for Capsule Update |
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490 | (1) |
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Firmware Boot Time Optimization Conclusion |
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490 | (1) |
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Supporting New CPU Architecture Migration with UEFI |
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491 | (26) |
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497 | (1) |
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498 | (4) |
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502 | (4) |
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506 | (11) |
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Porting a New CPU Architecture (Elixir) Conclusion |
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517 | (1) |
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Reducing the System Firmware Boundary with LinuxBoot |
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517 | (22) |
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522 | (1) |
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523 | (4) |
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527 | (4) |
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531 | (8) |
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539 | (1) |
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Adopting a Hybrid Firmware Development Model |
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539 | (38) |
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543 | (1) |
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543 | (7) |
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550 | (4) |
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554 | (23) |
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Hybrid Firmware Development Model Conclusion |
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577 | (1) |
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577 | (2) |
Appendix A Postcodes |
|
579 | (6) |
Appendix B Data Types |
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585 | (4) |
Glossary |
|
589 | (6) |
Reference |
|
595 | (1) |
Websites |
|
595 | (3) |
References for the Chapter 1 |
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598 | (1) |
Books |
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598 | (1) |
Conferences, Journals, and Papers |
|
598 | (1) |
Specifications and Guidelines |
|
599 | (1) |
Websites |
|
599 | (2) |
References for Chapter 5 |
|
601 | (2) |
Index |
|
603 | |