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VLSI Design Methodology Development [Pehme köide]

  • Formaat: Paperback / softback, 752 pages, kõrgus x laius x paksus: 34x232x182 mm, kaal: 1180 g
  • Ilmumisaeg: 10-Jul-2020
  • Kirjastus: Pearson
  • ISBN-10: 0135732417
  • ISBN-13: 9780135732410
Teised raamatud teemal:
  • Formaat: Paperback / softback, 752 pages, kõrgus x laius x paksus: 34x232x182 mm, kaal: 1180 g
  • Ilmumisaeg: 10-Jul-2020
  • Kirjastus: Pearson
  • ISBN-10: 0135732417
  • ISBN-13: 9780135732410
Teised raamatud teemal:
The Complete, Modern Tutorial on Practical VLSI Chip Design, Validation, and Analysis

As microelectronics engineers design complex chips using existing circuit libraries, they must ensure correct logical, physical, and electrical properties, and prepare for reliable foundry fabrication. VLSI Design Methodology Development focuses on the design and analysis steps needed to perform these tasks and successfully complete a modern chip design.

Microprocessor design authority Tom Dillinger carefully introduces core concepts, and then guides engineers through modeling, functional design validation, design implementation, electrical analysis, and release to manufacturing. Writing from the engineer’s perspective, he covers underlying EDA tool algorithms, flows, criteria for assessing project status, and key tradeoffs and interdependencies. This fresh and accessible tutorial will be valuable to all VLSI system designers, senior undergraduate or graduate students of microelectronics design, and companies offering internal courses for engineers at all levels.
  • Reflect complexity, cost, resources, and schedules in planning a chip design project
  • Perform hierarchical design decomposition, floorplanning, and physical integration, addressing DFT, DFM, and DFY requirements
  • Model functionality and behavior, validate designs, and verify formal equivalency
  • Apply EDA tools for logic synthesis, placement, and routing
  • Analyze timing, noise, power, and electrical issues
  • Prepare for manufacturing release and bring-up, from mastering ECOs to qualification

This guide is for all VLSI system designers, senior undergraduate or graduate students of microelectronics design, and companies offering internal courses for engineers at all levels. It is applicable to engineering teams undertaking new projects and migrating existing designs to new technologies.

Preface xiv
Topic I: Overview of VLSI Design Methodology 1(220)
I.1 Methodology Guidelines for Logical and Physical Design Hierarchy Correspondence
6(2)
I.2 Managing Inter-Block Glue Logic
8(5)
Chapter 1 Introduction
13(118)
1.1 Definitions
13(8)
1.2 Intellectual Property (IP) Models
21(21)
1.3 Tapeout and NRE Fabrication Cost
42(2)
1.4 Fabrication Technology
44(61)
1.5 Power and Clock Domains On-chip
105(8)
1.6 Physical Design Planning
113(13)
1.7 Summary
126(1)
References
127(2)
Further Research
129(2)
Chapter 2 VLSI Design Methodology
131(62)
2.1 IP Design Methodology
131(10)
2.2 SoC Physical Design Methodology
141(24)
2.3 EDA Tool and Release Flow Management
165(3)
2.4 Design Methodology "Trailblazing" and Reference Flows
168(3)
2.5 Design Data Management (DDM)
171(4)
2.6 Power and Clock Domain Management
175(2)
2.7 Design for Testability (DFT)
177(7)
2.8 Design-for-Manufacturability (DFM) and Design-for-Yield (DFY) Requirements
184(1)
2.9 Design Optimization
185(1)
2.10 Methodology Checks
186(4)
References
190(1)
Further Research
190(3)
Chapter 3 Hierarchical Design Decomposition
193(28)
3.1 Logical-to-Physical Correspondence
193(4)
3.2 Division of SRAM Array Versus Non-Array Functionality
197(1)
3.3 Division of Dataflow and Control Flow Functionality
198(4)
3.4 Design Block Size for Logic Synthesis and Physical Design
202(4)
3.5 Power and Clock Domain Considerations
206(1)
3.6 Opportunities for Reuse of Hierarchical Units
207(1)
3.7 Automated Test Pattern Generation (ATPG) Limitations
208(3)
3.8 Intangibles
211(1)
3.9 The Impact of Changes to the SoC Model Hierarchy During Design
212(2)
3.10 Generating Hierarchical Electrical Abstracts Versus Top-Level Flat Analysis
214(2)
3.11 Methodologies for Top-Level Logical and Physical Hierarchies
216(2)
3.12 Summary
218(1)
References
219(1)
Further Research
219(2)
Topic II: Modeling 221(36)
Chapter 4 Cell and IP Modeling
223(34)
4.1 Functional Modeling for Cells and IP
223(17)
4.2 Physical Models for Library Cells
240(1)
4.3 Library Cell Models for Analysis Flows
241(10)
4.4 Design for End-of-Life (EOL) Circuit Parameter Drift
251(2)
4.5 Summary
253(1)
References
253(1)
Further Research
254(3)
Topic III: Design Validation 257(60)
Chapter 5 Characteristics of Functional Validation
259(42)
5.1 Software Simulation
259(3)
5.2 Testbench Stimulus Development
262(6)
5.3 Hardware-Accelerated Simulation: Emulation and Prototyping
268(7)
5.4 Behavioral Co-simulation
275(1)
5.5 Switch-Level and Symbolic Simulation
275(6)
5.6 Simulation Throughput and Resource Planning
281(3)
5.7 Validation of Production Test Patterns
284(4)
5.8 Event Trace Logging
288(1)
5.9 Model Coverage Analysis
289(6)
5.10 Switching Activity Factor Estimates for Power Dissipation Analysis
295(1)
5.11 Summary
296(1)
References
297(1)
Further Research
298(3)
Chapter 6 Characteristics of Formal Equivalency Verification
301(16)
6.1 RTL Combinational Model Equivalency
301(1)
6.2 State Mapping for Equivalency
302(3)
6.3 Combinational Logic Cone Analysis
305(1)
6.4 Use of Model Input Assertions for Equivalency
306(1)
6.5 Sequential Model Equivalency
307(2)
6.6 Functional and Test-Mode Equivalence Verification
309(1)
6.7 Array Equivalence Verification
310(3)
6.8 Summary
313(1)
References
314(1)
Further Research
314(3)
Topic IV: Design Implementation 317(86)
Chapter 7 Logic Synthesis
319(44)
7.1 Level of Hardware Description Language Modeling
319(1)
7.2 Generation and Verification of Timing Constraints
320(8)
7.3 Technology Mapping to the Cell Library
328(7)
7.4 Signal Repowering and "High-Fan-out" Net Synthesis (HFNS)
335(4)
7.5 Post-Synthesis Netlist Characteristics
339(1)
7.6 Synthesis with a Power Format File
340(3)
7.7 Post-Technology Mapping Optimizations for Timing and Power
343(5)
7.8 Hold Timing Optimization
348(2)
7.9 Clock Tree Synthesis (CTS)
350(3)
7.10 Integration of Hard IP Macros in Synthesis
353(1)
7.11 Low-Effort Synthesis (LES) Methodology
354(5)
7.12 Summary
359(1)
References
360(1)
Further Research
360(3)
Chapter 8 Placement
363(10)
8.1 Global Floorplanning of Hierarchical Units
363(3)
8.2 Parasitic Interconnect Estimation
366(1)
8.3 Cell Placement
367(2)
8.4 Clock Tree Local Buffer Placement
369(1)
8.5 Summary
370(1)
References
370(1)
Further Research
370(3)
Chapter 9 Routing
373(30)
9.1 Routing Introduction
373(5)
9.2 Global and Detailed Routing Phases
378(5)
9.3 Back End Of Line Interconnect "Stacks"
383(4)
9.4 Routing Optimizations
387(12)
9.5 Summary
399(1)
References
400(1)
Further Research
400(3)
Topic V: Electrical Analysis 403(190)
Chapter 10 Layout Parasitic Extraction and Electrical Modeling
405(38)
10.1 Introduction
405(6)
10.2 Cell- and Transistor-Level Parasitic Modeling for Cell Characterization
411(20)
10.3 Decoupling Capacitance Calculation for Power Grid Analysis
431(2)
10.4 Interconnect Extraction
433(5)
10.5 "Selected Net" Extraction Options
438(1)
10.6 RLC Modeling
439(1)
10.7 Summary
439(1)
References
440(2)
Further Research
442(1)
Chapter 11 Timing Analysis
443(32)
11.1 Cell Delay Calculation
443(3)
11.2 Interconnect Delay Calculation
446(6)
11.3 Electrical Design Checks
452(1)
11.4 Static Timing Analysis
453(16)
11.5 Summary
469(1)
References
470(2)
Further Research
472(3)
Chapter 12 Noise Analysis
475(20)
12.1 Introduction to Noise Analysis
475(1)
12.2 Static Noise Analysis, Part I
476(5)
12.3 Noise Impact on Delay
481(4)
12.4 Electrical Models for Static Noise Analysis
485(3)
12.5 Static Noise Analysis, Part II
488(3)
12.6 Summary
491(1)
References
492(1)
Further Research
493(2)
Chapter 13 Power Analysis
495(14)
13.1 Introduction to Power Analysis
495(2)
13.2 Models for Switching Activity Power Dissipation
497(4)
13.3 IP Power Models
501(1)
13.4 Device Self-Heat Models
502(2)
13.5 Design-for-Power Feedback from Power Analysis
504(1)
13.6 Summary
505(1)
References
506(1)
Further Research
506(3)
Chapter 14 Power Rail Voltage Drop Analysis
509(20)
14.1 Introduction to Power Rail Voltage Drop Analysis
509(3)
14.2 Static I*R Rail Analysis
512(1)
14.3 Dynamic P/G Voltage Drop Analysis
513(13)
14.4 Summary
526(1)
References
526(1)
Further Research
527(2)
Chapter 15 Electromigration (EM) Reliability Analysis
529(30)
15.1 Introduction to EM Reliability Analysis
529(6)
15.2 Fundamentals of Electromigration
535(10)
15.3 Power Rail Electromigration Analysis: powerEM
545(3)
15.4 Signal Interconnect Electromigration Analysis: sigEM
548(7)
15.5 Summary
555(1)
References
555(1)
Further Research
556(3)
Chapter 16 Miscellaneous Electrical Analysis Requirements
559(34)
16.1 SleepFET Power Rail Analysis
559(3)
16.2 Substrate Noise Injection and Latchup Analysis
562(6)
16.3 Electrostatic Discharge (ESD) Checking
568(8)
16.4 Soft Error Rate (SER) Analysis
576(14)
16.5 Summary
590(1)
References
590(1)
Further Research
591(2)
Topic VI: Preparation for Manufacturing Release and Bring-Up 593(112)
Chapter 17 ECOs
595(12)
17.1 Application of an Engineering Change
595(4)
17.2 ECOs and Equivalency Verification
599(1)
17.3 Use of Post-Silicon Cells for ECOs
600(2)
17.4 ECOs and Design Version Management
602(3)
17.5 Summary
605(1)
References
606(1)
Further Research
606(1)
Chapter 18 Physical Design Verification
607(18)
18.1 Design Rule Checking (DRC)
607(3)
18.2 Layout-Versus-Schematic (LVS) Verification
610(6)
18.3 Electrical Rule Checking (ERC)
616(2)
18.4 Lithography Process Checking (LPC)
618(2)
18.5 DRC Waivers
620(2)
18.6 Summary
622(1)
Further Research
622(3)
Chapter 19 Design for Testability Analysis
625(52)
19.1 Stuck-at Fault Models and Automated Test Pattern Generation (ATPG)
625(11)
19.2 DFT Design Rule Checking
636(2)
19.3 Memory Built-in Self-Test (MBIST)
638(7)
19.4 Logic Built-in Self-Test (LBIST)
645(14)
19.5 Delay Faults
659(5)
19.6 Bridging Faults
664(1)
19.7 Pattern Diagnostics
665(7)
19.8 Summary
672(1)
References
673(1)
Further Research
674(3)
Chapter 20 Preparation for Tapeout
677(16)
20.1 Introduction to Tapeout Preparation
677(1)
20.2 Foundry Interface Release Tapeout Options
678(6)
20.3 Tapeout Checklist Review
684(5)
20.4 Project Tapeout Planning
689(3)
Further Research
692(1)
Chapter 21 Post-Silicon Debug and Characterization ("Bring-up") and Product Qualification
693(12)
21.1 Systematic Test Fails
693(2)
21.2 "Shmoo" of Performance Dropout Versus Frequency
695(3)
21.3 Product Qualification
698(4)
21.4 Summary
702(1)
Reference
702(1)
Further Research
703(2)
Epilogue 705(6)
Index 711
Thomas Dillin ger has more than 30 years of experience in the microelectronics industry, including semiconductor circuit design, fabrication process research, and EDA tool development. He has been responsible for the design methodology development for ASIC, SoC, and complex microprocessor chips for IBM, Sun Microsystems/Oracle, and AMD. He is the author of the book VLSI Engineering and has written for SemiWiki.