Preface |
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xiv | |
Topic I: Overview of VLSI Design Methodology |
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1 | (220) |
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I.1 Methodology Guidelines for Logical and Physical Design Hierarchy Correspondence |
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6 | (2) |
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I.2 Managing Inter-Block Glue Logic |
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8 | (5) |
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13 | (118) |
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13 | (8) |
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1.2 Intellectual Property (IP) Models |
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21 | (21) |
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1.3 Tapeout and NRE Fabrication Cost |
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42 | (2) |
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1.4 Fabrication Technology |
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44 | (61) |
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1.5 Power and Clock Domains On-chip |
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105 | (8) |
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1.6 Physical Design Planning |
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113 | (13) |
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126 | (1) |
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127 | (2) |
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129 | (2) |
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Chapter 2 VLSI Design Methodology |
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131 | (62) |
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2.1 IP Design Methodology |
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131 | (10) |
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2.2 SoC Physical Design Methodology |
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141 | (24) |
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2.3 EDA Tool and Release Flow Management |
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165 | (3) |
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2.4 Design Methodology "Trailblazing" and Reference Flows |
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168 | (3) |
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2.5 Design Data Management (DDM) |
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171 | (4) |
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2.6 Power and Clock Domain Management |
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175 | (2) |
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2.7 Design for Testability (DFT) |
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177 | (7) |
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2.8 Design-for-Manufacturability (DFM) and Design-for-Yield (DFY) Requirements |
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184 | (1) |
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185 | (1) |
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186 | (4) |
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190 | (1) |
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190 | (3) |
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Chapter 3 Hierarchical Design Decomposition |
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193 | (28) |
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3.1 Logical-to-Physical Correspondence |
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193 | (4) |
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3.2 Division of SRAM Array Versus Non-Array Functionality |
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197 | (1) |
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3.3 Division of Dataflow and Control Flow Functionality |
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198 | (4) |
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3.4 Design Block Size for Logic Synthesis and Physical Design |
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202 | (4) |
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3.5 Power and Clock Domain Considerations |
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206 | (1) |
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3.6 Opportunities for Reuse of Hierarchical Units |
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207 | (1) |
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3.7 Automated Test Pattern Generation (ATPG) Limitations |
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208 | (3) |
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211 | (1) |
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3.9 The Impact of Changes to the SoC Model Hierarchy During Design |
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212 | (2) |
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3.10 Generating Hierarchical Electrical Abstracts Versus Top-Level Flat Analysis |
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214 | (2) |
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3.11 Methodologies for Top-Level Logical and Physical Hierarchies |
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216 | (2) |
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218 | (1) |
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219 | (1) |
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219 | (2) |
Topic II: Modeling |
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221 | (36) |
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Chapter 4 Cell and IP Modeling |
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223 | (34) |
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4.1 Functional Modeling for Cells and IP |
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223 | (17) |
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4.2 Physical Models for Library Cells |
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240 | (1) |
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4.3 Library Cell Models for Analysis Flows |
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241 | (10) |
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4.4 Design for End-of-Life (EOL) Circuit Parameter Drift |
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251 | (2) |
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253 | (1) |
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253 | (1) |
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254 | (3) |
Topic III: Design Validation |
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257 | (60) |
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Chapter 5 Characteristics of Functional Validation |
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259 | (42) |
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259 | (3) |
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5.2 Testbench Stimulus Development |
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262 | (6) |
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5.3 Hardware-Accelerated Simulation: Emulation and Prototyping |
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268 | (7) |
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5.4 Behavioral Co-simulation |
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275 | (1) |
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5.5 Switch-Level and Symbolic Simulation |
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275 | (6) |
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5.6 Simulation Throughput and Resource Planning |
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281 | (3) |
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5.7 Validation of Production Test Patterns |
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284 | (4) |
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288 | (1) |
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5.9 Model Coverage Analysis |
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289 | (6) |
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5.10 Switching Activity Factor Estimates for Power Dissipation Analysis |
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295 | (1) |
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296 | (1) |
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297 | (1) |
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298 | (3) |
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Chapter 6 Characteristics of Formal Equivalency Verification |
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301 | (16) |
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6.1 RTL Combinational Model Equivalency |
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301 | (1) |
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6.2 State Mapping for Equivalency |
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302 | (3) |
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6.3 Combinational Logic Cone Analysis |
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305 | (1) |
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6.4 Use of Model Input Assertions for Equivalency |
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306 | (1) |
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6.5 Sequential Model Equivalency |
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307 | (2) |
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6.6 Functional and Test-Mode Equivalence Verification |
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309 | (1) |
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6.7 Array Equivalence Verification |
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310 | (3) |
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313 | (1) |
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314 | (1) |
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314 | (3) |
Topic IV: Design Implementation |
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317 | (86) |
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Chapter 7 Logic Synthesis |
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319 | (44) |
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7.1 Level of Hardware Description Language Modeling |
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319 | (1) |
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7.2 Generation and Verification of Timing Constraints |
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320 | (8) |
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7.3 Technology Mapping to the Cell Library |
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328 | (7) |
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7.4 Signal Repowering and "High-Fan-out" Net Synthesis (HFNS) |
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335 | (4) |
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7.5 Post-Synthesis Netlist Characteristics |
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339 | (1) |
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7.6 Synthesis with a Power Format File |
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340 | (3) |
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7.7 Post-Technology Mapping Optimizations for Timing and Power |
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343 | (5) |
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7.8 Hold Timing Optimization |
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348 | (2) |
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7.9 Clock Tree Synthesis (CTS) |
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350 | (3) |
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7.10 Integration of Hard IP Macros in Synthesis |
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353 | (1) |
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7.11 Low-Effort Synthesis (LES) Methodology |
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354 | (5) |
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359 | (1) |
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360 | (1) |
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360 | (3) |
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363 | (10) |
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8.1 Global Floorplanning of Hierarchical Units |
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363 | (3) |
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8.2 Parasitic Interconnect Estimation |
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366 | (1) |
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367 | (2) |
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8.4 Clock Tree Local Buffer Placement |
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369 | (1) |
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370 | (1) |
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370 | (1) |
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370 | (3) |
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373 | (30) |
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373 | (5) |
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9.2 Global and Detailed Routing Phases |
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378 | (5) |
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9.3 Back End Of Line Interconnect "Stacks" |
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383 | (4) |
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9.4 Routing Optimizations |
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387 | (12) |
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399 | (1) |
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400 | (1) |
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400 | (3) |
Topic V: Electrical Analysis |
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403 | (190) |
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Chapter 10 Layout Parasitic Extraction and Electrical Modeling |
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405 | (38) |
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405 | (6) |
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10.2 Cell- and Transistor-Level Parasitic Modeling for Cell Characterization |
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411 | (20) |
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10.3 Decoupling Capacitance Calculation for Power Grid Analysis |
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431 | (2) |
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10.4 Interconnect Extraction |
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433 | (5) |
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10.5 "Selected Net" Extraction Options |
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438 | (1) |
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439 | (1) |
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439 | (1) |
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440 | (2) |
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442 | (1) |
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Chapter 11 Timing Analysis |
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443 | (32) |
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11.1 Cell Delay Calculation |
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443 | (3) |
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11.2 Interconnect Delay Calculation |
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446 | (6) |
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11.3 Electrical Design Checks |
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452 | (1) |
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11.4 Static Timing Analysis |
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453 | (16) |
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469 | (1) |
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470 | (2) |
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472 | (3) |
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Chapter 12 Noise Analysis |
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475 | (20) |
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12.1 Introduction to Noise Analysis |
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475 | (1) |
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12.2 Static Noise Analysis, Part I |
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476 | (5) |
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12.3 Noise Impact on Delay |
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481 | (4) |
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12.4 Electrical Models for Static Noise Analysis |
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485 | (3) |
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12.5 Static Noise Analysis, Part II |
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488 | (3) |
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491 | (1) |
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492 | (1) |
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493 | (2) |
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Chapter 13 Power Analysis |
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495 | (14) |
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13.1 Introduction to Power Analysis |
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495 | (2) |
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13.2 Models for Switching Activity Power Dissipation |
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497 | (4) |
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501 | (1) |
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13.4 Device Self-Heat Models |
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502 | (2) |
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13.5 Design-for-Power Feedback from Power Analysis |
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504 | (1) |
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505 | (1) |
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506 | (1) |
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506 | (3) |
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Chapter 14 Power Rail Voltage Drop Analysis |
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509 | (20) |
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14.1 Introduction to Power Rail Voltage Drop Analysis |
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509 | (3) |
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14.2 Static I*R Rail Analysis |
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512 | (1) |
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14.3 Dynamic P/G Voltage Drop Analysis |
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513 | (13) |
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526 | (1) |
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526 | (1) |
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527 | (2) |
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Chapter 15 Electromigration (EM) Reliability Analysis |
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529 | (30) |
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15.1 Introduction to EM Reliability Analysis |
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529 | (6) |
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15.2 Fundamentals of Electromigration |
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535 | (10) |
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15.3 Power Rail Electromigration Analysis: powerEM |
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545 | (3) |
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15.4 Signal Interconnect Electromigration Analysis: sigEM |
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548 | (7) |
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555 | (1) |
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555 | (1) |
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556 | (3) |
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Chapter 16 Miscellaneous Electrical Analysis Requirements |
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559 | (34) |
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16.1 SleepFET Power Rail Analysis |
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559 | (3) |
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16.2 Substrate Noise Injection and Latchup Analysis |
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562 | (6) |
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16.3 Electrostatic Discharge (ESD) Checking |
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568 | (8) |
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16.4 Soft Error Rate (SER) Analysis |
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576 | (14) |
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590 | (1) |
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590 | (1) |
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591 | (2) |
Topic VI: Preparation for Manufacturing Release and Bring-Up |
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593 | (112) |
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595 | (12) |
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17.1 Application of an Engineering Change |
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595 | (4) |
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17.2 ECOs and Equivalency Verification |
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599 | (1) |
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17.3 Use of Post-Silicon Cells for ECOs |
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600 | (2) |
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17.4 ECOs and Design Version Management |
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602 | (3) |
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605 | (1) |
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606 | (1) |
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606 | (1) |
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Chapter 18 Physical Design Verification |
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607 | (18) |
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18.1 Design Rule Checking (DRC) |
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607 | (3) |
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18.2 Layout-Versus-Schematic (LVS) Verification |
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610 | (6) |
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18.3 Electrical Rule Checking (ERC) |
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616 | (2) |
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18.4 Lithography Process Checking (LPC) |
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618 | (2) |
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620 | (2) |
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622 | (1) |
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622 | (3) |
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Chapter 19 Design for Testability Analysis |
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625 | (52) |
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19.1 Stuck-at Fault Models and Automated Test Pattern Generation (ATPG) |
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625 | (11) |
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19.2 DFT Design Rule Checking |
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636 | (2) |
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19.3 Memory Built-in Self-Test (MBIST) |
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638 | (7) |
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19.4 Logic Built-in Self-Test (LBIST) |
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645 | (14) |
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659 | (5) |
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664 | (1) |
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665 | (7) |
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672 | (1) |
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673 | (1) |
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674 | (3) |
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Chapter 20 Preparation for Tapeout |
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677 | (16) |
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20.1 Introduction to Tapeout Preparation |
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677 | (1) |
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20.2 Foundry Interface Release Tapeout Options |
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678 | (6) |
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20.3 Tapeout Checklist Review |
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684 | (5) |
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20.4 Project Tapeout Planning |
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689 | (3) |
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692 | (1) |
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Chapter 21 Post-Silicon Debug and Characterization ("Bring-up") and Product Qualification |
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693 | (12) |
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21.1 Systematic Test Fails |
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693 | (2) |
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21.2 "Shmoo" of Performance Dropout Versus Frequency |
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695 | (3) |
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21.3 Product Qualification |
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698 | (4) |
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702 | (1) |
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702 | (1) |
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703 | (2) |
Epilogue |
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705 | (6) |
Index |
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711 | |