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E-raamat: Advanced Interconnects for ULSI Technology [Wiley Online]

Edited by (IMEC), Edited by (Fraunhofer Inst. for Non-Destr. Testing), Edited by (University of Texas at Austin)
  • Formaat: 608 pages
  • Ilmumisaeg: 02-Mar-2012
  • Kirjastus: John Wiley & Sons Inc
  • ISBN-10: 1119963672
  • ISBN-13: 9781119963677
Teised raamatud teemal:
  • Wiley Online
  • Hind: 240,80 €*
  • * hind, mis tagab piiramatu üheaegsete kasutajate arvuga ligipääsu piiramatuks ajaks
Advanced Interconnects for ULSI TechnologySuurem pilt
  • Formaat: 608 pages
  • Ilmumisaeg: 02-Mar-2012
  • Kirjastus: John Wiley & Sons Inc
  • ISBN-10: 1119963672
  • ISBN-13: 9781119963677
Teised raamatud teemal:
Wiley Online e-raamatudRohkem infot Wiley Online kohta
Raamatu kodulehekülg: https://onlinelibrary.wiley.com/doi/book/10.1002/9781119963677
"This book presents an in-depth overview of present status, novel developments and new materials and approaches for advanced interconnect technology"--



Finding new materials for copper/low-k interconnects is critical to the continuing development of computer chips. While copper/low-k interconnects have served well, allowing for the creation of Ultra Large Scale Integration (ULSI) devices which combine over a billion transistors onto a single chip, the increased resistance and RC-delay at the smaller scale has become a significant factor affecting chip performance.

Advanced Interconnects for ULSI Technology is dedicated to the materials and methods which might be suitable replacements. It covers a broad range of topics, from physical principles to design, fabrication, characterization, and application of new materials for nano-interconnects, and discusses:

  • Interconnect functions, characterisations, electrical properties and wiring requirements
  • Low-k materials: fundamentals, advances and mechanical properties
  • Conductive layers and barriers
  • Integration and reliability including mechanical reliability, electromigration and electrical breakdown
  • New approaches including 3D, optical, wireless interchip, and carbon-based interconnects

Intended for postgraduate students and researchers, in academia and industry, this book provides a critical overview of the enabling technology at the heart of the future development of computer chips.

About the Editors xiii
List of Contributors
xv
Preface xix
Abbreviations xxiii
Section I Low-k Materials
1(172)
1 Low-k Materials: Recent Advances
3(32)
Geraud Dubois
Willi Volksen
1.1 Introduction
3(2)
1.2 Integration Challenges
5(5)
1.2.1 Process-Induced Damage
6(3)
1.2.2 Mechanical Properties
9(1)
1.3 Processing Approaches to Existing Integration Issues
10(6)
1.3.1 Post-deposition Treatments
11(3)
1.3.2 Prevention or Repair of Plasma-Induced Processing Damage
14(1)
1.3.3 Multilayer Structures
15(1)
1.4 Material Advances to Overcome Current Limitations
16(6)
1.4.1 Silica Zeolites
16(3)
1.4.2 Hybrid Organic-Inorganic: Oxycarbosilanes
19(3)
1.5 Conclusion
22(13)
References
23(12)
2 Ultra-Low-k by CVD: Deposition and Curing
35(44)
Vincent Jousseaume
Aziz Zenasni
Olivier Gourhant
Laurent Favennec
Mikhail R. Baklanov
2.1 Introduction
35(2)
2.2 Porogen Approach by PECVD
37(5)
2.2.1 Precursors and Deposition Conditions
37(4)
2.2.2 Mystery Still Unsolved: From Porogens to Pores
41(1)
2.3 UV Curing
42(7)
2.3.1 General Overview of Curing
42(1)
2.3.2 UV Curing Mechanisms
43(6)
2.4 Impact of Curing on Structure and Physical Properties: Benefits of UV Curing
49(8)
2.4.1 Porosity
49(1)
2.4.2 Chemical Structure and Mechanical Properties
50(6)
2.4.3 Electrical Properties
56(1)
2.5 Limit/Issues with the Porogen Approach
57(5)
2.5.1 Porosity Creation Limit
58(1)
2.5.2 Porogen Residues
59(3)
2.6 Future of CVD Low-k
62(6)
2.6.1 New Matrix Precursor
62(2)
2.6.2 Other Deposition Strategies
64(2)
2.6.3 New Deposition Techniques
66(2)
2.7 Material Engineering: Adaptation to Integration Schemes
68(2)
2.8 Conclusion
70(9)
References
71(8)
3 Plasma Processing of Low-k Dielectrics
79(50)
Hualiang Shi
Denis Shamiryan
Jean-Francois de Marneffe
Huai Huang
Paul S. Ho
Mikhail R. Baklanov
3.1 Introduction
79(1)
3.2 Materials and Equipment
80(2)
3.3 Process Results Characterization
82(3)
3.4 Interaction of Low-k Dielectrics with Plasma
85(7)
3.4.1 Low-k Etch Chemistries
85(2)
3.4.2 Patterning Strategies and Masking Materials
87(1)
3.4.3 Etch Mechanisms
88(4)
3.5 Mechanisms of Plasma Damage
92(20)
3.5.1 Gap Structure Studies
93(2)
3.5.2 Effect of Radical Density
95(1)
3.5.3 Effect of Ion Energy
96(3)
3.5.4 Effect of Photon Energy and Intensity
99(4)
3.5.5 Plasma Damage by Oxidative Radicals
103(2)
3.5.6 Hydrogen-Based Plasma
105(3)
3.5.7 Minimization of Plasma Damage
108(4)
3.6 Dielectric Recovery
112(9)
3.6.1 CH4 Beam Treatment
112(1)
3.6.2 Dielectric Recovery by Silylation
113(6)
3.6.3 UV Radiation
119(2)
3.7 Conclusions
121(8)
References
122(7)
4 Wet Clean Applications in Porous Low-k Patterning Processes
129(44)
Quoc Toan Le
Guy Vereecke
Herbert Struyf
Els Kesters
Mikhail R. Baklanov
4.1 Introduction
129(1)
4.2 Silica and Porous Hybrid Dielectric Materials
130(4)
4.3 Impact of Plasma and Subsequent Wet Clean Processes on the Stability of Porous Low-k Dielectrics
134(7)
4.3.1 Stability in Pure Chemical Solutions
134(1)
4.3.2 Stability in Commercial Chemistries
135(3)
4.3.3 Hydrophobicity of Hybrid Low-k Materials
138(3)
4.4 Removal of Post-Etch Residues and Copper Surface Cleaning
141(5)
4.5 Plasma Modification and Removal of Post-Etch 193 nm Photoresist
146(27)
4.5.1 Modification of 193 nm Photoresist by Plasma Etch
146(7)
4.5.2 Wet Removal of 193 nm Photoresist
153(13)
Acknowledgments
166(1)
References
166(7)
Section II Conductive Layers and Barriers
173(62)
5 Copper Electroplating for On-Chip Metallization
175(18)
Valery M. Dubin
5.1 Introduction
175(1)
5.2 Copper Electroplating Techniques
176(1)
5.3 Copper Electroplating Superfill
177(5)
5.3.1 The Role of Accelerator
177(1)
5.3.2 The Role of Suppressor
178(2)
5.3.3 The Role of Leveler
180(2)
5.4 Alternative Cu Plating Methods
182(2)
5.4.1 Electroless Plating
182(1)
5.4.2 Direct Plating
182(2)
5.5 Electroplated Cu Properties
184(2)
5.5.1 Resistivity
184(1)
5.5.2 Impurities
184(1)
5.5.3 Electromigration
185(1)
5.6 Conclusions
186(7)
References
187(6)
6 Diffusion Barriers
193(42)
Michael Hecker
Rene Hubner
6.1 Introduction
193(5)
6.1.1 Cu Metallization, Barrier Requirements and Materials
193(2)
6.1.2 Barrier Deposition Techniques
195(1)
6.1.3 Characterization of Barrier Performance
196(2)
6.2 Metal-Based Barriers as Liners for Cu Seed Deposition
198(14)
6.2.1 Ta-Based Barriers
198(11)
6.2.2 W-Based Barriers
209(1)
6.2.3 Ti-Based Barriers
210(1)
6.2.4 Further Systems
211(1)
6.3 Advanced Barrier Approaches
212(9)
6.3.1 Barriers for Direct Cu Plating
212(2)
6.3.2 Metal Capping Layers
214(2)
6.3.3 Self-Forming Diffusion Barriers
216(2)
6.3.4 Self-Assembled Molecular Nanolayers and Polymer-Based Barriers
218(3)
6.4 Conclusions
221(14)
References
221(14)
Section III Integration and Reliability
235(200)
7 Process Integration of Interconnects
237(30)
Sridhar Balakrishnan
Ruth Brain
Larry Zhao
7.1 Introduction
237(1)
7.2 On-Die Interconnects in the Submicrometer Era
237(3)
7.3 On-Die Interconnects at Sub-100 nm Nodes
240(1)
7.4 Integration of Low-k Dielectrics in Sub-65 nm Nodes
241(7)
7.4.1 Degradation of Dielectric Constant during Integration
243(3)
7.4.2 Integration Issues in ELK Dielectrics Due to Degraded Mechanical Properties
246(2)
7.5 Patterning Integration at Sub-65 nm Nodes
248(4)
7.5.1 Patterning Challenges
249(3)
7.6 Integration of Conductors in Sub-65 nm Nodes
252(6)
7.6.1 Narrow Line Copper Resistivity
253(1)
7.6.2 Integrating Novel Barrier/Liner Materials and Deposition Techniques for Cu Interconnects
254(2)
7.6.3 Self-Forming Barriers and Their Integration
256(1)
7.6.4 Integration to Enable Reliable Copper Interconnects
257(1)
7.7 Novel Air-Gap Interconnects
258(9)
7.7.1 Unlanded Via Integration with Air-Gap Interconnects
258(1)
7.7.2 Air-Gap Formation Using Nonconformal Dielectric Deposition
259(1)
7.7.3 Air-Gap Formation Using a Sacrificial Material
260(1)
References
261(6)
8 Chemical Mechanical Planarization for Cu-Low-k Integration
267(24)
Gautam Banerjee
8.1 Introduction
267(1)
8.2 Back to Basics
268(1)
8.3 Mechanism of the CMP Process
268(3)
8.4 CMP Consumables
271(5)
8.4.1 Slurry
271(2)
8.4.2 Pad
273(1)
8.4.3 Pad Conditioner
274(2)
8.5 CMP Interactions
276(5)
8.6 Post-CMP Cleaning
281(6)
8.6.1 Other Defects
286(1)
8.6.2 Surface Finish
286(1)
8.6.3 E-Test
287(1)
8.7 Future Direction
287(4)
References
288(3)
9 Scaling and Microstructure Effects on Electromigration Reliability for Cu Interconnects
291(48)
Chao-Kun Hu
Rene Hubner
Lijuan Zhang
Meike Hauschildt
Paul S. Ho
9.1 Introduction
291(2)
9.2 Electromigration Fundamentals
293(6)
9.2.1 EM Mass Flow
293(1)
9.2.2 EM Lifetime and Scaling Rule
294(2)
9.2.3 Statistical Test Method
296(1)
9.2.4 Effect of Current Density on EM Lifetime
297(2)
9.3 Cu Microstructure
299(7)
9.3.1 X-ray Diffraction (XRD)
299(2)
9.3.2 Electron Backscatter Diffraction in the Scanning Electron Microscope
301(3)
9.3.3 Orientation Imaging Microscopy in the Transmission Electron Microscope
304(2)
9.4 Lifetime Enhancement
306(15)
9.4.1 Effect of a Ta Liner
306(2)
9.4.2 Upper-Level Dummy Vias
308(2)
9.4.3 Plasma Pre-clean and SiH4 Soak
310(1)
9.4.4 CVD and ECD Cu and the Effect of Nonmetallic Impurities
311(3)
9.4.5 Cu Alloys
314(5)
9.4.6 CoWP Cap Near-Bamboo and Polycrystalline Cu Lines
319(2)
9.5 Effect of Grain Size on EM Lifetime and Statistics
321(5)
9.6 Massive-Scale Statistical Study of EM
326(3)
9.7 Summary
329(10)
Acknowledgments
331(1)
References
331(8)
10 Mechanical Reliability of Low-k Dielectrics
339(30)
Kris Vanstreels
Han Li
Joost J. Vlassak
10.1 Introduction
339(1)
10.2 Mechanical Properties of Porous Low-k Materials
340(12)
10.2.1 Techniques to Measure Mechanical Properties of Thin Films
340(2)
10.2.2 Effect of Porosity on the Stiffness of Organosilicate Glass Films
342(2)
10.2.3 Hybrid Dielectrics Containing Organic/Inorganic Bridging Units
344(5)
10.2.4 Effect of UV Wavelength and Porogen Content on the Hardening Process of PECVD Low-k Dielectrics
349(3)
10.3 Fracture Properties of Porous Low-k Materials
352(9)
10.3.1 Adhesion Measurement Methods
352(2)
10.3.2 Fracture Toughness Measurement Techniques
354(1)
10.3.3 Effect of Porosity and Network Structure on the Fracture Toughness of Organosilicate Glass Films
355(2)
10.3.4 Effects of UV Cure on Fracture Properties of Carbon-Doped Oxides
357(2)
10.3.5 Water Diffusion and Fracture Properties of Organosilicate Glass Films
359(2)
10.4 Conclusion
361(8)
References
362(7)
11 Electrical Breakdown in Advanced Interconnect Dielectrics
369(66)
Ennis T. Ogawa
Oliver Aubel
11.1 Introduction
369(9)
11.1.1 Dual-Damascene Integration of Low-k Dielectrics
370(3)
11.1.2 Low-k Types and Integrating Low-k Dielectrics
373(5)
11.2 Reliability Testing
378(19)
11.2.1 Measurement of Dielectric Degradation
378(12)
11.2.2 Reliability Analysis
390(7)
11.3 Lifetime Extrapolation and Models
397(6)
11.4 Future Trends and Concerns
403(32)
Acknowledgments
405(1)
References
405(30)
Section IV New Approaches
435(130)
12 3D Interconnect Technology
437(54)
John U. Knickerbocker
Lay Wai Kong
Sven Niese
Alain Diebold
Ehrenfried Zschech
12.1 Introduction
437(1)
12.2 Dimensional Interconnected Circuits (3DICs) for System Applications
438(29)
John U. Knickerbocker
12.2.1 Introduction
438(3)
12.2.2 System Needs
441(3)
12.2.3 3D Interconnect Design and Architecture
444(2)
12.2.4 3D Fabrication and Interconnect Technology
446(18)
12.2.5 Trade-offs in Application Design and Product Applications
464(2)
12.2.6 Summary
466(1)
Acknowledgments
467(1)
12.3 Advanced Microscopy Techniques for 3D Interconnect Characterization
467(19)
Lay Wai Kong
Sven Niese
Alain Diebold
Ehrenfried Zschech
12.3.1 Scanning Acoustic Microscopy
467(6)
12.3.2 IR Microscopy
473(1)
12.3.3 Transmission X-ray Microscopy and Tomography
474(6)
12.3.4 Microstructure Analysis
480(6)
12.4 Summary
486(5)
References
486(5)
13 Carbon Nanotubes for Interconnects
491(12)
Mizuhisa Nihei
Motonobu Sato
Akio Kawabata
Shintaro Sato
Yuji Awano
13.1 Introduction
491(1)
13.2 Advantage of CNT Vias
492(1)
13.3 Fabrication Processes of CNT Vias
493(3)
13.4 Electrical Properties of CNT Vias
496(2)
13.5 Current Reliability of CNT Vias
498(3)
13.6 Conclusion
501(2)
Acknowledgments
501(1)
References
501(2)
14 Optical Interconnects
503(40)
Wim Bogaerts
14.1 Introduction
503(2)
14.2 Optical Links
505(14)
14.2.1 Waveguides
507(3)
14.2.2 Waveguide Filters and (De)multiplexers
510(3)
14.2.3 Transmitter: Light Source
513(1)
14.2.4 Transmitter: Modulators
514(3)
14.2.5 Receiver: Photodetector
517(1)
14.2.6 Power Consumption and Heat Dissipation
517(1)
14.2.7 Different Materials
518(1)
14.2.8 Conclusion
519(1)
14.3 The Case for Silicon Photonics
519(9)
14.3.1 Waveguides and WDM Components
519(4)
14.3.2 Modulators, Tuners and Switches
523(3)
14.3.3 Photodetectors
526(1)
14.3.4 Light Sources
526(1)
14.3.5 Conclusion
527(1)
14.4 Optical Networks on a Chip
528(4)
14.4.1 WDM Point-to-Point Links
529(1)
14.4.2 Bus Architecture
529(1)
14.4.3 (Reconfigurable) Networks
530(2)
14.5 Integration Strategies
532(6)
14.5.1 Front-End-of-Line Integration
533(2)
14.5.2 Backside Integration
535(1)
14.5.3 Back-End-of-Line Integration
535(1)
14.5.4 3D Integration
536(1)
14.5.5 Flip-Chip Integration
537(1)
14.5.6 Conclusion
537(1)
14.6 Conclusion
538(5)
References
538(5)
15 Wireless Interchip Interconnects
543(22)
Takamaro Kikkawa
15.1 Introduction
543(4)
15.2 Wireless Interconnect Technologies
547(14)
15.2.1 Figure of Merit for Wireless Interconnects
547(2)
15.2.2 Capacitively Coupled Wireless Interconnects
549(1)
15.2.3 Inductively Coupled Wireless Interconnects
550(3)
15.2.4 Antennas and Propagation
553(8)
15.3 Conclusion
561(4)
References
561(4)
Index 565
Mikhail R. Baklanov IMEC, Leuven, Belgium

Paul S. Ho Laboratory for Interconnect and Packaging, University of Texas at Austin, Austin, Texas, USA

Ehrenfried Zschech Fraunhofer Institute for Nondestructive Testing, Dresden, Germany
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