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Euro-Par 2022: Parallel Processing Workshops: Euro-Par 2022 International Workshops, Glasgow, UK, August 2226, 2022, Revised Selected Papers 1st ed. 2023 [Paperback / softback]

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  • Format: Paperback / softback, 306 pages, height x width: 235x155 mm, weight: 492 g, 84 Illustrations, color; 11 Illustrations, black and white; XI, 306 p. 95 illus., 84 illus. in color., 1 Paperback / softback
  • Series: Lecture Notes in Computer Science 13835
  • Pub. Date: 02-May-2023
  • Publisher: Springer International Publishing AG
  • ISBN-10: 3031312082
  • ISBN-13: 9783031312083
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  • Format: Paperback / softback, 306 pages, height x width: 235x155 mm, weight: 492 g, 84 Illustrations, color; 11 Illustrations, black and white; XI, 306 p. 95 illus., 84 illus. in color., 1 Paperback / softback
  • Series: Lecture Notes in Computer Science 13835
  • Pub. Date: 02-May-2023
  • Publisher: Springer International Publishing AG
  • ISBN-10: 3031312082
  • ISBN-13: 9783031312083
Other books in subject:
This book constitutes revised selected papers from the workshops held at the 28th International European Conference on Parallel and Distributed Computing, Euro-Par 2022, which took place in Glasgow, UK, in August 22–26, 2022

Out of a total of 35 submissions 24 papers have been accepted, 19 of these are included in this book.

They stem from the following workshops:

- Workshop on Algorithms, Models and Tools for Parallel Computing on Heterogeneous Platforms (HeteroPar)
- Workshop on Asynchronous Many-Task systems for Exascale (AMTE) 
- Workshop on Domain Specific Languages for High-Performance Computing (DSL-HPC)
- Workshop on Distributed and Heterogeneous Programming in C and C++ (DHPCC++)
- Workshop on Resiliency in High Performance Computing in Clouds, Grids, and Clusters (Resilience)

In addition, the proceedings also contains 6 extended abstracts from the PhD Symposium. 

AMTE Asynchronous Many-Task Systems for Exascale.- Quantifying
Overheads in Charm++ and HPX using Task Bench.- A Portable and Heterogeneous
LU Factorization on IRIS.- Halide Code Generation Framework in
Phylanx.- DSL-HPC  Domain Specific Languages for High-Performance
Computing.- Exploring the suitability of the Cerebras Wafer Scale Engine for
stencil-based computation codes.- Performance of the Vipera framework for
DSLs on micro-core architectures.- FFTc: An MLIR Dialect for Developing HPC
Fast Fourier Transform Libraries.- HeteroPar  Algorithms, Models and Tools
for Parallel Computing on Heterogeneous Platforms.- Programming Heterogeneous
Architectures Using Hierarchical Tasks.- A C++ library for memory layout and
performance portability of scientific applications.- Implementation and
Performance Evaluation of Memory System using Addressable Cache for HPC
applications on HBM2 equipped FPGAs.- Programming abstractions for preemptive
scheduling in FPGAs using partial reconfiguration.- Modeling Task Mapping for
Data-intensive Applications in Heterogeneous Systems.- Mapping Tree-shaped
Workflows on Memory-heterogeneous Architectures.- Hetero-Vis: A Framework for
Latency Optimized Deployment of Convolutional Neural Networks on
Heterogeneous Architectures.- Rapid development of OS support with PMCSched
for scheduling on asymmetric multicore systems.- HIPLZ: Enabling Performance
Portability for Exascale Systems.- StorAlloc: A Simulator for Job Scheduling
on Heterogeneous Storage Resources.- Performance and scalability analysis of
AI-accelerated CFD simulations across various computing
platforms.- Miscellaneous Workshops.- Performance Portability Assessment:
Non-negative Matrix Factorization as a case study.- Task-level Checkpointing
System for Task-based Parallel Workflows.- Euro-Par PhD Symposium.- A
Stochastic Programming Approach for an Enhanced Performance of a
Multi-committees Byzantine Fault Tolerant Algorithm.- Coupe: a modular,
multi-threaded mesh partitioning platform.- Preliminary study of resource
allocation in wireless communications.- Benchmarking Parallelism in
Unikernels.- Machine Learning methodologies to support HPC systems
operations: Anomaly detection.- FPGAs in supercomputers: performance through
dataflow programming and flexibility.