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Fundamentals of Digital and Computer Design with VHDL [Hardback]

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  • Format: Hardback, 736 pages, height x width x depth: 264x206x33 mm, weight: 1501 g, 664 Illustrations
  • Pub. Date: 16-Oct-2011
  • Publisher: McGraw Hill Higher Education
  • ISBN-10: 0073380695
  • ISBN-13: 9780073380698
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Fundamentals of Digital and Computer Design with VHDLLarger Image
  • Format: Hardback, 736 pages, height x width x depth: 264x206x33 mm, weight: 1501 g, 664 Illustrations
  • Pub. Date: 16-Oct-2011
  • Publisher: McGraw Hill Higher Education
  • ISBN-10: 0073380695
  • ISBN-13: 9780073380698
Other books in subject:
Permanent link: https://www.kriso.ee/db/9780073380698.html
Keywords:
This text is intended for an introductory digital design course for students at the freshman level; it also is intended for an introductory computer design course with assembly language programming for students at the sophomore level. This text uses a spiral teaching approach by introducing a design problem and then, in the same chapter or a later chapter, either (1) reemphasizing the same concepts when a different design is presented, or (2) working the same problem using a different technique. This is done to increase the likelihood of retention.
Preface xiii
About the Authors xx
Chapter 1 Boolean Algebra, Boolean Functions, VHDL, and Gates
1(36)
1.1 Introduction
1(1)
1.2 Basics of Boolean Algebra
1(9)
1.2.1 Venn Diagrams
2(1)
1.2.2 Black Boxes for Boolean Functions
3(1)
1.2.3 Basic Logic Symbols
4(3)
1.2.4 Boolean Algebra Postulates
7(1)
1.2.5 Boolean Algebra Theorems
8(1)
1.2.6 Proving Boolean Algebra Theorems
9(1)
1.3 Deriving Boolean Functions from Truth Tables
10(5)
1.3.1 Deriving Boolean Functions Using the 1s of the Functions
10(1)
1.3.2 Deriving Boolean Functions Using the 0s of the Functions
11(1)
1.3.3 Deriving Boolean Functions Using Minterms and Maxterms
12(3)
1.4 Writing VHDL Designs for Simple Gate Functions
15(15)
1.4.1 VHDL Design for a NOT Function
15(2)
1.4.2 VHDL Design for an AND Function
17(1)
1.4.3 VHDL Design for an OR Function
18(1)
1.4.4 VHDL Design for an XOR Function
19(2)
1.4.5 VHDL Design for a NAND Function
21(1)
1.4.6 VHDL Design for a NOR Function
22(2)
1.4.7 VHDL Design for an XNOR Function
24(2)
1.4.8 VHDL Design for a BUFFER Function
26(1)
1.4.9 VHDL Design for any Boolean Function Written in Canonical Form
27(3)
1.5 More about Logic Gates
30(7)
1.5.1 Equivalent Gate Symbols
30(1)
1.5.2 Functionally Complete Gates
31(1)
1.5.3 Equivalent Gate Circuits
32(1)
1.5.4 Compact Description Names for Gates
32(1)
1.5.5 International Logic Symbols for Gates
32(2)
Problems
34(3)
Chapter 2 Number Conversions, Codes, and Function Minimization
37(30)
2.1 Introduction
37(1)
2.2 Digital Circuits versus Analog Circuits
37(1)
2.2.1 Digitized Signal for the Human Heart
37(1)
2.2.2 Discrete Signals versus Continuous Signals
38(1)
2.3 Binary Number Conversions
38(7)
2.3.1 Decimal, Binary, Octal, and Hexadecimal Numbers
38(2)
2.3.2 Conversion Techniques
40(5)
2.4 Binary Codes
45(9)
2.4.1 Minimum Number of Bits for Keypads and Keyboards
45(1)
2.4.2 Commonly Used Codes: BCD, ASCII, and Others
45(3)
2.4.3 Modulo-2 Addition and Conversions between Binary and Reflective Gray Code
48(3)
2.4.4 7-Segment Code
51(1)
2.4.5 VHDL Design for a Letter Display System
52(2)
2.5 Karnaugh Map Reduction Method
54(13)
2.5.1 The Karnaugh Map Explorer
55(1)
2.5.2 Using a 2-Variable K-Map
56(2)
2.5.3 Using a 3-Variable K-Map
58(2)
2.5.4 Using a 4-Variable K-Map
60(1)
2.5.5 Don't-Care Outputs
61(2)
Problems
63(4)
Chapter 3 Introduction to Logic Circuit Analysis and Design
67(27)
3.1 Introduction
67(1)
3.2 Integrated Circuit Devices
67(2)
3.3 Analyzing and Designing Logic Circuits
69(5)
3.3.1 Analyzing and Designing Relay Logic Circuits
69(1)
3.3.2 Analyzing IC Logic Circuits
70(1)
3.3.3 Designing IC Logic Circuits
71(3)
3.4 Generating Detailed Schematics
74(2)
3.5 Designing Circuits in NAND/NAND and NOR/NOR Form
76(2)
3.6 Propagation Delay Time
78(1)
3.7 Decoders
79(6)
3.7.1 Designing Logic Circuits with Decoders and Single Gates
82(3)
3.8 Multiplexers
85(3)
3.8.1 Designing Logic Circuits with MUXs
87(1)
3.9 Hazards
88(6)
3.9.1 Function Hazards
88(1)
3.9.2 Logic Hazards
89(2)
Problems
91(3)
Chapter 4 Combinational Logic Circuit Design with VHDL
94(31)
4.1 Introduction
94(1)
4.2 VHDL
94(1)
4.3 The Library Part
95(1)
4.4 The Entity Declaration
96(1)
4.5 The Architecture Declaration
97(2)
4.5.1 Comments about a Dataflow Design Style
98(1)
4.5.2 Comments about a Behavioral Design Style
98(1)
4.5.3 Comments about a Structural Design Style
98(1)
4.6 Dataflow Design Style
99(3)
4.7 Behavioral Design Style
102(4)
4.8 Structural Design Style
106(6)
4.9 Implementing with Wires and Buses
112(4)
4.10 VHDL Examples
116(9)
4.10.1 Design with Scalar Inputs and Outputs
117(1)
4.10.2 Design with Vector Inputs and Outputs
118(2)
4.10.3 Common VHDL Constructs
120(1)
Problems
121(4)
Chapter 5 Bistable Memory Device Design with VHDL
125(31)
5.1 Introduction
125(1)
5.2 Analyzing an S-R NOR Latch
125(7)
5.2.1 Simple On/Off Light Switch
125(2)
5.2.2 Circuit Delay Model for an S-R NOR Latch
127(1)
5.2.3 Characteristic Table for an S-R NOR Latch
128(1)
5.2.4 Characteristic Equation for an S-R NOR Latch
129(1)
5.2.5 PS/NS Table for an S-R NOR Latch
129(1)
5.2.5 Timing Diagram for an S-R NOR Latch
130(2)
5.3 Analyzing an S-R NAND Latch
132(2)
5.3.1 Circuit Delay Model for an S-R NAND Latch
132(1)
5.3.2 Characteristic Table for an S-R NAND Latch
132(1)
5.3.3 Characteristic Equation for an S-R NAND Latch
133(1)
5.3.4 PS/NS Table for an S-R NAND Latch
133(1)
5.3.5 Timing Diagram for an S-R NAND Latch
133(1)
5.4 Designing a Simple Clock
134(3)
5.5 Designing a D Latch
137(6)
5.5.1 Gated S-R Latch Circuit Design
137(1)
5.5.2 D Latch Circuit Design with S-R Latches
138(1)
5.5.3 D Latch Circuit Design via the Characteristic Table for a D Latch
139(1)
5.5.4 Timing Diagram for a D Latch
140(1)
5.5.5 Creating a Clock via a D Latch
141(1)
5.5.6 Creating an 8-bit D Latch
142(1)
5.6 Designing D Flip-Flop Circuits
143(13)
5.6.1 Designing Master--Slave D Flip-Hop Circuits
143(3)
5.6.2 Designing D Flip-Flop Circuits with S-R NAND Latches
146(3)
5.6.3 Timing Diagram for Positive Edge-Triggered D Flip-Hop
149(1)
Problems
150(6)
Chapter 6 Simple Finite State Machine Design with VHDL
156(28)
6.1 Introduction
156(1)
6.2 Synchronous Circuits
156(1)
6.3 Creating D-type Flip-Flops in VHDL
157(1)
6.4 Designing Simple Synchronous Circuits
158(1)
6.5 Counter Design Using the Algorithmic Equation Method
159(8)
6.6 Nonconventional Counter Design Using the Algorithmic Equation Method
167(3)
6.7 Counter Design Using the Arithmetic Method
170(1)
6.8 Frequency Division (Slowing Down a Fast Clock Frequency)
171(3)
6.9 Counter Design Using the PS/NS Tabular Method
174(3)
6.10 Nonconventional Counter Design Using the PS/NS Tabular Method
177(7)
Problems
178(6)
Chapter 7 Computer Circuits
184(26)
7.1 Introduction
184(1)
7.2 Three-State Outputs and the Disconnected State
184(3)
7.3 Data Bus Sharing for a Microcomputer System
187(3)
7.4 More about XOR and XNOR Symbols and Functions
190(7)
7.4.1 Odd and Even Functions
191(1)
7.4.2 Single-Bit Error Detection System
192(2)
7.4.3 Comparators and Greater Than Circuits
194(3)
7.5 Adder Design
197(3)
7.5.1 Designing a Half Adder Module
197(1)
7.5.2 Designing a Full Adder Module
198(2)
7.6 Designing and Using Ripple-Carry Adders and Subtractors
200(3)
7.7 Propagation Delay Time for Ripple-Carry Adders
203(1)
7.8 Designing Carry Look-Ahead Adders
203(3)
7.9 Propagation Delay Time for Carry Look-Ahead Adders
206(4)
Problems
206(4)
Chapter 8 Circuit Implementation Techniques
210(17)
8.1 Introduction
210(1)
8.2 Programmable Logic Devices
210(7)
8.2.1 PROMs and LUTs
212(1)
8.2.2 PLAs
213(1)
8.2.3 PALs or GALs
213(1)
8.2.4 Designing with PROMs or LUTs
214(1)
8.2.5 Designing with PLAs
215(1)
8.2.6 Designing with PALs or GALs
216(1)
8.3 Positive Logic Convention and Direct Polarity Indication
217(4)
8.3.1 Signal Names
217(1)
8.3.2 Analyzing Equivalent Circuits for the PLC and the DPI Systems
218(3)
8.4 More about MUXs and DMUXs
221(6)
8.4.1 Designing MUX Trees
223(1)
8.4.2 Designing DMUX Trees
223(1)
Problems
224(3)
Chapter 9 Complex Finite State Machine Design with VHDL
227(52)
9.1 Introduction
227(1)
9.2 Designing with the Two-Process PS/NS Method
228(3)
9.3 Explanation of CPLDs and FPGAs and State Machine Encoding Styles
231(3)
9.4 Summary of Finite State Machine Models
234(1)
9.5 Designing Compact Encoded State Machines with Moore Outputs
235(2)
9.6 Designing One-Hot Encoded State Machines with Moore Outputs
237(4)
9.7 Designing Compact Encoded State Machines with Moore and Mealy Outputs
241(2)
9.8 Designing One-Hot Encoded State Machines with Moore and Mealy Outputs
243(2)
9.9 Using the Algorithmic Equation Method to Design Complex State Machines
245(6)
9.10 Improving the Reliability of Complex State Machine Designs
251(4)
9.11 Additional State Machine Design Methods
255(24)
9.11.1 Two-Assignment PS/NS Method
256(3)
9.11.2 Hybrid PS/NS Method
259(3)
Problems
262(17)
Chapter 10 Basic Computer Architectures
279(13)
10.1 Introduction
279(1)
10.2 Generic Data-Processing System or Computer
279(1)
10.3 Harvard-Type Computer and RISC Architecture
280(2)
10.4 Princeton (von Neumann)-Type Computer and CISC Architecture
282(1)
10.5 Overview of VBC1 (Very Basic Computer 1)
283(1)
10.6 Design Philosophy of VBC1
283(3)
10.7 Programmer's Register Model for VBC1
286(1)
10.8 Instruction Set Architecture for VBC1
287(2)
10.9 Format for Writing Assembly Language Programs
289(3)
Problems
290(2)
Chapter 11 Assembly Language Programming for VBC1
292(24)
11.1 Introduction
292(1)
11.2 Instruction Set for VBC1
292(1)
11.3 The IN Instruction
293(3)
11.4 The OUT Instruction
296(2)
11.5 The MOV Instruction
298(2)
11.6 The LOADI Instruction
300(1)
11.7 The ADDI Instruction
301(2)
11.8 The ADD Instruction
303(1)
11.9 The SR0 Instruction
304(2)
11.10 The JNZ Instruction
306(2)
11.11 Programming Examples and Techniques for VBC1
308(8)
11.11.1 Unconditional Jump
308(1)
11.11.2 Labels
308(1)
11.11.3 Loop Counter
309(1)
11.11.4 Program Runs Amuck
310(1)
11.11.5 Subtraction Instruction
310(2)
11.11.6 Multiply Instruction
312(1)
11.11.7 Divide Instruction
312(1)
Problems
312(4)
Chapter 12 Designing Input/Output Circuits
316(19)
12.1 Introduction
316(1)
12.2 Designing Steering Circuits
316(2)
12.3 Designing Bus Steering Circuits
318(1)
12.4 Designing Loadable Register Circuits
319(2)
12.5 Designing Input Circuits
321(3)
12.5.1 Designing an Input Circuit Driven by Four Slide Switches
323(1)
12.6 Designing Output Circuits
324(5)
12.6.1 Designing an Output Circuit to Drive Four LEDs
325(1)
12.6.2 Designing an Output Circuit to Drive a 7-Segment Display
326(2)
12.6.3 A Closer Look at the Circuitry for Display 0
328(1)
12.7 Combining Input and Output Circuits to Form a Simple I/O System
329(3)
12.8 Alternate VHDL Design Styles
332(3)
Problems
333(2)
Chapter 13 Designing Instruction Memory, Loading Program Counter, and Debounced Circuit
335(22)
13.1 Introduction
335(1)
13.2 Designing an Instruction Memory
335(7)
13.2.1 Coding Alterations for Instruction Memory
337(2)
13.2.2 Initializing Instruction Memory for VBC1 at Startup
339(3)
13.3 Designing a Loading Program Counter
342(3)
13.4 Designing a Debounced One-Pulse Circuit
345(3)
13.5 Design Verification for a Debounced One-Pulse Circuit
348(9)
Problems
355(2)
Chapter 14 Designing Multiplexed Display Systems
357(22)
14.1 Introduction
357(1)
14.2 Multiplexed Display System for Four 7-Segment LED Displays
357(3)
14.3 Designing a Multiplexed Display System Using VHDL
360(4)
14.3.1 Designing Module 1: A 4-to-1 MUX Array
360(1)
14.3.2 Designing Module 2: A HEX Display Decoder
361(1)
14.3.3 Designing Module 3: A 2-bit Counter and a Frequency Divider
362(2)
14.3.4 Designing Module 4: A 2-to-4 Decoder
364(1)
14.4 Complete Design of a Multiplexed Display System Using a Flat Design Approach
364(3)
14.5 Complete Design of a Multiplexed Display System Using a Hierarchal Design Approach
367(5)
14.6 Designing a Word Display System Using a Flat Design Approach
372(7)
Problems
377(2)
Chapter 15 Designing Instruction Decoders
379(19)
15.1 Introduction
379(1)
15.2 Purpose of the Instruction Decoder
379(1)
15.3 Instruction Decoder Truth Tables for the IN, OUT, and MOV Instructions
380(2)
15.4 Designing an Instruction Decoder for the IN Instruction
382(1)
15.5 Designing an Instruction Decoder for the OUT and MOV Instructions
383(1)
15.6 Instruction Decoder Truth Table for the LOADI Instruction
384(1)
15.7 Instruction Decoder Truth Table for the ADDI Instruction
385(1)
15.8 Instruction Decoder Truth Table for the ADD Instruction
386(1)
15.9 Instruction Decoder Truth Table for the SR0 Instruction
387(1)
15.10 Designing an Instruction Decoder for the SR0 Instruction
388(1)
15.11 Instruction Decoder Truth Table for the JNZ Instruction
389(2)
15.12 Designing an Instruction Decoder for the JNZ Instruction
391(2)
15.13 Designing an Instruction Decoder for VBC1
393(5)
Problems
393(5)
Chapter 16 Designing Arithmetic Logic Units
398(18)
16.1 Introduction
398(1)
16.2 Utilization of the Arithmetic Logic Unit
398(1)
16.3 Designing the LOADI Instruction Part of the ALU
399(1)
16.4 Designing the ADDI Instruction Part of the ALU
400(1)
16.5 Designing the ADD Instruction Part of the ALU
401(1)
16.6 Designing the SR0 Instruction Part of the ALU
401(1)
16.7 Designing an ALU for VBC1
402(1)
16.8 Additional Circuit Designs with VHDL
403(13)
16.8.1 Designing Additional ALU Circuits
403(3)
16.8.2 Designing Shifter Circuits
406(3)
16.8.3 Designing Barrel Shifter Circuits
409(3)
16.8.4 Designing Shift Register Circuits
412(2)
Problems
414(2)
Chapter 17 Completing the Design for VBC1
416(9)
17.1 Introduction
416(1)
17.2 Designing a Running Program Counter
416(3)
17.3 Combining a Loading and a Running Program Counter
419(2)
17.4 Designing a Run Frequency Circuit and a Speed Circuit
421(2)
17.5 Designing Circuits to Provide a Loader for Instruction Memory for VBC1
423(2)
Problems
424(1)
Chapter 18 Assembly Language Programming for VBC1-E
425(33)
18.1 Introduction
425(1)
18.2 Instruction Summary
425(2)
18.3 Input, Output, and Interrupt Instructions
427(5)
18.4 Data Memory Instructions
432(2)
18.5 Arithmetic and Logic Instructions
434(3)
18.6 Shift and Rotate Instructions
437(2)
18.7 Jump, Jump Relative, and Halt Instructions
439(4)
18.8 More about Interrupts and Assembler Directives
443(5)
18.9 Complete Instruction Set Summary for VBC1-E
448(10)
Problems
449(9)
Chapter 19 Designing Input/Output Circuits for VBC1-E
458(13)
19.1 Introduction
458(1)
19.2 Designing the Input Circuit for VBC1-E
458(2)
19.3 Instruction Decoder Truth Table for the Modified IN Instruction for VBC1-E
460(2)
19.4 Designing the Output Circuit for VBC1-E
462(2)
19.5 Instruction Decoder Truth Table for the Modified OUT Instruction for VBC1-E
464(2)
19.6 Designing an Instruction Decoder for the Modified IN and OUT Instructions for VBC1-E
466(1)
19.7 Designing an Instruction Decoder for the LOADI, ADDI, and JNZ Instructions for VBC1-E
467(4)
Problems
468(3)
Chapter 20 Designing the Data Memory Circuit for VBC1-E
471(11)
20.1 Introduction
471(1)
20.2 Designing the Data Memory for VBC1-E
471(4)
20.3 Designing Circuits to Select the Registers and Data for VBC1-E
475(1)
20.4 Instruction Decoder Truth Tables for the STORE and FETCH Instructions for VBC1-E
475(3)
20.5 Designing an Instruction Decoder for the STORE and FETCH Instructions for VBC1-E
478(1)
20.6 Designing an Instruction Decoder for the MOV Instruction for VBC1-E
479(3)
Problems
480(2)
Chapter 21 Designing the Arithmetic, Logic, Shift, Rotate, and Unconditional Jump Circuits for VBC1-E
482(11)
21.1 Introduction
482(1)
21.2 Designing the Arithmetic and Logic Instructions Part of the ALU for VBC1-E
482(2)
21.3 Designing the Instruction Decoder for the Arithmetic and Logic Instructions for VBC1-E
484(1)
21.4 Designing the Shift and Rotate Instructions Part of the ALU for VBC1-E
485(1)
21.5 Designing the Instruction Decoder for the Shift and Rotate Instructions for VBC1-E
486(2)
21.6 Designing the JMP and JMPR Circuits for VBC1-E
488(1)
21.7 Designing the Instruction Decoder for the JMP and JMPR Instructions for VBC1-E
489(4)
Problems
490(3)
Chapter 22 Designing a Circuit to Prevent Program Execution During Manual Loading for VBC1-E
493(3)
22.1 Introduction
493(1)
22.2 Designing a Circuit to Modify Manual Loading for VBC1-E
493(2)
22.3 Modifying the Instruction Decoder for Manual Loading for VBC1-E
495(1)
Problems
495(1)
Chapter 23 Designing Extended Instruction Memory for VBC1-E
496(8)
23.1 Introduction
496(1)
23.2 Modifying the Instruction Memory to Add Extended Instruction Memory for VBC1-E
496(4)
23.3 Modifying the Running Program Counter Circuit for VBC1-E
500(1)
23.4 Modifying the Proper Address Circuit for VBC1-E
501(1)
23.5 Modifying the Loading Program Counter Circuit for VBC1-E
501(1)
23.6 Modifying the JMPR Circuit for VBC1-E
502(2)
Problems
502(2)
Chapter 24 Designing the Software Interrupt Circuits for VBC1-E
504(12)
24.1 Introduction
504(1)
24.2 Designing the Modified Circuit for the Running Program Counter and the Select Circuit for VBC1-E
504(5)
24.3 Designing the Circuit to Store PCPLUS1 for VBC1-E
509(1)
24.4 Instruction Decoder Truth Tables for the INT and IRET Instructions for VBC1-E
510(1)
24.5 Designing the Instruction Decoder for the INT and IRET Instructions for VBC1-E
511(5)
Problems
513(3)
Chapter 25 Completing the Design for VBC1-E
516(12)
25.1 Introduction
516(1)
25.2 Designing a Debounced One-Pulse Trigger Interrupt Circuit and Modifying the RPC Circuit for VBC1-E
516(5)
25.3 Designing Circuits for Displaying the Signal RETA for VBC1-E
521(4)
25.4 Designing Circuits to Provide a Loader for Instruction Memory for VBC1-E
525(3)
Problems
525(3)
Appendices
A Laboratory Experiments
528(147)
Experiment 1A Designing and Simulating Gates
528(6)
Experiment 1B Completing the Design Cycle
534(5)
Experiment 2 Designing and Testing a Keypad Encoder System
539(3)
Experiment 3 Designing and Testing a Check Gates System
542(4)
Experiment 4 Designing and Testing a Custom Decimal Display Decoder System
546(3)
Experiment 5A Designing and Testing a D Latch and a D Flip-Flop with a CLR Input
549(4)
Experiment 5B Designing and Testing an 8-bit Register and a D Flip-Flop with a PRE Input
553(5)
Experiment 6A Designing and Testing a Simple Counter System---A One-Hot Up Counter with 8 Bits
558(4)
Experiment 6B Designing and Testing a Simple Counter System---A Gray Code Counter with 2 Bits
562(3)
Experiment 6C Designing and Testing a Simple Nonconventional Counter System---A Robot Eye Circuit
565(4)
Experiment 6D Designing and Testing a Simple Nonconventional Counter---A Smiley Face Circuit
569(3)
Experiment 7A Designing and Testing a Simple Error Detection System Using a Flat Design Approach
572(5)
Experiment 7B Designing and Testing a 4-bit Simple Adder-Subtractor System Using a Hierarchal Design Approach
577(3)
Experiment 8 Designing and Testing a LUT Design System Using a Flat Design Approach
580(4)
Experiment 9A Designing and Testing a One-Hot Up/Down Counter System Using a Flat Design Approach
584(5)
Experiment 9B Designing and Testing a 10-State Counter System Using a Hierarchal Design Approach
589(4)
Experiment 10 Working with EASY1 (Editor/Assembler/Simulator) for VBC1
593(5)
Experiment 11 Writing and Simulating Programs for VBC1 with EASY1
598(2)
Experiment 12 Designing and Testing VBC1 (Data Path Unit)
600(5)
Experiment 13 Designing and Testing VBC1 (Instruction Memory Unit)
605(4)
Experiment 14 Designing and Testing VBC1 (Monitor System)
609(4)
Experiment 15 Designing and Testing VBC1 (Instruction Decoder)
613(4)
Experiment 16 Designing and Testing VBC1 (Arithmetic Logic Unit)
617(4)
Experiment 17 Designing and Testing VBC1 (Final Hardware Design for VBC1)
621(5)
Experiment 17L Designing a Loader for Instruction Memory for VBC1
626(6)
Experiment 18 Writing Assembly Language Programs and Running Them on VBC1
632(3)
Experiment 19 Designing and Testing VBC1-E (IN, OUT, and Unchanged Instructions)
635(5)
Experiment 20 Designing and Testing VBC1-E (MOV and Data Memory Instructions)
640(5)
Experiment 21 Designing and Testing VBC1-E (Almost All Instructions)
645(6)
Experiment 22 Designing and Testing VBC1-E (Modified Manual Loading)
651(3)
Experiment 23 Designing and Testing VBC1-E (Add Extended Instruction Memory)
654(4)
Experiment 24 Designing and Testing VBC1-E (INT and IRET Instructions)
658(5)
Experiment 25 Designing and Testing VBC1-E (Final Hardware Design for VBC1-E)
663(5)
Experiment 25L Designing a Loader for Instruction Memory for VBC1-E
668(7)
B Obtaining Simulations via the VHDL Test Bench Program
675(8)
B.1 Introduction
675(1)
B.2 Example 1---Combinational Logic Design (project: AND_3)
675(4)
B.3 Example 2---Synchronous Sequential Logic Design (project: DFF)
679(4)
C FPGA Pin Connections---Handy Reference
683(4)
C.1 BASYS 2 Board
683(1)
C.2 NEXYS 2 Board
684(1)
C.3 Memory Loader I/O Pin Connections for the FPGAs on the BASYS 2 and NEXYS 2 Board
685(1)
C.4 FX2 MIB (Module Interface Board)---Add-on Board for NEXYS 2
686(1)
D EASY1 Tutorial
687(14)
D.1 Introduction
687(1)
D.2 EASY1 Screen or GUI
687(1)
D.3 EASY1 Layout
687(2)
D.4 How to Use EASY1
689(1)
D.5 Example 1---A Simple Input/Output Program
689(6)
D.6 Example 2---Input/Output Program Modified to Run Continuously
695(1)
D.7 Example 3---A Simple State Machine Program
696(1)
D.8 Example 4---A Complex State Machine Program
696(2)
D.9 Example 5---Generating Time Delays
698(1)
D.10 Using EASY1 to Generate Machine Code for VBC1
699(2)
E Three Methods for Loading Instructions into Memory
701(4)
E.1 Loading Memory Manually
701(1)
E.2 Initializing Memory at Startup
702(1)
E.3 Loading Memory via the Memory Loader Program
703(2)
Index 705