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E-raamat: Handbook of Algorithms for Physical Design Automation [Taylor & Francis e-raamat]

Edited by , Edited by (University of Minnesota, Minneapolis, USA), Edited by
  • Formaat: 1044 pages
  • Ilmumisaeg: 11-Sep-2019
  • Kirjastus: CRC Press
  • ISBN-13: 9780429118173
  • Taylor & Francis e-raamat
  • Hind: 276,97 €*
  • * hind, mis tagab piiramatu üheaegsete kasutajate arvuga ligipääsu piiramatuks ajaks
  • Tavahind: 395,67 €
  • Säästad 30%
  • Formaat: 1044 pages
  • Ilmumisaeg: 11-Sep-2019
  • Kirjastus: CRC Press
  • ISBN-13: 9780429118173
The physical design flow of any project depends upon the size of the design, the technology, the number of designers, the clock frequency, and the time to do the design. As technology advances and design-styles change, physical design flows are constantly reinvented as traditional phases are removed and new ones are added to accommodate changes in technology.





Handbook of Algorithms for Physical Design Automation provides a detailed overview of VLSI physical design automation, emphasizing state-of-the-art techniques, trends and improvements that have emerged during the previous decade. After a brief introduction to the modern physical design problem, basic algorithmic techniques, and partitioning, the book discusses significant advances in floorplanning representations and describes recent formulations of the floorplanning problem. The text also addresses issues of placement, net layout and optimization, routing multiple signal nets, manufacturability, physical synthesis, special nets, and designing for specialized technologies. It includes a personal perspective from Ralph Otten as he looks back on the major technical milestones in the history of physical design automation.





Although several books on this topic are currently available, most are either too broad or out of date. Alternatively, proceedings and journal articles are valuable resources for researchers in this area, but the material is widely dispersed in the literature. This handbook pulls together a broad variety of perspectives on the most challenging problems in the field, and focuses on emerging problems and research results.
Editors xiii
Contributors xv
PART I Introduction
Chapter 1 Introduction to Physical Design
3(6)
Charles J. Alpert
Dinesh P. Mehta
Sachin S. Sapatnekar
Chapter 2 Layout Synthesis: A Retrospective
9(20)
Ralph H.J.M. Otten
Chapter 3 Metrics Used in Physical Design
29(26)
Frank Liu
Sachin S. Sapatnekar
PART II Foundations
Chapter 4 Basic Data Structures
55(18)
Dinesh P. Mehta
Hai Zhou
Chapter 5 Basic Algorithmic Techniques
73(16)
Vishal Khandelwal
Ankur Srivastava
Chapter 6 Optimization Techniques for Circuit Design Applications
89(20)
Zhi-Quan Luo
Chapter 7 Partitioning and Clustering
109(30)
Dorothy Kucar
PART III Floorplanning
Chapter 8 Floorplanning: Early Research
139(22)
Susmita Sur-Kolay
Chapter 9 Slicing Floorplans
161(24)
Ting-Chi Wang
Martin D.F. Wong
Chapter 10 Floorplan Representations
185(18)
Evangeline F.Y. Young
Chapter 11 Packing Floorplan Representations
203(36)
Tung-Chieh Chen
Yao-Wen Chang
Chapter 12 Recent Advances in Floorplanning
239(18)
Dinesh P. Mehta
Yan Feng
Chapter 13 Industrial Floorplanning and Prototyping
257(20)
Louis K. Scheffer
PART IV Placement
Chapter 14 Placement: Introduction/Problem Formulation
277(12)
Gi-Joon Nam
Paul G. Villarrubia
Chapter 15 Partitioning-Based Methods
289(22)
Jarrod A. Roy
Igor L. Markov
Chapter 16 Placement Using Simulated Annealing
311(16)
William Swartz
Chapter 17 Analytical Methods in Placement
327(20)
Ulrich Brenner
Jens Vygen
Chapter 18 Force-Directed and Other Continuous Placement Methods
347(30)
Andrew Kennings
Kristofer Vorwerk
Chapter 19 Enhancing Placement with Multilevel Techniques
377(22)
Jason Cong
Joseph R. Shinnerl
Chapter 20 Legalization and Detailed Placement
399(24)
Ameya R. Agnihotri
Patrick H. Madden
Chapter 21 Timing-Driven Placement
423(24)
David Z. Pan
Bill Halpin
Haoxing Ren
Chapter 22 Congestion-Driven Physical Design
447(22)
Saurabh N. Adya
Xiaojian Yang
PART V Net Layout and Optimization
Chapter 23 Global Routing Formulation and Maze Routing
469(18)
Muhammet Mustafa Ozdal
Martin D.F. Wong
Chapter 24 Minimum Steiner Tree Construction
487(22)
Gabriel Robins
Alexander Zelikovsky
Chapter 25 Timing-Driven Interconnect Synthesis
509(26)
Jiang Hu
Gabriel Robins
Cliff C. N. Sze
Chapter 26 Buffer Insertion Basics
535(22)
Jiang Hu
Zhuo Li
Shiyan Hu
Chapter 27 Generalized Buffer Insertion
557(12)
Milos Hrkic
John Lillis
Chapter 28 Buffering in the Layout Environment
569(16)
Jiang Hu
Cliff C. N. Sze
Chapter 29 Wire Sizing
585(14)
Sanghamitra Roy
Charlie Chung-Ping Chen
PART VI Routing Multiple Signal Nets
Chapter 30 Estimation of Routing Congestion
599(16)
Rupesh S. Shelar
Prashant Saxena
Chapter 31 Rip-Up and Reroute
615(12)
Jeffrey S. Salowe
Chapter 32 Optimization Techniques in Routing
627(18)
Christoph Albrecht
Chapter 33 Global Interconnect Planning
645(28)
Cheng-Kok Koh
Evangeline F.Y. Young
Yao-Wen Chang
Chapter 34 Coupling Noise
673(22)
Rajendran Panda
Vladimir Zolotov
Murat Becer
PART VII Manufacturability and Detailed Routing
Chapter 35 Modeling and Computational Lithography
695(42)
Franklin M. Schellenberg
Chapter 36 CMP Fill Synthesis: A Survey of Recent Studies
737(34)
Andrew B. Kahng
Kambiz Samadi
Chapter 37 Yield Analysis and Optimization
771(20)
Puneet Gupta
Evanthia Papadopoulou
Chapter 38 Manufacturability-Aware Routing
791(22)
Minsik Cho
Joydeep Mitra
David Z. Pan
PART VIII Physical Synthesis
Chapter 39 Placement-Driven Synthesis Design Closure Tool
813(22)
Charles J. Alpert
Nathaniel Hieter
Arjen Mets
Ruchir Puri
Lakshmi Reddy
Haoxing Ren
Louise Trevillyan
Chapter 40 X Architecture Place and Route: Physical Design for the X Interconnect Architecture
835(30)
Steve Teig
Asmus Hetzel
Joseph Ganley
Jon Frankle
Aki Fujimura
PART IX Designing Large Global Nets
Chapter 41 Inductance Effects in Global Nets
865(16)
Yehea I. Ismail
Chapter 42 Clock Network Design: Basics
881(16)
Chris Chu
Min Pan
Chapter 43 Practical Issues in Clock Network Design
897(16)
Chris Chu
Min Pan
Chapter 44 Power Grid Design
913(28)
Haihua Su
Sani Nassif
PART X Physical Design for Specialized Technologies
Chapter 45 Field-Programmable Gate Array Architectures
941(16)
Steven J.E. Wilton
Nathalie Chan King Choy
Scott Y.L. Chin
Kara K.W. Poon
Chapter 46 FPGA Technology Mapping, Placement, and Routing
957(28)
Kia Bazargan
Chapter 47 Physical Design for Three-Dimensional Circuits
985(18)
Kia Bazargan
Sachin S. Sapatnekar
Index 1003
Charles J. Alpert, Dinesh p. Mehta, Sachin S. Sapatnekar