Editors |
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xiii | |
Contributors |
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xv | |
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Chapter 1 Introduction to Physical Design |
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3 | (6) |
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Chapter 2 Layout Synthesis: A Retrospective |
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9 | (20) |
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Chapter 3 Metrics Used in Physical Design |
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29 | (26) |
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Chapter 4 Basic Data Structures |
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55 | (18) |
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Chapter 5 Basic Algorithmic Techniques |
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73 | (16) |
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Chapter 6 Optimization Techniques for Circuit Design Applications |
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89 | (20) |
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Chapter 7 Partitioning and Clustering |
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109 | (30) |
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Chapter 8 Floorplanning: Early Research |
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139 | (22) |
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Chapter 9 Slicing Floorplans |
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161 | (24) |
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Chapter 10 Floorplan Representations |
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185 | (18) |
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Chapter 11 Packing Floorplan Representations |
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203 | (36) |
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Chapter 12 Recent Advances in Floorplanning |
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239 | (18) |
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Chapter 13 Industrial Floorplanning and Prototyping |
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257 | (20) |
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Chapter 14 Placement: Introduction/Problem Formulation |
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277 | (12) |
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Chapter 15 Partitioning-Based Methods |
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289 | (22) |
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Chapter 16 Placement Using Simulated Annealing |
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311 | (16) |
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Chapter 17 Analytical Methods in Placement |
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327 | (20) |
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Chapter 18 Force-Directed and Other Continuous Placement Methods |
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347 | (30) |
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Chapter 19 Enhancing Placement with Multilevel Techniques |
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377 | (22) |
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Chapter 20 Legalization and Detailed Placement |
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399 | (24) |
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Chapter 21 Timing-Driven Placement |
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423 | (24) |
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Chapter 22 Congestion-Driven Physical Design |
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447 | (22) |
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PART V Net Layout and Optimization |
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Chapter 23 Global Routing Formulation and Maze Routing |
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469 | (18) |
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Chapter 24 Minimum Steiner Tree Construction |
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487 | (22) |
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Chapter 25 Timing-Driven Interconnect Synthesis |
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509 | (26) |
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Chapter 26 Buffer Insertion Basics |
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535 | (22) |
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Chapter 27 Generalized Buffer Insertion |
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557 | (12) |
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Chapter 28 Buffering in the Layout Environment |
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569 | (16) |
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585 | (14) |
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PART VI Routing Multiple Signal Nets |
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Chapter 30 Estimation of Routing Congestion |
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599 | (16) |
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Chapter 31 Rip-Up and Reroute |
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615 | (12) |
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Chapter 32 Optimization Techniques in Routing |
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627 | (18) |
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Chapter 33 Global Interconnect Planning |
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645 | (28) |
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Chapter 34 Coupling Noise |
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673 | (22) |
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PART VII Manufacturability and Detailed Routing |
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Chapter 35 Modeling and Computational Lithography |
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695 | (42) |
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Chapter 36 CMP Fill Synthesis: A Survey of Recent Studies |
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737 | (34) |
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Chapter 37 Yield Analysis and Optimization |
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771 | (20) |
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Chapter 38 Manufacturability-Aware Routing |
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791 | (22) |
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PART VIII Physical Synthesis |
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Chapter 39 Placement-Driven Synthesis Design Closure Tool |
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813 | (22) |
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Chapter 40 X Architecture Place and Route: Physical Design for the X Interconnect Architecture |
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835 | (30) |
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PART IX Designing Large Global Nets |
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Chapter 41 Inductance Effects in Global Nets |
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865 | (16) |
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Chapter 42 Clock Network Design: Basics |
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881 | (16) |
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Chapter 43 Practical Issues in Clock Network Design |
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897 | (16) |
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Chapter 44 Power Grid Design |
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913 | (28) |
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PART X Physical Design for Specialized Technologies |
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Chapter 45 Field-Programmable Gate Array Architectures |
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941 | (16) |
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Chapter 46 FPGA Technology Mapping, Placement, and Routing |
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957 | (28) |
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Chapter 47 Physical Design for Three-Dimensional Circuits |
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985 | (18) |
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Index |
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1003 | |