Preface |
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xv | |
Acknowledgments |
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xxiii | |
The Author |
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xxv | |
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1 Number Systems, Operations, and Codes |
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1 | (34) |
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2 | (1) |
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1.2 Digital versus Analog Quantities |
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3 | (1) |
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1.3 Digital Numbering System (Base 10) |
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4 | (1) |
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1.4 Binary Numbering System (Base 2) |
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5 | (2) |
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1.5 Octal Numbering System (Base 8) |
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7 | (1) |
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1.6 Hexadecimal Numbering System (Base 16) |
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8 | (2) |
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1.7 Binary-Coded-Decimal System |
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10 | (1) |
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11 | (1) |
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12 | (5) |
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13 | (1) |
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14 | (1) |
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1.9.3 Binary Multiplication |
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15 | (1) |
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16 | (1) |
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17 | (1) |
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1.11 Hexadecimal Conversions |
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18 | (2) |
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1.12 Hexadecimal Operations |
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20 | (3) |
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1.12.1 Hexadecimal Addition |
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20 | (1) |
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1.12.2 Hexadecimal Subtraction |
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21 | (1) |
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1.1.3 1's and 2's Complements of Binary Numbers |
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21 | (1) |
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1.13.1 Finding the 1's Complement |
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21 | (1) |
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1.13.2 Finding the 2's Complement |
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21 | (2) |
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23 | (2) |
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24 | (1) |
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1.14.2 Sign-Magnitude Form |
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24 | (1) |
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1.14.3 1's Complement Form |
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24 | (1) |
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1.14.4 2's Complement Form |
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25 | (1) |
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25 | (3) |
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28 | (7) |
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29 | (1) |
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Answers to Section Review Quiz |
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30 | (1) |
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30 | (1) |
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31 | (1) |
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32 | (3) |
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2 Semiconductors and Digital Logic |
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35 | (54) |
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36 | (1) |
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36 | (1) |
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37 | (5) |
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2.3.1 Inverter Truth Table |
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38 | (1) |
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39 | (1) |
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2.3.3 Operation of an Inverter |
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40 | (1) |
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40 | (1) |
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2.3.5 Logic Expressions for an Inverter |
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41 | (1) |
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42 | (7) |
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42 | (1) |
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2.4.2 Operation of an And Gate |
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43 | (1) |
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2.4.3 And Gate Truth Table |
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44 | (2) |
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46 | (1) |
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2.4.5 Logic Expressions for an And Gate |
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47 | (2) |
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49 | (8) |
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49 | (1) |
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2.5.2 Operation of an OR Gate |
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49 | (2) |
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2.5.3 OR Gate Truth Table |
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51 | (1) |
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52 | (3) |
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2.5.5 Logic Expressions for an OR Gate |
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55 | (2) |
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57 | (5) |
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57 | (1) |
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2.6.2 Operation of a Nand Gate |
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57 | (1) |
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58 | (2) |
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2.6.4 Negative-OR Equivalent Operation of a Nand Gate |
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60 | (1) |
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2.6.5 Logic Expressions for a Nand Gate |
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61 | (1) |
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62 | (5) |
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62 | (1) |
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2.7.2 Operation of a NOR Gate |
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62 | (1) |
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63 | (1) |
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2.7.4 Negative-And Equivalent Operation of the NOR Gate |
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64 | (1) |
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2.7.5 Logic Expressions for a NOR Gate |
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65 | (2) |
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2.8 The Exclusive-OR Gate |
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67 | (7) |
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67 | (1) |
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2.8.2 Operation of XOR Gate |
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67 | (2) |
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2.8.3 XOR Gate Truth Table |
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69 | (1) |
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69 | (2) |
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71 | (1) |
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2.8.5.1 Odd-Parity Generator |
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72 | (2) |
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2.9 The Exclusive-NOR Gate |
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74 | (3) |
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74 | (1) |
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2.9.2 Operation of XNOR Gate |
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75 | (1) |
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2.9.3 XNOR Gate Truth Table |
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75 | (1) |
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76 | (1) |
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77 | (12) |
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78 | (1) |
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Answers to Section Review Quiz |
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79 | (1) |
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80 | (1) |
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80 | (1) |
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81 | (8) |
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3 Microcontroller Hardware |
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89 | (44) |
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90 | (1) |
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3.2 A Transistor as a Switch |
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91 | (2) |
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3.3 The TTL Integrated Circuit |
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93 | (1) |
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3.4 The CMOS Integrated Circuit |
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94 | (2) |
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3.5 Using Integrated-Circuit Logic Gates |
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96 | (2) |
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3.6 Seven-Segment Displays |
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98 | (4) |
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3.7 Liquid-Crystal Displays |
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102 | (3) |
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105 | (1) |
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3.9 The 68HC11/68HC12 Microcontroller |
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106 | (15) |
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110 | (2) |
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112 | (2) |
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114 | (1) |
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115 | (1) |
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116 | (1) |
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117 | (1) |
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3.9.3 HC11 Advanced On-Chip Input/Output (I/O) Capabilities |
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118 | (3) |
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121 | (3) |
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124 | (9) |
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126 | (2) |
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Answers to Section Review Quiz |
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128 | (1) |
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129 | (1) |
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130 | (1) |
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131 | (2) |
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4 Microcontroller Software |
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133 | (42) |
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134 | (1) |
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135 | (4) |
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139 | (3) |
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142 | (6) |
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144 | (1) |
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145 | (1) |
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145 | (2) |
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147 | (1) |
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4.5 Flow and State Diagrams |
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148 | (4) |
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148 | (1) |
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4.5.2 Flowcharting Techniques |
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148 | (2) |
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150 | (2) |
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4.6 HC11 Programming Model |
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152 | (6) |
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4.6.1 The Condition Code Register (Flags) |
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153 | (1) |
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154 | (1) |
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4.6.1.2 Negative Flag (N) |
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154 | (1) |
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155 | (1) |
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4.6.1.4 Overflow Flag (V) |
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156 | (1) |
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4.6.1.5 Interrupt Mask Flag (I) |
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157 | (1) |
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4.6.1.6 Nonmaskable Interrupt Flag (X) |
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157 | (1) |
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4.6.1.7 Half-Carry Flag (H) |
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158 | (1) |
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4.6.1.8 Stop Disable Flag (S) |
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158 | (1) |
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4.7 HC11 Memory-Addressing Modes |
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158 | (6) |
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4.7.1 Extended Addressing |
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159 | (1) |
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160 | (1) |
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4.7.3 Immediate Addressing |
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161 | (1) |
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4.7.4 Inherent Addressing |
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162 | (1) |
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162 | (1) |
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4.7.6 Relative Addressing |
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163 | (1) |
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164 | (11) |
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166 | (3) |
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Answers to Section Review Quiz |
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169 | (1) |
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169 | (1) |
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170 | (1) |
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171 | (4) |
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175 | (42) |
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176 | (1) |
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177 | (10) |
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178 | (3) |
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181 | (3) |
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184 | (1) |
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5.2.4 Transfer Instructions |
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185 | (1) |
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5.2.5 Exchange Instructions |
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186 | (1) |
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187 | (8) |
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187 | (3) |
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5.3.2 Increment Instructions |
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190 | (1) |
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191 | (3) |
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5.3.4 Negate and Decrement Instructions |
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194 | (1) |
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195 | (4) |
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5.5 Shifting and Rotating |
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199 | (5) |
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5.6 Multiplication and Division |
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204 | (1) |
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5.7 CCR (Flag) Manipulation |
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205 | (1) |
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206 | (1) |
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207 | (10) |
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208 | (2) |
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Answers to Section Review Quiz |
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210 | (1) |
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210 | (1) |
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211 | (1) |
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212 | (5) |
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6 Control Structures and Subroutines |
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217 | (44) |
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218 | (1) |
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6.2 Indexed Addressing Mode |
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219 | (2) |
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6.3 Jumping and Branching |
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221 | (10) |
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223 | (2) |
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225 | (1) |
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6.3.2.1 Relative Addressing versus Absolute Addressing |
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225 | (2) |
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6.3.2.2 Conditional and Unconditional Branching |
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227 | (4) |
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231 | (4) |
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6.5 Conditional Flow and Program Loops |
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235 | (4) |
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239 | (5) |
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244 | (2) |
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246 | (2) |
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248 | (13) |
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249 | (2) |
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Answers to Section Review Quiz |
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251 | (1) |
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251 | (1) |
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252 | (1) |
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253 | (8) |
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261 | (52) |
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262 | (1) |
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7.2 Creating Source Code Files |
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263 | (9) |
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7.2.1 Writing the "Hello World!" Program |
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269 | (3) |
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272 | (4) |
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276 | (27) |
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303 | (10) |
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304 | (1) |
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Answers to Section Review Quiz |
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305 | (1) |
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305 | (1) |
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306 | (1) |
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306 | (7) |
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8 Input/Output (I/O) Ports |
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313 | (36) |
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314 | (1) |
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315 | (2) |
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317 | (1) |
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318 | (2) |
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320 | (4) |
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324 | (3) |
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8.7 I/O Using Handshaking |
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327 | (6) |
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329 | (1) |
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8.7.2 Full-Input Handshaking |
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330 | (2) |
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8.7.3 Full-Output Handshaking |
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332 | (1) |
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8.8 A Project Using Port B |
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333 | (7) |
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333 | (1) |
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8.8.2 Requirements Analysis |
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334 | (1) |
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335 | (5) |
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340 | (9) |
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341 | (1) |
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Answers to Section Review Quiz |
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342 | (1) |
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342 | (1) |
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343 | (1) |
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344 | (5) |
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349 | (56) |
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350 | (2) |
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9.2 Basics of an Interrupt |
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352 | (2) |
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9.3 Servicing an Interrupt |
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354 | (9) |
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363 | (4) |
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9.4.1 Interrupt Related Instructions |
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364 | (2) |
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9.4.2 Local and Global Control |
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366 | (1) |
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367 | (3) |
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9.5.1 Serial Communication System Interrupt Sources |
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367 | (1) |
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9.5.2 Timer System Interrupt Sources |
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367 | (1) |
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9.5.3 External Interrupts Using IRQ |
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368 | (1) |
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9.5.4 Maskable Interrupt Priority |
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369 | (1) |
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370 | (12) |
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9.6.1 Internal Timing Devices |
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371 | (4) |
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9.6.2 Output Compare Interrupts |
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375 | (1) |
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9.6.2.1 Output-Compare Registers |
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376 | (1) |
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9.6.2.2 Dedicated Comparators |
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377 | (5) |
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9.7 Nonmaskable Interrupts |
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382 | (1) |
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9.7.1 External Interrupts Using XIRQ |
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382 | (1) |
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9.7.2 Other Nonmaskable Interrupts |
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382 | (1) |
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9.8 Interrupts on the EVBU |
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383 | (2) |
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9.9 A Project with Interrupts |
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385 | (8) |
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385 | (1) |
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9.9.2 Requirements Analysis |
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385 | (1) |
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386 | (1) |
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9.9.4 Description of OC3 ISR |
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387 | (6) |
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393 | (12) |
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394 | (2) |
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Answers to Section Review Quiz |
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396 | (1) |
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396 | (1) |
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397 | (2) |
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399 | (6) |
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405 | (28) |
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406 | (1) |
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10.2 Analog-to-Digital Conversion |
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407 | (9) |
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409 | (2) |
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411 | (1) |
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10.2.3 Step Voltage and Digital Code |
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412 | (2) |
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414 | (2) |
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416 | (4) |
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417 | (1) |
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417 | (1) |
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10.3.3 Conversion Control |
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418 | (2) |
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420 | (1) |
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420 | (3) |
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10.5 A Project with Analog Capture |
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423 | (4) |
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10.5.1 Requirements Analysis |
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423 | (1) |
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423 | (1) |
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424 | (3) |
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427 | (6) |
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428 | (1) |
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Answers to Section Review Quiz |
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429 | (1) |
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429 | (1) |
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430 | (1) |
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431 | (2) |
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433 | (16) |
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434 | (1) |
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11.2 Basic Modules of Input Capture |
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435 | (1) |
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11.3 Input-Capture Registers |
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436 | (1) |
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11.4 Input Edge Detection Logic |
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437 | (2) |
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11.5 Interrupt Generation Logic |
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439 | (1) |
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11.6 A Project with Input Capture |
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440 | (3) |
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443 | (6) |
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444 | (1) |
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Answers to Section Review Quiz |
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445 | (1) |
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446 | (1) |
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447 | (1) |
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447 | (2) |
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12 Higher-Level Programming |
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449 | (30) |
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450 | (1) |
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12.2 Levels in Programming Languages |
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450 | (3) |
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453 | (12) |
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12.3.1 Getting Started with C |
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453 | (1) |
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454 | (3) |
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457 | (3) |
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12.3.4 Conditional Flow and Program Loops |
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460 | (3) |
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463 | (1) |
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12.3.6 Pointers and Arrays |
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464 | (1) |
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465 | (4) |
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469 | (4) |
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473 | (6) |
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474 | (1) |
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Answers to Section Review Quiz |
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475 | (1) |
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475 | (1) |
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476 | (1) |
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477 | (2) |
Appendix 1 Supplemental Web Site |
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479 | (2) |
Appendix 2 States and Resolution for Binary Numbers |
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481 | (2) |
Appendix 3 Basic Boolean Theorems and Identities |
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483 | (2) |
Appendix 4 The Resistor Color Code |
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485 | (2) |
Appendix 5 Waterfall Software Development Lifecycle Model |
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487 | (2) |
Appendix 6 Loading Your Program into the EEPROM |
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489 | (2) |
Appendix 7 Pulse-Width Modulation |
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491 | (2) |
Appendix 8 HC11 Instruction Set |
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493 | (8) |
Appendix 9 Comprehensive Glossary |
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501 | (12) |
Index |
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513 | |