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E-raamat: Mobile 3D Graphics SoC - From Algorithm To Chip: From Algorithm to Chip [Wiley Online]

(Korea Advanced Institute of Science and Technology, Republic of Korea), (Korea Advanced Institute of Science and Technology, Republic of Korea), (Samsung Electronics, Republi), (LG Electronics Institute of Technology, Republic of Korea)
  • Formaat: 352 pages
  • Sari: IEEE Press
  • Ilmumisaeg: 11-Jun-2010
  • Kirjastus: Wiley-IEEE Press
  • ISBN-10: 470823798
  • ISBN-13: 9780470823798
Teised raamatud teemal:
  • Wiley Online
  • Hind: 179,74 €*
  • * hind, mis tagab piiramatu üheaegsete kasutajate arvuga ligipääsu piiramatuks ajaks
Mobile 3D Graphics SoC - From Algorithm To Chip: From Algorithm to ChipSuurem pilt
  • Formaat: 352 pages
  • Sari: IEEE Press
  • Ilmumisaeg: 11-Jun-2010
  • Kirjastus: Wiley-IEEE Press
  • ISBN-10: 470823798
  • ISBN-13: 9780470823798
Teised raamatud teemal:
Wiley Online e-raamatudRohkem infot Wiley Online kohta
Raamatu kodulehekülg: https://onlinelibrary.wiley.com/doi/book/10.1002/9780470823798
As mobile entertainment rapidly evolves, there is increasing interest in mobile 3D graphics within the field of mobile electronics, particularly for handheld devices. In Mobile 3D Graphics SoC, the authors provide a comprehensive understanding of the algorithms of mobile 3D graphics and their real chip implementation methods.

Until now, most books on mobile 3D graphics have dealt only with software issues. This unique book addresses hardware issues for mobile 3D graphics, focusing on how to adopt 3D graphics algorithms to chips. Furthermore, while advanced 3D graphics hardware techniques are well understood and supported by industry standards, this is less true in the emerging mobile applications and games market. This book redresses this imbalance, providing an in-depth look at the mobile 3D graphics hardware and software and showing what these new embedded 3D graphics systems can provide for 3D graphics and games developers.

This book is ideal for researchers and industry professionals, such as mobile 3D graphics programmers and engineers in hardware design, embedded software design, and verification. Field engineers involved in embedded system and embedded software also will find this book useful for developing mobile systems. Postgraduate students in VISI design, computer games, or 3D graphics will also find the book to be a helpful reference text.

The first book to explain the principals behind mobile 3D hardware implementation, helping readers understand advanced algorithms, produce low-cost, low-power SoCs, or become familiar with embedded systems

As mobile broadcasting and entertainment applications evolve, there is increasing interest in 3D graphics within the field of mobile electronics, particularly for handheld devices. In Mobile 3D Graphics SoC, Yoo provides a comprehensive understanding of the algorithms of mobile 3D graphics and their real chip implementation methods. 3D graphics SoC (System on a Chip) architecture and its interaction with embedded system software are explained with numerous examples. Yoo divides the book into three sections: general methodology of low power SoC, design of low power 3D graphics SoC, and silicon implementation of 3D graphics SoCs and their application to mobile electronics. Full examples are presented at various levels such as system level design and circuit level optimization along with design technology. Yoo incorporates many real chip examples, including many commercial 3D graphics chips, and provides cross-comparisons of various architectures and their performance. Furthermore, while advanced 3D graphics techniques are well understood and supported by industry standards, this is less true in the emerging mobile applications and games market. This book redresses this imbalance, providing an in-depth look at the new OpenGL ES (The Standard for Embedded Accelerated 3D Graphics), and shows what these new embedded systems graphics libraries can provide for 3D graphics and games developers.

Preface ix
1 Introduction
1(8)
1.1 Mobile 3D Graphics
1(2)
1.2 Mobile Devices and Design Challenges
3(3)
1.2.1 Mobile Computing Power
3(2)
1.2.2 Mobile Display Devices
5(1)
1.2.3 Design Challenges
5(1)
1.3 Introduction to SoC Design
6(1)
1.4 About this Book
7(2)
2 Application Platform
9(58)
2.1 SoC Design Paradigms
9(9)
2.1.1 Platform and Set-based Design
9(5)
2.1.2 Modeling: Memory and Operations
14(4)
2.2 System Architecture
18(9)
2.2.1 Reference Machine and API
18(4)
2.2.2 Communication Architecture Design
22(3)
2.2.3 System Analysis
25(2)
2.3 Low-power SoC Design
27(1)
2.3.1 CMOS Circuit-level Low-power Design
27(1)
2.3.2 Architecture-level Low-power Design
27(1)
2.3.3 System-level Low-power Design
28(1)
2.4 Network-on-Chip based SoC
28(39)
2.4.1 Network-on-Chip Basics
29(12)
2.4.2 NoC Design Considerations
41(7)
2.4.3 Case Studies of Chip Implementation
48(19)
3 Introduction to 3D Graphics
67(18)
3.1 The 3D Graphics Pipeline
68(10)
3.1.1 The Application Stage
68(1)
3.1.2 The Geometry Stage
68(6)
3.1.3 The Rendering Stage
74(4)
3.2 Programmable 3D Graphics
78(7)
3.2.1 Programmable Graphics Pipeline
78(3)
3.2.2 Shader Models
81(4)
4 Mobile 3D Graphics
85(14)
4.1 Principles of Mobile 3D Graphics
85(6)
4.1.1 Application Challenges
86(1)
4.1.2 Design Principles
87(4)
4.2 Mobile 3D Graphics APIs
91(5)
4.2.1 KAIST MobileGL
91(2)
4.2.2 Khronos OpenGL-ES
93(2)
4.2.3 Microsoft's Direct3D-Mobile
95(1)
4.3 Summary and Future Directions
96(3)
5 Mobile 3D Graphics SoC
99(20)
5.1 Low-power Rendering Processor
100(10)
5.1.1 Early Depth Test
101(1)
5.1.2 Logarithmic Datapaths
102(2)
5.1.3 Low-power Texture Unit
104(2)
5.1.4 Tile-based Rendering
106(1)
5.1.5 Texture Compression
107(2)
5.1.6 Texture Filtering and Anti-aliasing
109(1)
5.2 Low-power Shader
110(9)
5.2.1 Vertex Cache
110(1)
5.2.2 Low-power Register File
111(2)
5.2.3 Mobile Unified Shader
113(6)
6 Real Chip Implementations
119(30)
6.1 KAIST RAMP Architecture
119(20)
6.1.1 RAMP-IV
120(3)
6.1.2 RAMP-V
123(4)
6.1.3 RAMP-VI
127(5)
6.1.4 RAMP-VII
132(7)
6.2 Industry Architecture
139(10)
6.2.1 nVidia Mobile GPU - SC10 and Tegra
139(4)
6.2.2 Sony PSP
143(1)
6.2.3 Imagination technology MBX/SGX
144(5)
7 Low-power Rasterizer Design
149(146)
7.1 Target System Architecture
149(1)
7.2 Summary of Performance and Features
150(1)
7.3 Block Diagram of the Rasterizer
150(1)
7.4 Instruction Set Architecture (ISA)
151(3)
7.5 Detailed Design with Register Transfer Level Code
154(141)
7.5.1 Rasterization Top Block
154(2)
7.5.2 Pipeline Architecture
156(1)
7.5.3 Main Controller Design
156(2)
7.5.4 Rasterization Core Unit
158(137)
8 The Future of Mobile 3D Graphics
295(4)
8.1 Game and Mapping Applications Involving Networking
295(1)
8.2 Moves Towards More User-centered Applications
296(1)
8.3 Final Remarks
297(2)
Appendix Verilog HDL Design
299(24)
A.1 Introduction to Verilog Design
299(1)
A.2 Design Level
300(1)
A.2.1 Behavior Level
300(1)
A.2.2 Register Transfer Level
300(1)
A.2.3 Gate Level
300(1)
A.3 Design Flow
301(4)
A.3.1 Specification
302(1)
A.3.2 High-level Design
302(1)
A.3.3 Low-level Design
303(1)
A.3.4 RTL Coding
303(1)
A.3.5 Simulation
304(1)
A.3.6 Synthesis
304(1)
A.3.7 Placement and Routing
305(1)
A.4 Verilog Syntax
305(13)
A.4.1 Modules
306(1)
A.4.2 Logic Values and Numbers
307(1)
A.4.3 Data Types
308(1)
A.4.4 Operators
309(2)
A.4.5 Assignment
311(1)
A.4.6 Ports and Connections
312(1)
A.4.7 Expressions
312(2)
A.4.8 Instantiation
314(2)
A.4.9 Miscellaneous
316(2)
A.5 Example of Four-bit Adder with Zero Detection
318(2)
A.6 Synthesis Scripts
320(3)
Glossaries 323(2)
Index 325
Hoi Jun Yoo is a Professor of Electrical Engineering at the Korea Advanced Institute of Science and Technology (KAIST) and currently serves as Project Manager for the Korea Ministry of Information and Communication's IT SoC and Post-PC programs. Yoo's industry experience includes time with Bell Communications Research in Red Bank, NJ, where he invented the two-dimensional phase-locked VCSEL array, the front-surface-emitting laser, and the high-speed lateral HBT, as well as an appointment as Manager of a DRAM design group at Hyundai Electronics. He has written popular Korean books on DRAM design and high performance DRAM, and in 1994 received the Electronic Industrial Association of Korea Award for his contribution to DRAM technology, along with the Korea Semiconductor Industry Association Award in 2002. Yoo is the founder the System Integration and IP Authoring Research Center (SIPAC), a national-level center funded by the Korean government. Yoo holds a B.S. in Electronic Engineering from Seoul National University and an M.S. and Ph.D degrees in Electrical Engineering from KAIST.

Jeong-Ho Woo is a PhD candidate at KAIST. Ju-Ho Sohn works at LG Electronics, and Byung-Gyu Nam works for Samsung.
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