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Physics and Technology of Crystalline Oxide Semiconductor CAAC-IGZO: Application to LSI [Hardback]

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  • Format: Hardback, 376 pages, height x width x depth: 246x173x23 mm, weight: 726 g
  • Series: Wiley Series in Display Technology
  • Pub. Date: 23-Dec-2016
  • Publisher: John Wiley & Sons Inc
  • ISBN-10: 1119247349
  • ISBN-13: 9781119247340
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Physics and Technology of Crystalline Oxide Semiconductor CAAC-IGZO: Application to LSILarger Image
  • Format: Hardback, 376 pages, height x width x depth: 246x173x23 mm, weight: 726 g
  • Series: Wiley Series in Display Technology
  • Pub. Date: 23-Dec-2016
  • Publisher: John Wiley & Sons Inc
  • ISBN-10: 1119247349
  • ISBN-13: 9781119247340
Other books in subject:
Permanent link: https://www.kriso.ee/db/9781119247340.html
Keywords:
This book describes the application of c-axis aligned crystalline In-Ga-Zn oxide (CAAC-IGZO) technology in large-scale integration (LSI) circuits. The applications include Non-volatile Oxide Semiconductor Random Access Memory (NOSRAM), Dynamic Oxide Semiconductor Random Access Memory (DOSRAM), central processing unit (CPU), field-programmable gate array (FPGA), image sensors, and etc. The book also covers the device physics (e.g., off-state characteristics) of the CAAC-IGZO field effect transistors (FETs) and process technology for a hybrid structure of CAAC-IGZO and Si FETs. It explains an extremely low off-state current technology utilized in the LSI circuits, demonstrating reduced power consumption in LSI prototypes fabricated by the hybrid process. A further two books in the series will describe the fundamentals; and the specific application of CAAC-IGZO to LCD and OLED displays.

Key features:

• Outlines the physics and characteristics of CAAC-IGZO FETs that contribute to favorable operations of LSI devices.
• Explains the application of CAAC-IGZO to LSI devices, highlighting attributes including low off-state current, low power consumption, and excellent charge retention.
• Describes the NOSRAM, DOSRAM, CPU, FPGA, image sensors, and etc., referring to prototype chips fabricated by a hybrid process of CAAC-IGZO and Si FETs.
About the Editors x
List of Contributors xii
Series Editor's Foreword xiii
Preface xv
Acknowledgments xviii
1 Introduction 1(10)
1.1 Overview of this Book
1(2)
1.2 Background
3(4)
1.2.1 Typical Characteristics of CAAC-IGZO FETs
3(1)
1.2.2 Possible Applications of CAAC-IGZO FETs
4(3)
1.3 Summary of Each
Chapter
7(2)
References
9(2)
2 Device Physics of CAAC-IGZO FET 11(91)
2.1 Introduction
11(3)
2.2 Off-State Current
14(15)
2.2.1 Off-State Current Comparison between Si and CAAC-IGZO FETs
14(2)
2.2.2 Measurement of Extremely Low Off-State Current
16(7)
2.2.3 Theoretical Discussion with Energy Band Diagram
23(5)
2.2.4 Conclusion
28(1)
2.3 Subthreshold Characteristics
29(10)
2.3.1 Estimation of ICUT by SS
30(3)
2.3.2 Extraction Method of Interface Levels
33(2)
2.3.3 Reproduction of Measured Value and Estimation of lcut
35(3)
2.3.4 Conclusion
38(1)
2.4 Technique for Controlling Threshold Voltage (Vth)
39(10)
2.4.1 Vth Control by Application of Back-Gate Bias
39(3)
2.4.2 Vth Control by Formation of Circuit for Retaining Back-Gate Bias
42(3)
2.4.3 Vth Control by Charge Injection into the Charge Trap Layer
45(4)
2.4.4 Conclusion
49(1)
2.5 On-State Characteristics
49(13)
2.5.1 Channel-Length Dependence of Field-Effect Mobility
50(9)
2.5.2 Measurement of Cut-off Frequency
59(3)
2.5.3 Summary
62(1)
2.6 Short-Channel Effect
62(21)
2.6.1 Features of S-ch CAAC-IGZO FETs
63(7)
2.6.2 Effect of S-ch Structure
70(1)
2.6.3 Intrinsic Accumulation-Mode Device
71(3)
2.6.4 Dielectric Anisotropy
74(2)
2.6.5 Numerical Calculation of the Band Diagrams in IGZO FETs
76(6)
2.6.6 Summary
82(1)
2.7 20-nm-Node CAAC-IGZO FET
83(9)
2.7.1 TGSA CAAC-IGZO FET
83(3)
2.7.2 Device Characteristics
86(3)
2.7.3 Memory-Retention Characteristics
89(3)
2.7.4 Summary
92(1)
2.8 Hybrid Structure
92(6)
2.8.1 TGTC Structure
93(1)
2.8.2 TGSA Structure
94(2)
2.8.3 Hybrid Structure
96(2)
Appendix: Comparison between CAAC-IGZO and Si
98(1)
References
99(3)
3 NOSRAM 102(35)
3.1 Introduction
102(1)
3.2 Memory Characteristics
103(1)
3.3 Application of CAAC-IGZO FETs to Memory and their Operation
104(2)
3.4 Configuration and Operation of NOSRAM Module
106(2)
3.4.1 NOSRAM Module
106(1)
3.4.2 Setting Operational Voltage of NOSRAM Module
106(2)
3.4.3 Operation of NOSRAM Module
108(1)
3.5 Multilevel NOSRAM
108(12)
3.5.1 4-Level (2 Bits/Cell) NOSRAM Module
110(2)
3.5.2 8-Level (3 Bits/Cell) NOSRAM Module
112(2)
3.5.3 16-Level (4 Bits/Cell) NOSRAM Module
114(5)
3.5.4 Stacked Multilevel NOSRAM
119(1)
3.6 Prototype and Characterization
120(16)
3.6.1 2-Level NOSRAM
120(8)
3.6.2 4-Level NOSRAM
128(1)
3.6.3 8-Level NOSRAM
128(1)
3.6.4 16-Level NOSRAM
129(4)
3.6.5 Comparison of Prototypes
133(3)
References
136(1)
4 DOSRAM 137(16)
4.1 Introduction
137(1)
4.2 Characteristics and Problems of DRAM
138(1)
4.3 Operations and Characteristics of DOSRAM Memory Cell
138(1)
4.4 Configuration and Basic Operation of DOSRAM
139(1)
4.4.1 Circuit Configuration and Operation of DOSRAM
139(1)
4.4.2 Hybrid Structure of DOSRAM
139(1)
4.5 Operation of Sense Amplifier
140(3)
4.5.1 Writing Operation
140(1)
4.5.2 Reading Operation
141(2)
4.6 Characteristic Measurement
143(4)
4.6.1 Writing Characteristics
143(1)
4.6.2 Reading Characteristics
144(1)
4.6.3 Data-Retention Characteristics
145(1)
4.6.4 Summary of 8-kbit DOSRAM
146(1)
4.7 Prototype DOSRAM Using 60-nm Technology Node
147(4)
4.7.1 Configuration of Prototype
147(1)
4.7.2 Measurements of Prototype Characteristics
148(3)
4.7.3 Summary for Prototype DOSRAM
151(1)
4.8 Conclusion
151(1)
References
152(1)
5 CPU 153(41)
5.1 Introduction
153(1)
5.2 Normally-Off Computing
153(3)
5.3 CPUs
156(25)
5.3.1 Flip-Flop (FF)
158(8)
5.3.2 8-Bit Normally-Off CPU
166(4)
5.3.3 32-Bit Normally-Off CPU (MIPS-Like CPU)
170(4)
5.3.4 32-Bit Normally-Off CPU (ARM® Cortex®-MO)
174(7)
5.4 CAAC-IGZO Cache Memory
181(11)
References
192(2)
6 FPGA 194(56)
6.1 Introduction
194(1)
6.2 CAAC-IGZO FPGA
195(14)
6.2.1 Overview
195(2)
6.2.2 PRS
197(3)
6.2.3 PLE
200(2)
6.2.4 Prototype
202(7)
6.3 Multicontext FPGA Realizing Fine-Grained Power Gating
209(17)
6.3.1 Overview
209(1)
6.3.2 Normally-Off Computing
209(7)
6.3.3 Prototype
216(10)
6.4 Subthreshold Operation of FPGA
226(14)
6.4.1 Overview
226(1)
6.4.2 Subthreshold Operation
227(7)
6.4.3 Prototype
234(6)
6.5 CPU + FPGA
240(7)
6.5.1 Overview
240(1)
6.5.2 CPU Computing
241(1)
6.5.3 CPU + GPU Computing
242(1)
6.5.4 CPU + FPGA Computing
243(3)
6.5.5 CAAC-IGZO CPU + CAAC-IGZO FPGA Computing
246(1)
References
247(3)
7 Image Sensor 250(43)
7.1 Introduction
250(1)
7.2 Global Shutter Image Sensor
251(11)
7.2.1 Sensor Pixel
251(1)
7.2.2 Global and Rolling Shutters
252(2)
7.2.3 Challenges Facing Adoption of Global Shutter
254(1)
7.2.4 CAAC-IGZO Image Sensor
255(7)
7.3 Image Sensor Conducting High-Speed Continuous Image Capture
262(16)
7.3.1 Overview
262(1)
7.3.2 Conventional High-Speed Continuous-Capturing Image Sensor
263(1)
7.3.3 High-Speed Continuous-Capturing CAAC-IGZO Image Sensor
263(13)
7.3.4 Application to Optical Flow System
276(2)
7.4 Motion Sensor
278(13)
7.4.1 Overview
278(1)
7.4.2 Configuration
278(5)
7.4.3 Prototype
283(2)
7.4.4 Sensor Pixel Threshold-Compensation Function
285(6)
References
291(2)
8 Future Applications/Developments 293(50)
8.1 Introduction
293(1)
8.2 RF Devices
294(9)
8.2.1 Overview
294(1)
8.2.2 NOSRAM Wireless IC Tag
294(4)
8.2.3 Application Examples of NOSRAM Wireless IC Tags
298(5)
8.3 X-Ray Detector
303(7)
8.3.1 Outline
303(1)
8.3.2 X-Ray Detection Principle
303(1)
8.3.3 CAAC-IGZO X-Ray Detector
304(4)
8.3.4 Fabrication Example and Evaluation
308(2)
8.4 CODEC
310(4)
8.4.1 Introduction
310(1)
8.4.2 Encoder/Decoder
311(2)
8.4.3 CAAC-IGZO CODEC
313(1)
8.5 DC-DC Converters
314(8)
8.5.1 Introduction
314(1)
8.5.2 Non-hybrid DC-DC Converter
315(1)
8.5.3 Fabricated CAAC-IGZO Bias Voltage Sampling Circuit with Amplifier
315(2)
8.5.4 Evaluation Results of Fabricated CAAC-IGZO Bias Voltage Sampling Circuit with Amplifier
317(1)
8.5.5 Proposed DC-DC Converter
318(4)
8.6 Analog Programmable Devices
322(8)
8.6.1 Overview
322(1)
8.6.2 Design
322(1)
8.6.3 Prototype
323(7)
8.6.4 Possible Application to Phase-Locked Loop
330(1)
8.7 Neural Networks
330(5)
8.7.1 Introduction
330(1)
8.7.2 Neural Networks
330(2)
8.7.3 CAAC-IGZO Neural Network
332(2)
8.7.4 Conclusion
334(1)
8.8 Memory-Based Computing
335(4)
8.9 Backtracking Programs with Power Gating
339(2)
References
341(2)
Appendix 343(2)
Index 345
Shunpei Yamazaki, Semiconductor Energy Laboratory Co., Ltd., Kanagawa, JAPAN Dr. Shunpei Yamazaki is an authority on semiconductors, memory devices, and liquid crystal displays. Listed on over 4,000 US utility patents, Dr. Yamazaki was named in the Guinness Book of World Records as holding the most patents in the world; hailed the most prolific inventor in history by USA Today (in 2005). His most notable work is on the thin-film transistor -- a significant discovery being a crystalline structure in Indium gallium zinc oxide (IGZO) material, which he discovered "by chance" in 2009. Today Dr. Yamazaki is President of the Semiconductor Energy Laboratory (SEL), where he and his team pioneered the unique development of ultra-low-power devices using CAAC-IGZO technology. A joint venture with the Sharp Corporation manufacturing smartphones using crystalline oxide semiconductors (IGZO) is a global first. In 2015 Dr. Yamazaki received the SID (Society for Information Display) Special Recognition Award for "discovering CAAC-IGZO semiconductors, leading its practical application, and paving the way to next-generation displays." His paper on CAAC-IGZO ranked in the top 15 most downloaded papers of Wiley Electrical Engineering and Communications Technology journals, 2014. Dr. Yamazaki is also an IEEE Life Fellow.

Masahiro Fujita, University of Tokyo, Japan Masahiro Fujita: received his Ph.D. in Information Engineering from the University of Tokyo in 1985 on his work on model checking of hardware designs by using logic programming languages. In 1985, he joined Fujitsu as a researcher and started to work on hardware automatic synthesis as well as formal verification methods and tools. From 1993 to 2000, he was director at Fujitsu Laboratories of America and headed a hardware formal verification group developing a formal verifier for real-life designs. Since March 2000, he has been a professor at VLSI Design and Education Center of the University of Tokyo. He has authored and co-authored more than 10 books and 300 publications, and has been given several awards from scientific societies. His research interests include synthesis and verification of hardware and software systems.