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E-raamat: Switch/Router Architectures: Systems with Crossbar Switch Fabrics [Taylor & Francis e-raamat]

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  • Formaat: 366 pages, 4 Tables, black and white; 129 Line drawings, black and white; 7 Illustrations, black and white
  • Ilmumisaeg: 28-Nov-2019
  • Kirjastus: CRC Press
  • ISBN-13: 9780367809041
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Switch/Router Architectures: Systems with Crossbar Switch FabricsSuurem pilt
  • Formaat: 366 pages, 4 Tables, black and white; 129 Line drawings, black and white; 7 Illustrations, black and white
  • Ilmumisaeg: 28-Nov-2019
  • Kirjastus: CRC Press
  • ISBN-13: 9780367809041
Teised raamatud teemal:
Taylor & Francis e-raamatudRohkem infot Taylor & Francis e-raamatute kohta
Raamatu kodulehekülg: https://www.taylorfrancis.com/books/9780367809041
Crossbar switch fabrics offer many benefits when designing switch/routers. This book discusses switch/router architectures using design examples and case studies of well-known systems that employ crossbar switch fabric as their internal interconnects. This book looks to explain the design of switch/routers from a practicing engineer’s perspective. It uses a broad range of design examples to illustrate switch/router designs and provides case studies to enhance readers comprehension of switch/router architectures. The book goes on to discuss industry best practices in switch/router design and explains the key features and differences between unicast and multicast packet forwarding architectures. This book will be of benefit to telecoms/networking industry professionals and engineers as well as researchers and academics looking for more practical and efficient approaches for designing non-blocking crossbar switch fabrics.
Preface xv
Author xvii
PART 1 Characteristics of Switch/Routers with Crossbar Switch Fabrics
Chapter 1 The Switch/Router: Integrated OSI Layers 2 and 3 Forwarding on a Single Platform
3(44)
1.1 Introduction
3(1)
1.2 Flow-Based Layer 3 Forwarding
4(1)
1.3 Network Topology-Based Layer 3 Forwarding
5(3)
1.4 Using Centralized or Distributed Forwarding Engines
8(2)
1.4.1 Forwarding Using a Centralized Forwarding Engine
8(1)
1.4.2 Forwarding Using Distributed Forwarding Engines
9(1)
1.5 Building the Layer 2 Forwarding Tables
10(2)
1.5.1 MAC Address Aging
10(1)
1.5.2 Synchronizing MAC Address Tables in a Distributed Forwarding Architecture
11(1)
1.5.3 History of MAC Address Changes
11(1)
1.6 Memory Architectures for Storing Forwarding Databases
12(4)
1.6.1 Content Addressable Memory (CAM)
12(2)
1.6.2 Ternary Content Addressable Memory (TCAM)
14(2)
1.7 Physical and Logical Interfaces on a Switch/Router
16(28)
1.7.1 Layer 2 (Switch) Interfaces
17(1)
1.7.1.1 Access Ports
17(1)
1.7.1.2 Access Ports and Tagged Packets
18(1)
1.7.1.3 Trunk Ports
19(1)
1.7.1.4 Port Channels or Port Groups
20(1)
1.7.2 Layer 3 (Routed) Interfaces
21(1)
1.7.2.1 Physical Layer 3 (Routed) Interfaces
21(2)
1.7.2.2 Logical Layer 3 (Routed) Interfaces (VLAN Interfaces or Switch Virtual Interfaces (SVIs))
23(2)
1.7.3 Subinterfaces
25(2)
1.7.4 Loopback Interfaces
27(1)
1.7.4.1 Local Communications
28(1)
1.7.4.2 Testing and Performance Analysis
28(1)
1.7.4.3 Device Identification
28(1)
1.7.4.4 Routing Information Maintenance
29(2)
1.7.5 Tunnel Interfaces
31(1)
1.7.5.1 Layer 3 Tunnel Interfaces/Ports Examples
32(4)
1.7.5.2 Layer 2 Tunnel Interfaces/Ports Examples
36(4)
1.7.6 Port Channels
40(1)
1.7.6.1 Layer 2 and Layer 3 Port Channels
41(2)
1.7.6.2 Load Balancing
43(1)
1.7.6.3 Dynamic Configuration of Port Channels
44(1)
1.8 Challenges
44(3)
References
46(1)
Chapter 2 Understanding Crossbar Switch Fabrics
47(62)
2.1 Introduction
47(2)
2.2 The Crossbar Switch Fabric
49(12)
2.2.1 Implementing a Crossbar Switch
50(1)
2.2.2 Building Multistage Switches
51(4)
2.2.3 Challenges in Building Larger Crosspoint Arrays
55(3)
2.2.4 Designing Today's System Interconnects
58(3)
2.3 Logical Architecture and Improving Data Transfer Throughput
61(4)
2.4 Components of a Practical Crossbar Switch Fabric System
65(2)
2.5 Traffic Scheduling in the Crossbar Switch
67(8)
2.5.1 The Scheduling Problem
69(1)
2.5.2 Parallel Iterative Matching (PIM)
70(2)
2.5.3 Round-Robin Matching (RRM)
72(1)
2.5.4 Iterative Round-Robin Matching with Slip (iSLIP)
73(2)
2.5.5 Other Considerations in the Design of Schedulers
75(1)
2.6 Handling Multicast Traffic
75(11)
2.6.1 Multicast Packet Replication
77(2)
2.6.2 Multicast Traffic Scheduling
79(1)
2.6.2.1 Full versus Partial Multicast Scheduling across the Crossbar Switch Fabric
79(1)
2.6.2.2 Scheduling in Internally Unbuffered Crossbar Switches
80(2)
2.6.2.3 Scheduling in Internally Buffered Crossbar Switches
82(1)
2.6.2.4 Special Focus: The ESLIP Scheduling Algorithm
83(3)
2.7 Data Transfer Process over the Switch Fabric
86(1)
2.8 System Monitoring and Control
87(5)
2.8.1 Main MBus Functions
89(1)
2.8.2 Alarm Functionality
90(2)
2.9 Scalability
92(3)
2.10 Fault Tolerance
95(4)
2.11 Generic Switch/Router with Crossbar Switch Fabric
99(10)
References
104(5)
Chapter 3 Introduction to Switch/Routers with Crossbar Switch Fabrics
109(14)
3.1 The Crossbar Switch Fabric
109(1)
3.2 Architectures with Crossbar-Based Switch Fabrics and Centralized Forwarding Engines
110(2)
3.2.1 Architectures with Forwarding Using a Flow/Route Cache in Centralized Processor
110(1)
3.2.2 Architectures with Forwarding Using an Optimized Lookup System in Centralized Processor
111(1)
3.3 Architectures with Crossbar-Based Switch Fabrics and Distributed Forwarding Engines
112(4)
3.3.1 Architectures with Forwarding Engine and Flow/Route Cache in Line Cards
113(1)
3.3.2 Architectures with Fully Distributed Forwarding Engines in Line Cards
114(2)
3.4 Relating Architectures to Switch/Router Types
116(7)
PART 2 Design Examples and Case Studies
Chapter 4 Cisco Catalyst 6500 Series Switches with Supervisor Engines 1A and 2
123(34)
4.1 Introduction
123(1)
4.2 Main Architectural Features of the Catalyst 6500 Series
124(4)
4.3 Catalyst 6500 Switch Fabric Architecture
128(4)
4.4 Catalyst 6500 Line Cards Architectures
132(1)
4.4.1 Fabric-Enabled Line Cards
132(1)
4.4.2 Fabric-Only Line Cards
133(1)
4.5 Catalyst 6500 Control Plane Implementation and Forwarding Engines---Supervisor Engines
133(12)
4.5.1 Supervisor Engine 1A Architecture
133(1)
4.5.1.1 Supervisor Engine 1A with Only a PFC1
133(2)
4.5.1.2 Supervisor Engine 1A with a PFC1 and MSFC1/MSFC2
135(2)
4.5.2 Supervisor Engine 2 Architecture
137(1)
4.5.2.1 Supervisor Engine 2 with a PFC2
137(3)
4.5.2.2 Supervisor Engine 2 with a PFC 2 and MSFC2
140(1)
4.5.3 Supporting High Availability with Dual Supervisor Engines
141(1)
4.5.4 Distributed Forwarding Card
142(1)
4.5.4.1 Packet Forwarding in the DFC
143(2)
4.6 Packet Flow in the Catalyst 6500
145(12)
4.6.1 Packet Flow in the Catalyst 6500 with Centralized Forwarding
145(3)
4.6.2 Packet Flow in the Catalyst 6500 with Distributed Forwarding
148(8)
References
156(1)
Chapter 5 Avaya P580 and P882 Routing Switch Architecture with 80-Series Media Module
157(18)
5.1 Introduction
157(1)
5.2 Basic Architecture
157(1)
5.3 Data Flow through the Avaya 80-Series Switch
158(3)
5.4 Quality of Service (QoS) Mechanisms
161(9)
5.4.1 Classification Precedence
161(2)
5.4.2 DiffServ Mapping Table
163(1)
5.4.3 Queuing and Scheduling
164(1)
5.4.4 Traffic Management
164(3)
5.4.5 IEEE 802.1p/Q and DSCP or ToS Standards in the Avaya 80-Series
167(1)
5.4.5.1 Diff Serv's Per-Hop Behaviors (PHB)
167(1)
5.4.5.2 Packet Loss Priority (PLP)
168(1)
5.4.5.3 Avaya 80-Series Recommendations for IEEE 802.1p/Q, DSCP Code Point, and Queues
169(1)
5.5 Designing the High-Performance Switch/Router
170(5)
References
172(3)
Chapter 6 Foundry Networks Multilayer Switches with IronCore" Network Interface Module
175(18)
6.1 Introduction
175(1)
6.2 Switch Chassis Overview
175(2)
6.3 Chassis Crossbar Switch Fabric
177(2)
6.4 IronCore" Network Interface Module Architecture
179(8)
6.4.1 Network Interface Module Components
180(1)
6.4.1.1 Physical Ports
180(2)
6.4.1.2 Multi-Port MAC
182(1)
6.4.2 Packet Processor---The Forwarding Engine of IronCore
182(1)
6.4.3 Route Processor Components
183(1)
6.4.3.1 System Management Module/Board---The Route Processor Module
183(1)
6.4.3.2 System Management Interface/CPU
183(1)
6.4.3.3 CPU Path and Data Transfer Engine Path
184(1)
6.4.3.4 Management Bus
184(1)
6.4.4 Shared Memory and Switch Fabric Interface Components
184(1)
6.4.4.1 Shared-Memory Switch Fabric and Buffer Pool
184(1)
6.4.4.2 Data Transfer Engine
185(1)
6.4.4.3 Crossbar Backplane Connection--- Module Connection to Crossbar Switch Fabric
185(1)
6.4.4.4 Multiple Destination Output Priority Queues
185(1)
6.4.4.5 Multiple Input Source Buffers per Output Port
186(1)
6.5 Biglron 4000 Complete Crossbar Switch System
187(1)
6.6 Packet Processing Overview
188(3)
6.6.1 Role of the Data Transfer Engine and Packet Flow for Unicast and Multicast Traffic
189(1)
6.6.1.1 Forwarding Unicast Traffic
190(1)
6.6.1.2 Forwarding Multicast Traffic
190(1)
6.7 Important Attributes of the Shared-Memory Based IronCore Architecture
191(2)
References
192(1)
Chapter 7 Foundry Networks Multilayer Switches with JetCore" Network Interface Module
193(26)
7.1 Introduction
193(1)
7.2 JetCore" Network Interface Module Architecture
193(14)
7.2.1 Network Interface Components
197(1)
7.2.1.1 Physical Ports
197(1)
7.2.1.2 Media Access Controller (MAC)
197(1)
7.2.2 JetCore Forwarding Engine Components
197(1)
7.2.2.1 Packet Classifier---The Forwarding Engine of JetCore
197(2)
7.2.2.2 Content Addressable Memory (CAM)
199(1)
7.2.2.3 Parameter Random Access Memory (PRAM)
200(1)
7.2.2.4 VLAN Multicast Assist Module
200(1)
7.2.2.5 Transmit Pipeline
201(1)
7.2.3 Memory Components of the Port Group Switching Logic and Switch Fabric
201(1)
7.2.3.1 Shared-Memory Switch Fabric
201(1)
7.2.3.2 Buffer Manager
202(1)
7.2.3.3 Shared-Memory Buffer Pool
203(1)
7.2.4 Route Processor Components
203(1)
7.2.4.1 Command Bus
203(1)
7.2.4.2 System Management Interface
203(1)
7.2.5 Module Crossbar Switch Fabric
204(1)
7.2.5.1 Backplane Connectivity
204(1)
7.2.5.2 Replication of Multicast Packets
204(1)
7.2.6 Multiple Destination Output Priority Queues
205(2)
7.3 Other JetCore Features
207(1)
7.4 Packet Processing Overview
208(3)
7.4.1 Packet Flow for Unicast and Multicast Traffic
208(1)
7.4.1.1 Forwarding Unicast Traffic to Destination Port(s) on a Different Module Crossbar Switch Fabric
209(1)
7.4.1.2 Forwarding Multicast Traffic to Destination Port(s) on Different Module Crossbar Switch Fabric(s)
209(2)
7.5 Foundry IronWare" Software Architecture
211(2)
7.6 Switching and Routing Architecture
213(6)
7.6.1 Foundry Switching and Routing Architecture
213(2)
7.6.2 Packet Handling Mechanisms in the Multilayer Switch
215(1)
7.6.3 Fastlron Multilayer Switch Architecture
216(1)
7.6.4 Biglron, Netlron, and Turbolron Multilayer Switch Architecture
217(1)
Reference
218(1)
Chapter 8 Cisco Catalyst 6500 Series Switches with Supervisor Engine 720
219(36)
8.1 Introduction
219(2)
8.2 Cisco Catalyst 6500 Backplane
221(1)
8.3 Cisco Catalyst 6500 Crossbar Switch Fabric
222(3)
8.4 Supervisor Engine 720
225(4)
8.4.1 Multilayer Switch Feature Card 3(MSFC3)
228(1)
8.4.2 Policy Feature Card 3 (PFC3)
228(1)
8.5 Supervisor Engine 720-3B
229(1)
8.5.1 Policy Feature Card 3B (PFC3B)
230(1)
8.6 Supervisor Engine 720-3BXL
230(1)
8.6.1 Policy Feature Card 3BXL (PFC3BXL)
230(1)
8.7 Packet Forwarding in Supervisor Engines 720, 720-3B, and 720-3BXL
230(1)
8.8 Catalyst 6500 Line Cards Supported by Supervisor Engine 720
231(7)
8.8.1 dCEF256 Line Card Architecture
232(2)
8.8.2 CEF720 Line Card Architecture
234(4)
8.8.3 dCEF720 Line Card Architecture
238(1)
8.9 Functional Elements of Distributed Forwarding Card (DFC) and Policy Feature Card (PFC)
238(6)
8.9.1 A Note on NetFlow
242(1)
8.9.2 Access Control Lists for QoS and Security Processing
242(1)
8.9.3 Distributed Forwarding Operations in Catalyst 6500 with PFC or DFC
243(1)
8.10 Packet Flow in the Catalyst 6500 with Supervisor Engine 720
244(11)
8.10.1 Centralized Forwarding
244(3)
8.10.2 Distributed Forwarding
247(3)
8.10.3 Flow Cache-Based Packet Forwarding--- Accelerated Cisco Express Forwarding (aCEF)
250(3)
References
253(2)
Chapter 9 Multicast Routing and Multicast Forwarding Information Base (MFIB) Architecture
255(50)
9.1 Introduction
255(1)
9.2 Benefits of the MFIB Architecture
256(1)
9.3 Protocol-Independent Multicast (PIM)
257(1)
9.4 Types of Multicast Table Entries
258(1)
9.4.1 Multicast Table Context
259(1)
9.5 Types of Multicast Tables
259(21)
9.5.1 IGMP Cache
260(1)
9.5.2 Reverse-Path Forwarding (RPF) Table
261(1)
9.5.3 PIM Dense Mode (PIM-DM) Table Entries
262(1)
9.5.4 PIM Sparse Mode (PIM-SM) Table Entries
263(1)
9.5.4.1 Concept of Rendezvous Point
264(1)
9.5.4.2 PIM-SM Router Architecture
265(1)
9.5.4.3 Sending Multicast Data
265(2)
9.5.4.4 Receiving Multicast Data
267(1)
9.5.4.5 PIM Assert Mechanism
268(1)
9.5.4.6 Electing the PIM Forwarder---PIM Assert Winner
269(1)
9.5.5 PIM Sparse-Dense Mode
270(1)
9.5.5.1 Auto-RP
271(2)
9.5.5.2 Using PIM Sparse-Dense with Auto-RP
273(1)
9.5.6 Multicast Source Discovery Protocol (MSDP) Cache
273(1)
9.5.6.1 MSDP Peer-RPF Checks
274(1)
9.5.7 PIM Source Specific Multicast (PIM-SSM) Table Entries
275(1)
9.5.8 Bidirectional PIM (BIDIR-PIM) Table Entries
276(2)
9.5.8.1 Designated Forwarder Election
278(1)
9.5.8.2 Building the Bidirectional Group Tree and Packet Forwarding
279(1)
9.6 Multicast Reverse Path Forwarding (RPF)
280(5)
9.6.1 Using the RPF Table
281(2)
9.6.2 Data-Plane versus Control-Plane RPF Check
283(1)
9.6.3 RPF Check
284(1)
9.7 MFIB Components
285(12)
9.7.1 Protocols and Tables Used in IP Multicast Routing
288(2)
9.7.2 Layers 2 and 3 Multicast Tables Entries in a Switch/Router
290(2)
9.7.2.1 Benefits of IGMP Snooping
292(1)
9.7.3 Multicast Fast Drop
292(1)
9.7.4 Using the Multicast Routing Information Base (MRIB)
293(1)
9.7.5 Using the Multicast Forwarding Information Base (MFIB)
294(1)
9.7.6 Using the Distributed MFIB
295(2)
9.8 Multicast Packet Forwarding Using the MFIB
297(4)
9.8.1 Process Switching
297(2)
9.8.2 Fast-Path Processing Using Flow/Route Caching
299(1)
9.8.3 Fast-Path Processing Using Optimized Forwarding Table Lookup Structures (without Flow/Route Caching)
299(2)
9.9 PIM-SM Tunnel Interfaces
301(4)
References
302(3)
Chapter 10 Unicast versus Multicast Packet Forwarding: A Case Study
305(38)
10.1 Introduction
305(1)
10.2 Unicast Forwarding Table and TCAM Lookup Architecture
305(3)
10.3 Unicast Forwarding Examples
308(11)
10.3.1 Catalyst 6500 Supervisor Engine 2
309(1)
10.3.2 Supervisor Engine 32
309(5)
10.3.3 Catalyst 6500 Supervisor Engine 720
314(5)
10.4 Multicast Forwarding Tables and TCAM Lookup Architecture
319(1)
10.5 Multicast Packet Replication
319(7)
10.5.1 Centralized Packet Replication
323(1)
10.5.2 Packet Replication in the Line Cards
323(1)
10.5.2.1 Ingress Multicast Packet Replication
324(1)
10.5.2.2 Egress Multicast Packet Replication
324(1)
10.5.3 Combined Replication Methods
325(1)
10.5.4 Packet Replication at Layer 3 versus Layer 2
325(1)
10.5.5 Packet Replication in the Switch Fabric: Preferred Method
326(1)
10.6 Multicast Forwarding Architecture Example: Catalyst 6500 Supervisor Engine 720
326(17)
10.6.1 Ingress Packet Replication Mode Example: Catalyst 6500 Supervisor Engine 720
333(2)
10.6.2 Egress Packet Replication Mode Example: Catalyst 6500 Supervisor Engine 720
335(7)
References
342(1)
Index 343
James Aweya, PhD, is a chief research scientist at Etisalat British Telecom Innovation Center (EBTIC), Khalifa University, Abu Dhabi, UAE. He has been granted 64 US patents and has published over 54 journal papers, 39 conference papers, and 43 Nortel technical reports. He has authored one book and is a senior member of the Institute of Electrical and Electronics Engineers (IEEE).
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