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E-raamat: Understanding Delta-Sigma Data Converters, Second Edition 2nd Edition [Wiley Online]

(Oregon State University), (University of California, Los Angeles),
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Understanding Delta-Sigma Data Converters, Second Edition 2nd EditionSuurem pilt
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Raamatu kodulehekülg: https://onlinelibrary.wiley.com/doi/book/10.1002/9781119258308

This book explains the principles and operations of delta-sigma ADCs in physical and conceptual terms rather than complicated mathematics in accordance to the developments over the past decade. To reflect the changed needs of designers, the second edition includes some new material on both theory and design techniques. The emphasis of topics in the existing material has also been changed. New chapters have been added on the cascade (MASH) architecture, on DAC mismatch effects and their mitigation, as well as expanded chapters on continuous-time delta-sigma ADCs, on circuit design techniques for both sampled-data and continuous-time ADCs, on decimation and interpolation filters, and on incremental ADCs.

Preface xiii
1 The Magic of Delta-Sigma Modulation 1(26)
1.1 The Need for Oversampling Converters
1(2)
1.2 Nyquist and Oversampling Conversion by Example
3(8)
1.2.1 The Coffee Shop Problem
4(2)
1.2.2 The Dictionary Problem
6(5)
1.3 Higher-Order Single-Stage Noise-Shaping Modulators
11(1)
1.4 Multi-Stage and Multi-Quantizer Delta-Sigma Modulators
12(2)
1.5 Mismatch Shaping in Multi-Bit Delta-Sigma Modulators
14(1)
1.6 Continuous-Time Delta-Sigma Modulation
15(2)
1.7 Bandpass Delta-Sigma Modulators
17(1)
1.8 Incremental Delta-Sigma Converters
18(1)
1.9 Delta-Sigma Digital-to-Analog Converters
18(1)
1.10 Decimation and Interpolation
19(1)
1.11 Specifications and Figures of Merit
19(2)
1.12 Early History, Performance, and Architectural Trends
21(4)
References
25(2)
2 Sampling, Oversampling, and Noise-Shaping 27(36)
2.1 A Review of Sampling
28(2)
2.2 Quantization
30(9)
2.2.1 Quantizer Modeling
35(2)
2.2.2 Overloaded Quantizers
37(1)
2.2.3 Quantizer Modeling with Two Inputs
38(1)
2.3 Quantization Noise Reduction by Oversampling
39(3)
2.4 Noise-Shaping
42(10)
2.4.1 The Effects of Finite DC Gain of the Integrator
50(1)
2.4.2 Effect of Quantizer Nonidealities
50(1)
2.4.3 The Single-Bit First-Order Delta-Sigma Modulator
51(1)
2.5 Nonlinear Aspects of the First-Order Delta-Sigma Modulator
52(2)
2.6 MOD1 with DC Excitation
54(6)
2.6.1 Idle Tone Generation
55(2)
2.6.2 Stability of MOD1
57(1)
2.6.3 Dead-Zones
57(3)
2.7 Alternative Architectures: The Error-Feedback Structure
60(1)
2.8 The Road Ahead
60(1)
References
61(2)
3 Second-Order Delta-Sigma Modulation 63(20)
3.1 Simulation of MOD2
67(3)
3.2 Nonlinear Effects in MOD2
70(3)
3.2.1 Signal-Dependent Quantizer Gain
70(3)
3.3 Stability of MOD2
73(4)
3.3.1 Dead-Zones
75(2)
3.4 Alternative Second-Order Modulator Structures
77(3)
3.4.1 The Boser-Wooley Modulator
77(1)
3.4.2 The Silva-Steensgaard Structure
78(1)
3.4.3 The Error-Feedback Structure
79(1)
3.4.4 The Noise-Coupled Structure
79(1)
3.5 Generalized Second-Order Structures
80(2)
3.5.1 Optimal Second-Order Modulator
81(1)
3.6 Conclusions
82(1)
References
82(1)
4 High-Order Delta-Sigma Modulators 83(34)
4.1 Signal-Dependent Stability of Delta-Sigma Modulators
85(7)
4.1.1 Estimating Maximum Stable Amplitude
90(2)
4.2 Improving MSA in High-Order Delta-Sigma Converters
92(3)
4.3 Systematic NTF Design
95(2)
4.4 Noise Transfer Functions with Optimally Spread Zeros
97(1)
4.5 Fundamental Aspects of Noise Transfer Functions
98(2)
4.5.1 The Bode Sensitivity Integral
98(2)
4.6 High-Order Single-Bit Delta-Sigma Data Converters
100(4)
4.7 Loop Filter Topologies for Discrete-Time Delta-Sigma Converters
104(10)
4.7.1 Loop Filters with Distributed Feedback: The CIFB and CRFB Families
104(7)
4.7.2 Loop Filters with Distributed Feedforward and Input Coupling: The CIFF and CRFF Structures
111(2)
4.7.3 Loop Filters with Feedforward and Multiple Feedback: The CIFF-B Structure
113(1)
4.8 State-Space Description of Delta-Sigma Loops
114(1)
4.9 Conclusions
115(1)
References
115(2)
5 Multi-Stage and Multi-Quantizer Delta-Sigma Modulators 117(18)
5.1 Multi-Stage Modulators
117(3)
5.1.1 The Leslie-Singh Structure [ 1]
118(2)
5.2 Cascade (MASH) Modulators
120(3)
5.3 Noise Leakage in Cascade Modulators
123(3)
5.4 The Sturdy-MASH Architecture
126(2)
5.5 Noise-Coupled Architectures
128(3)
5.6 Cross-Coupled Architectures
131(1)
5.7 Conclusions
131(2)
References
133(2)
6 Mismatch-Shaping 135(30)
6.1 The Mismatch Problem
135(1)
6.2 Random Selection and Rotation
136(5)
6.3 Implementation of Rotation
141(4)
6.4 Alternative Mismatch-Shaping Topologies
145(6)
6.4.1 Butterfly Shuffler
145(1)
6.4.2 A-DWA and Bi-DWA
146(2)
6.4.3 Tree-Structured ESL
148(3)
6.5 High-Order Mismatch-Shaping
151(5)
6.5.1 Vector-Based Mismatch-Shaping
151(3)
6.5.2 Tree Structure
154(2)
6.6 Generalizations
156(2)
6.6.1 Tri-Level Elements
156(1)
6.6.2 Non-Unit Elements
157(1)
6.7 Transition-Error Shaping
158(4)
6.8 Conclusions
162(1)
References
162(3)
7 Circuit Design for Discrete-Time Delta-Sigma ADCs 165(58)
7.1 SCMOD2: A Second-Order Switched-Capacitor ADC
165(1)
7.2 High-Level Design
166(2)
7.2.1 NTF Selection
166(1)
7.2.2 Realization and Dynamic-Range Scaling
167(1)
7.3 Switched-Capacitor Integrator
168(6)
7.3.1 Integrator Variations
171(3)
7.4 Capacitor Sizing
174(2)
7.5 Initial Verification
176(2)
7.6 Amplifier Design
178(8)
7.6.1 Amplifier Gain
180(3)
7.6.2 Candidate Amplifier
183(3)
7.7 Intermediate Verification
186(5)
7.8 Switch Design
191(1)
7.9 Comparator Design
191(4)
7.10 Clocking
195(2)
7.11 Full-System Verification
197(4)
7.12 High-Order Modulators
201(2)
7.12.1 Architecture
201(1)
7.12.2 Capacitor Sizing
201(2)
7.12.3 Combining the Noise from Multiple SC Branches
203(1)
7.13 Multi-Bit Quantization
203(4)
7.14 Switch Design Revisited
207(2)
7.15 Double Sampling
209(2)
7.16 Gain-Boosting and Gain-Squaring
211(1)
7.17 Split-Steering and Amplifier Stacking
212(5)
7.18 Noise in Switched-Capacitor Circuits
217(4)
7.19 Conclusions
221(1)
References
221(2)
8 Continuous-Time Delta-Sigma Modulation 223(36)
8.1 CT-MOD1
224(6)
8.2 STF of CT-MOD1
230(4)
8.2.1 Summary of CT-MOD1
233(1)
8.3 Second-Order Continuous-Time Delta-Sigma Modulation
234(5)
8.3.1 Influence of the DAC Pulse Shape
237(2)
8.4 High-Order Continuous-Time Delta-Sigma Modulators
239(7)
8.4.1 Influence of DAC Pulse Shape [ 4]
241(5)
8.5 Loop-Filter Topologies
246(3)
8.5.1 The CIFB Family
246(2)
8.5.2 The CIFF Family
248(1)
8.5.3 The CIFF-B Family
249(1)
8.6 Continuous-Time Delta-Sigma Modulators with Complex NTF Zeros
249(1)
8.7 Modeling of Continuous-Time Delta-Sigma Modulators for Simulation
250(3)
8.8 Dynamic-Range Scaling
253(2)
8.9 Design Example
255(3)
8.10 Conclusions
258(1)
References
258(1)
9 Nonidealities in Continuous-Time Delta-Sigma Modulators 259(42)
9.1 Excess Loop Delay
259(12)
9.1.1 CT-MOD1: The First-Order Continuous-Time Delta-Sigma Modulator
260(3)
9.1.2 CT-MOD2: The Second-Order Continuous-Time Delta- Sigma Modulator
263(4)
9.1.3 Excess Delay Compensation in High-Order Continuous-Time Delta-Sigma Modulators with Arbitrary DAC Pulse Shapes [ 2, 3]
267(3)
9.1.4 Summary
270(1)
9.2 Time-Constant Variations of the Loop Filter
271(2)
9.3 Clock Jitter in Delta-Sigma Modulators
273(12)
9.3.1 The Discrete-Time Case
273(1)
9.3.2 Clock Jitter in Continuous-Time Delta-Sigma Modulators
274(4)
9.3.3 Clock Jitter in Single-Bit Continuous-Time Delta-Sigma Modulators
278(2)
9.3.4 Continuous-Time Delta-Sigma Modulators with RZ DACs
280(2)
9.3.5 Real Clock Sources and Phase Noise
282(3)
9.4 Addressing Clock Jitter in Continuous-Time Delta-Sigma Modulators
285(2)
9.5 Mitigating Clock Jitter Using FIR Feedback
287(6)
9.6 Comparator Metastability
293(5)
9.7 Conclusions
298(1)
References
298(3)
10 Circuit Design for Continuous-Time Delta-Sigma Modulators 301(62)
10.1 Integrators
302(3)
10.1.1 The Single-Stage OTA-RC Integrator
304(1)
10.2 The Miller-Compensated OTA-RC Integrator
305(1)
10.3 The Feedforward-Compensated OTA-RC Integrator
306(3)
10.4 Stability of Feedforward Amplifiers
309(3)
10.5 Device Noise in Continuous-Time Delta-Sigma Modulators
312(4)
10.5.1 Thermal versus Quantization Noise
315(1)
10.6 ADC Design
316(4)
10.7 Feedback DAC Design
320(11)
10.7.1 Resistive DACs
322(3)
10.7.2 Return-to-Zero and Return-to-Open DACs
325(1)
10.7.3 Current-Steering DACs
326(2)
10.7.4 Switched-Capacitor DACs
328(3)
10.8 Systematic Design Centering
331(7)
10.8.1 Closed-Loop Fitting
336(2)
10.9 Loop-Filter Nonlinearities in Continuous-Time Delta-Sigma Modulators
338(8)
10.9.1 Circuit Techniques to Improve Loop-Filter Linearity
345(1)
10.10 Case Study of a 16-Bit Audio Continuous-Time Delta-Sigma Modulator
346(12)
10.10.1 Choice of Number of Taps in the FIR DAC
349(1)
10.10.2 State-Space Modeling and Simulation with an FIR DAC
350(2)
10.10.3 Effect of Time-Constant Variations
352(1)
10.10.4 Modulator Architecture
352(1)
10.10.5 Opamp Design
353(4)
10.10.6 ADC and FIR DACs
357(1)
10.10.7 Decimation Filter
358(1)
10.11 Measurement Results
358(1)
10.12 Summary
359(1)
References
360(3)
11 Bandpass and Quadrature Delta-Sigma Modulation 363(44)
11.1 The Need for Bandpass Conversion
363(3)
11.2 System Overview
366(1)
11.3 Bandpass NTFs
367(5)
11.3.1 N-Path Transformation
368(4)
11.4 Architectures for Bandpass Delta-Sigma Modulators
372(8)
11.4.1 Topology Choices
372(3)
11.4.2 Resonator Implementations
375(5)
11.5 Bandpass Modulator Example
380(11)
11.5.1 LNA
382(1)
11.5.2 Attenuator
383(2)
11.5.3 Amplifiers
385(2)
11.5.4 Measurements
387(4)
11.6 Quadrature Signals
391(5)
11.6.1 Quadrature Mixing
391(1)
11.6.2 Quadrature Filters
392(4)
11.7 Quadrature Modulation
396(6)
11.8 Polyphase Signal Processing
402(2)
11.9 Conclusions
404(1)
References
405(2)
12 Incremental Analog-to-Digital Converters 407(18)
12.1 Motivation and Trade-Offs
407(1)
12.2 Analysis and Design of Single-Stage IADCs
408(3)
12.3 Digital Filter Design for Single-Stage IADCs
411(4)
12.4 Multiple-Stage IADCs and Extended Counting ADCs
415(1)
12.5 IADC Design Examples
416(6)
12.5.1 Third-Order Single-Bit IADC
416(4)
12.5.2 Two-Step IADC
420(2)
12.6 Conclusions
422(1)
References
423(2)
13 Delta-Sigma DACs 425(26)
13.1 System Architectures for Delta-Sigma DACs
425(2)
13.2 Loop Configurations for Delta-Sigma DACs
427(4)
13.2.1 Single-Stage Delta-Sigma Loops
428(1)
13.2.2 The Error-Feedback Structure
429(1)
13.2.3 Cascade (MASH) Structures
430(1)
13.3 Delta-Sigma DACs Using Multi-Bit Internal DACs
431(7)
13.3.1 Dual-Truncation DAC Structures
432(2)
13.3.2 Multi-bit Delta-Sigma DACs with Mismatch Error Shaping
434(2)
13.3.3 Digital Correction of Multi-Bit Delta-Sigma DACs
436(1)
13.3.4 Comparison of Single-Bit and Multi-Bit Delta-Sigma DACs
437(1)
13.4 Interpolation Filtering for Delta-Sigma DACs
438(3)
13.5 Analog Post-Filters for Delta-Sigma DACs
441(8)
13.5.1 Analog Post-Filtering in Single-Bit Delta-Sigma DACs
441(6)
13.5.2 Analog Post-Filtering in Multi-Bit Delta-Sigma DACs
447(2)
13.6 Conclusions
449(1)
References
449(2)
14 Interpolation and Decimation Filters 451(32)
14.1 Interpolation Filtering
452(4)
14.2 Example Interpolation Filter
456(5)
14.3 Decimation Filtering
461(2)
14.4 Example Decimation Filter
463(4)
14.5 Halfband Filters
467(4)
14.5.1 Saramaki Halfband Filter
469(2)
14.6 Decimation for Bandpass Delta-Sigma ADCs
471(1)
14.7 Fractional Rate Conversion
472(8)
14.7.1 Decimation by 1.5
472(3)
14.7.2 Sample-Rate Conversion
475(5)
14.8 Summary
480(1)
References
480(3)
A Spectral Estimation 483(16)
A.1 Windowing
484(4)
A.2 Scaling and Noise Bandwidth
488(3)
A.3 Averaging
491(2)
A.4 An Example
493(2)
A.5 Mathematical Background
495(3)
References
498(1)
B The Delta-Sigma Toolbox 499(40)
C Linear Periodically Time-Varying Systems 539(22)
C.1 Linearity and Time (In)variance
539(2)
C.2 Linear Time-Varying Systems
541(2)
C.3 Linear Periodically Time-Varying (LPTV) Systems
543(4)
C.4 LPTV Systems with Sampled Outputs
547(12)
C.4.1 Multiple Inputs
555(1)
C.4.2 Alias Rejection in Continuous-Time Delta-Sigma Modulators Revisited
556(3)
References
559(2)
Index 561
Shanthi Pavan is a Professor of electrical engineering at the Indian Institute of Technology, India, and has been the Editor-In-Chief of the IEEE Transactions on Circuits and Systems, and a Distinguished Lecturer of the IEEE Solid State Circuits Society.  He is a Fellow of the Indian National Academy of Engineering.

Richard Schreier was a Division Fellow in Analog Devices Inc. and an Adjunct Professor at the University of Toronto, Canada, when he retired in 2016. From 1991-1997 he was a Professor at Oregon State University.He was named an IEEE Fellow in 2015.

Gabor Temes is a Distinguished Professor Emeritus of the University of California, and Professor in the School of Electrical Engineering and Computer Science at Oregon State University, USA.  He is an IEEE Life Fellow and a member of the US National Academy of Engineering.
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