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E-raamat: Verilog HDL: Digital Design and Modeling [Taylor & Francis e-raamat]

(Santa Clara University, California, USA)
  • Formaat: 918 pages, 75 Tables, black and white; 796 Illustrations, black and white
  • Ilmumisaeg: 20-Feb-2007
  • Kirjastus: CRC Press Inc
  • ISBN-13: 9781315219547
  • Taylor & Francis e-raamat
  • Hind: 258,50 €*
  • * hind, mis tagab piiramatu üheaegsete kasutajate arvuga ligipääsu piiramatuks ajaks
  • Tavahind: 369,29 €
  • Säästad 30%
  • Formaat: 918 pages, 75 Tables, black and white; 796 Illustrations, black and white
  • Ilmumisaeg: 20-Feb-2007
  • Kirjastus: CRC Press Inc
  • ISBN-13: 9781315219547
Emphasizing the detailed design of various Verilog projects, Verilog HDL: Digital Design and Modeling offers students a firm foundation on the subject matter. The textbook presents the complete Verilog language by describing different modeling constructs supported by Verilog and by providing numerous design examples and problems in each chapter. Examples include counters of different moduli, half adders, full adders, a carry lookahead adder, array multipliers, different types of Moore and Mealy machines, and much more. The text also contains information on synchronous and asynchronous sequential machines, including pulse-mode asynchronous sequential machines.

In addition, it provides descriptions of the design module, the test bench module, the outputs obtained from the simulator, and the waveforms obtained from the simulator illustrating the complete functional operation of the design. Where applicable, a detailed review of the topic's theory is presented together with logic design principles, including state diagrams, Karnaugh maps, equations, and the logic diagram.

Verilog HDL: Digital Design and Modeling is a comprehensive, self-contained, and inclusive textbook that carries all designs through to completion, preparing students to thoroughly understand this popular hardware description language.
Preface xv
Introduction
1(6)
History of HDL
1(1)
Verilog HDL
2(1)
IEEE Standard
3(1)
Features
3(1)
Assertion Levels
3(4)
Overview
7(58)
Design Methodologies
7(2)
Modulo-16 Synchronous Counter
9(3)
Four-Bit Ripple Adder
12(3)
Modules and Ports
15(6)
Designing a Test Bench for Simulation
16(4)
Construct Definitions
20(1)
Introduction to Dataflow Modeling
21(5)
Two-Input Exclusive-OR Gate
22(2)
Four 2-Input And Gates with Delay
24(2)
Introduction to Behavioral Modeling
26(11)
Three-Input OR Gate
27(5)
Four-Bit Adder
32(2)
Modulo-16 Synchronous Counter
34(3)
Introduction to Structural Modeling
37(19)
Sum-of-Products Implementation
38(4)
Full Adder
42(6)
Four-Bit Ripple Adder
48(8)
Introduction to Mixed-Design Modeling
56(4)
Full Adder
56(4)
Problems
60(5)
Language Elements
65(52)
Comments
65(1)
Identifiers
66(1)
Keywords
67(29)
Bidirectional Gates
68(1)
Charge Storage Strengths
69(1)
CMOS Gates
70(1)
Combinational Logic Gates
70(6)
Continuous Assignment
76(1)
Data Types
77(1)
Module Declaration
78(1)
MOS Switches
79(1)
Multiway Branching
79(2)
Named Event
81(1)
Parameters
81(1)
Port Declaration
82(1)
Procedural Constructs
83(1)
Procedural Continuous Assignment
83(1)
Procedural Flow Control
84(4)
Pull Gates
88(1)
Signal Strengths
89(1)
Specify Block
90(1)
Tasks and Functions
91(1)
Three-State Gates
92(1)
Timing Control
93(2)
User-Defined Primitives
95(1)
Value Set
96(1)
Data Types
97(12)
Net Data Types
97(5)
Register Data Types
102(7)
Compiler Directives
109(3)
Problems
112(5)
Expressions
117(42)
Operands
117(9)
Constant
118(1)
Parameter
119(3)
Net
122(1)
Register
123(1)
Bit-Select
123(1)
Part-Select
124(1)
Memory Element
124(2)
Operators
126(30)
Arithmetic
127(3)
Logical
130(2)
Relational
132(2)
Equality
134(4)
Bitwise
138(5)
Reduction
143(4)
Shift
147(2)
Conditional
149(2)
Concatenation
151(3)
Replication
154(2)
Problems
156(3)
Gate-Level Modeling
159(68)
Multiple-Input Gates
159(25)
Gate Delays
184(19)
Inertial Delay
195(4)
Transport Delay
199(1)
Module Path Delay
200(3)
Additional Design Examples
203(20)
Iterative Networks
203(15)
Priority Encoder
218(5)
Problems
223(4)
User-Defined Primitives
227(70)
Defining a User-Defined Primitive
227(1)
Combinational User-Defined Primitives
228(37)
Map-Entered Variables
260(5)
Sequential User-Defined Primitives
265(26)
Level-Sensitive User-Defined Primitives
266(5)
Edge-Sensitive User-Defined Primitives
271(20)
Problems
291(6)
Dataflow Modeling
297(68)
Continuous Assignment
297(56)
Three-Input And Gate
298(3)
Sum of Products
301(3)
Reduction Operators
304(3)
Octal-to-Binary Encoder
307(4)
Four-to-One Multiplexer
311(4)
Four-to-One Multiplexer Using the Conditional Operator
315(3)
Four-Bit Adder
318(4)
Carry Lookahead Adder
322(6)
Asynchronous Sequential Machine
328(14)
Pulse-Mode Asynchronous Sequential Machine
342(11)
Implicit Continuous Assignment
353(1)
Delays
354(5)
Problems
359(6)
Behavioral Modeling
365(124)
Procedural Constructs
365(20)
Initial Statement
366(4)
Always Statement
370(15)
Procedural Assignments
385(19)
Intrastatement Delay
386(5)
Interstatement Delay
391(3)
Blocking Assignments
394(5)
Nonblocking Assignments
399(5)
Conditional Statements
404(20)
Case Statement
424(47)
Loop Statements
471(5)
For Loop
471(1)
While Loop
472(2)
Repeat Loop
474(1)
Forever Loop
475(1)
Block Statements
476(4)
Sequential Blocks
476(3)
Parallel Blocks
479(1)
Procedural Continuous Assignment
480(6)
Assign . . . Deassign
480(3)
Force . . . Release
483(3)
Problems
486(3)
Structural Modeling
489(92)
Module Instantiation
489(1)
Ports
490(5)
Unconnected Ports
493(1)
Port Connection Rules
494(1)
Design Examples
495(79)
Gray-to-Binary Code Converter
496(2)
Binary-Coded Decimal (BCD)-to-Decimal Decoder
498(7)
Modulo-10 Counter
505(7)
Adder/Subtractor
512(6)
Four-Function Arithmetic and Logic Unit (ALU)
518(8)
Adder and High-Speed Shifter
526(7)
Array Multiplier
533(8)
Moore-Mealy Synchronous Sequential Machine
541(6)
Moore Synchronous Sequential Machine
547(10)
Moore Asynchronous Sequential Machine
557(10)
Moore Pulse-Mode Asynchronous Sequential Machine
567(7)
Problems
574(7)
Tasks and Functions
581(20)
Tasks
581(8)
Task Declaration
582(1)
Task Invocation
582(7)
Functions
589(11)
Function Declaration
589(1)
Function Invocation
589(11)
Problems
600(1)
Additional Design Examples
601(154)
Johnson Counter
601(5)
Counter-Shifter
606(5)
Universal Shift Register
611(6)
Hamming Code Error Detection and Correction
617(14)
Booth Algorithm
631(11)
Moore Synchronous Sequential Machine
642(7)
Mealy Pulse-Mode Asynchronous Sequential Machine
649(8)
Mealy One-Hot Machine
657(12)
Binary-Coded Decimal (BCD) Adder/Subtractor
669(16)
BCD Addition
670(3)
BCD Subtraction
673(12)
Pipelined Reduced Instruction Set Computer (RISC) Processor
685(61)
Instruction Cache
701(5)
Instruction Unit
706(3)
Decode Unit
709(6)
Execution Unit
715(12)
Register File
727(8)
Data Cache
735(4)
RISC CPU Top
739(3)
System Top
742(4)
Problems
746(9)
Appendix A Event Queue
755(16)
Event Handling for Dataflow Assignments
755(5)
Event Handling for Blocking Assignments
760(3)
Event Handling for Nonblocking Assignments
763(4)
Event Handling for Mixed Blocking and Nonblocking Assignments
767(4)
Appendix B Verilog Project Procedure
771(2)
Appendix C Answers to Select Problems
773(118)
Overview
773(13)
Language Elements
786(3)
Expressions
789(7)
Gate Level Modeling
796(6)
User-Defined Primitives
802(13)
Dataflow Modeling
815(16)
Behavioral Modeling
831(12)
Structural Modeling
843(25)
Tasks and Functions
868(3)
Additional Design Examples
871(20)
Index 891


Santa Clara University, California, USA