Muutke küpsiste eelistusi

E-raamat: VLSI Architecture for Signal, Speech, and Image Processing: Advances, Challenges, and Potential [Taylor & Francis e-raamat]

Edited by (Zakir Husain Delhi College, University of Delhi, India), Edited by , Edited by , Edited by
  • Formaat: 320 pages, 45 Tables, black and white; 168 Line drawings, black and white; 6 Halftones, black and white; 174 Illustrations, black and white
  • Ilmumisaeg: 03-Nov-2022
  • Kirjastus: Apple Academic Press Inc.
  • ISBN-13: 9781003277538
  • Taylor & Francis e-raamat
  • Hind: 221,58 €*
  • * hind, mis tagab piiramatu üheaegsete kasutajate arvuga ligipääsu piiramatuks ajaks
  • Tavahind: 316,54 €
  • Säästad 30%
  • Formaat: 320 pages, 45 Tables, black and white; 168 Line drawings, black and white; 6 Halftones, black and white; 174 Illustrations, black and white
  • Ilmumisaeg: 03-Nov-2022
  • Kirjastus: Apple Academic Press Inc.
  • ISBN-13: 9781003277538
"This new volume introduces various VLSI (very-large-scale integration) architecture for DSP filters, speech filters, and image filters, detailing their key applications and discussing different aspects and technologies used in VLSI design, models and architectures, and more. The volume explores the major challenges with the aim to develop real-time hardware architecture designs that are compact and accurate. Knowledge of VLSI is necessary for understanding today's contemporary hardware prospects of engineering. It is the process of creating an integrated circuit by combining millions of MOS transistors onto a single chip that is needed for handheld portable battery-operated devices that require efficient, errorless, and low-power arithmetic operation. VLSI plays a most important role in the performance of digital systems, digital signal processing (DSP), image processing applications, hardware security, quantum computing, etc. Especially in DSP systems, the algorithms of VLSI have a number of interesting characteristics that can be exploited in the design of the arithmetic circuits so that they can be implemented more efficiently in terms of computation time, chip area, and power consumption. This volume, VLSI Architecture for Signal, Speech, and Image Processing, provides useful research in the field of computer arithmetic and can be applied for various arithmetic circuits, for their digital implementation schemes, and for performance considerations. It covers how computer arithmetic contributes to theera of quantum computing, hardware security, image processing, biomedical engineering, artificial intelligence, neural networks, and stochastic computing. Prepared by leading researchers in the field of computer arithmetic architecture, the state-of-the-art information presented here helps to provide a comprehensive understanding of VLSI for students, faculty, and researchers in computer science, computer engineering, and electrical and electronics engineering. It may be used as a textbook for courses onVLSI as well as a reference book"--

This new volume introduces various VLSI (very-large-scale integration) architecture for DSP filters, speech filters, and image filters, detailing their key applications and discussing different aspects and technologies used in VLSI design, models and architectures, and more. The volume explores the major challenges with the aim to develop real-time hardware architecture designs that are compact and accurate. It provides useful research in the field of computer arithmetic and can be applied for various arithmetic circuits, for their digital implementation schemes, and for performance considerations.



Introduces VLSI (very-large-scale integration) architecture for DSP filters, speech filters, and image filters, detailing the key uses and aspects and technologies used in VLSI design, models and architectures, and more. It explores the major challenges in developing real-time hardware architecture designs that are compact and accurate.

1. Evolution of 1-D, 2-D, and 3-D Lifting Discrete Wavelet Transform
VLSI Architecture
2. Execution of Lifting-Scheme Discrete Wavelet Transform
by Canonical Signed Digit Multiplier
3. Radix-8 Booth Multiplier in Terms of
Power and Area Efficient for Application in the Field of 2D DWT Architecture
4. Design and Performance Evaluation of Energy Efficient 8-Bit ALU at Ultra
Low Supply Voltages Using FinFET with 20nm Technology
5. Design and
Statistical Analysis of Strong Arbiter PUFs for Device Authentication and
Identification
6. An Impact of Aging on Arbiter Physical Unclonable Functions
7. Advanced Power Management Methodology for SoCs Using UPF
8. Architecture
Design: Network-on-Chip
9. Routing Strategy: Network-on-Chip Architectures
10. Self-Driven Clock Gating Technique for Dynamic Power Reduction of
High-Speed Complex Systems
11. Optimization of SOC Sub-Circuits Using
Mathematical Modeling
12. An Efficient Design of D Flip Flop in Quantum-Dot
Cellular Automata (QCA) for Sequential Circuits
13. Design and Performance
Analysis of Digitally Controlled DC-DC Converter
Durgesh Nandan, PhD, is a Research Mentor and Account Manager at Accendere Knowledge Management Services Pvt. Ltd. He formerly served as Head of the Department of Electronics and Communication Engineering, IASSCOM Fortune Institutes of Technology, India. He is a session chair, technical program committee chair, reviewer, and member of more than 50 national and international conferences. He is the author or a co-author of more than 90 papers and the author/co-author of two books.

Basant Kumar Mohanty, PhD, is Professor and Associate Dean (Research) at the Mukesh Patel School of Technology, Management and Engineering at the Narsee Moonjee Institute of Management Studies, Mumbai, India. He is also an Associate Editor for the Journal of Circuits, Systems, and Signal Processing and a senior member of IEEE Circuits and System Society. He has published over 60 technical papers and conference proceedings and has collaborated on research with faculties of top technical universities.

Sanjeev Kumar, PhD, is a Research Mentor at CL Educate Ltd., India. He was formerly affiliated with TIT Group of Institutes, India, and the Oriental Group of Institutes, Bhopal, India. He was also a project fellow at the Division of MMIC in the Defence Research and Development Organisation, Delhi, India. He acts as technical program chair, reviewer, and member of more than 40 refereed national/international conferences. He is the author or a co-author of more than 65 papers in international journals and conference proceedings.

Rajeev Kumar Arya, PhD, is Assistant Professor of Electronics and Communication Engineering at the National Institute of Technology, Patna, India. He was formerly affiliated with CMR Engineering College, Hyderabad, India. He serves as a guest editor of the International Journal of Information Technology and Web Engineering and the International Journal of Computational Systems Engineering and is a reviewer for IEEE Communication Letter and other journals.