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E-raamat: VLSI Circuits and Embedded Systems [Taylor & Francis e-raamat]

  • Formaat: 464 pages, 49 Tables, black and white; 244 Line drawings, black and white; 30 Halftones, black and white; 274 Illustrations, black and white
  • Ilmumisaeg: 29-Jul-2022
  • Kirjastus: CRC Press
  • ISBN-13: 9781003269182
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VLSI Circuits and Embedded SystemsSuurem pilt
  • Formaat: 464 pages, 49 Tables, black and white; 244 Line drawings, black and white; 30 Halftones, black and white; 274 Illustrations, black and white
  • Ilmumisaeg: 29-Jul-2022
  • Kirjastus: CRC Press
  • ISBN-13: 9781003269182
Teised raamatud teemal:
Taylor & Francis e-raamatudRohkem infot Taylor & Francis e-raamatute kohta
Raamatu kodulehekülg: https://www.taylorfrancis.com/books/9781003269182
Very Large-Scale Integration (VLSI) creates an integrated circuit (IC) by combining thousands of transistors into a single chip. While designing a circuit, reduction of power consumption is a great challenge. VLSI designs reduce the size of circuits which eventually reduces the power consumption of the devices. However, it increases the complexity of the digital system. Therefore, computer-aided design tools are introduced into hardware design processes.

Unlike the general-purpose computer, an embedded system is engineered to manage a wide range of processing tasks. Single or multiple processing cores manage embedded systems in the form of microcontrollers, digital signal processors, field-programmable gate arrays, and application-specific integrated circuits. Security threats have become a significant issue since most embedded systems lack security even more than personal computers. Many embedded systems hacking tools are readily available on the internet. Hacking in the PDAs and modems is a pervasive example of embedded systems hacking.

This book explores the designs of VLSI circuits and embedded systems. These two vast topics are divided into four parts. In the book's first part, the Decision Diagrams (DD) have been covered. DDs have extensively used Computer-Aided Design (CAD) software to synthesize circuits and formal verification. The book's second part mainly covers the design architectures of Multiple-Valued Logic (MVL) Circuits. MVL circuits offer several potential opportunities to improve present VLSI circuit designs. The book's third part deals with Programmable Logic Devices (PLD). PLDs can be programmed to incorporate a complex logic function within a single IC for VLSI circuits and Embedded Systems. The fourth part of the book concentrates on the design architectures of Complex Digital Circuits of Embedded Systems. As a whole, from this book, core researchers, academicians, and students will get the complete picture of VLSI Circuits and Embedded Systems and their applications.
List of Figures
xxi
List of Tables
xxxi
Preface xxxiii
Author Bio xxxv
Acknowledgments xxxvii
Acronyms xxxix
Introduction xliii
Introduction xliii
Section I An Overview About Decision Diagrams
Part 1
3(82)
Chapter 1 Shared Multi-Terminal Binary Decision Diagrams
5(14)
1.1 Introduction
5(1)
1.2 Preliminaries
6(6)
1.2.1 Shared Multi-Terminal Binary Decisi6n Diagrams
8(4)
1.3 An Optimization Algorithm For Smtbdd (k)S
12(4)
1.3.1 The Weight Calculation Procedure
13(2)
1.3.2 Optimization of SMTBDD(3)s
15(1)
1.4 Summary
16(3)
Chapter 2 Multiple-Output Functions
19(16)
2.1 Introduction
19(2)
2.1.1 Basic Definitions
20(1)
2.2 Binary Decision Diagrams For Multiple-Output Functions
21(5)
2.2.1 SBDDs and MTBDDs
21(1)
2.2.2 BDDs for CFs
21(1)
2.2.2.1 BDDs for CFs of Multiple-Output Functions
22(4)
2.2.3 Comparison of Various BDDs
26(1)
2.3 Construction Of Compact BDDS For CFS
26(5)
2.3.1 Formulation of the Problem
26(1)
2.3.2 Ordering of Output Variables
27(1)
2.3.3 Interleaving-Based Sampling Schemes for Ordering of Input Variables
28(1)
2.3.3.1 Generating Samples from Output Functions
28(1)
2.3.3.2 Interleaving the Variable Orderings of Samples
29(1)
2.3.4 Interleaving Method for Input Variables and Output Variables
29(1)
2.3.5 Algorithm for Ordering the Variables
30(1)
2.4 Summary
31(4)
Chapter 3 Shared Multiple-Valued DDs for Multiple-Output Functions
35(12)
3.1 Introduction
35(1)
3.2 Decision Diagrams
36(3)
3.2.1 Binary Decision Diagrams
37(1)
3.2.2 Multiple-Valued Decision Diagrams
37(1)
3.2.2.1 Shared Multiple-Valued Decision Diagrams
37(2)
3.3 Construction Of Compact SMDDS
39(5)
3.3.1 Pairing of Binary Input Variables
39(1)
3.3.1.1 The Method
39(4)
3.3.2 Ordering of Input Variables
43(1)
3.4 Summary
44(3)
Chapter 4 Heuristics to Minimize Multiple-Valued Decision Diagrams
47(14)
4.1 Introduction
47(2)
4.2 Basic Properties
49(1)
4.3 Multiple-Valued Decision Diagrams
49(5)
4.3.1 Size of MDDs
49(5)
4.4 Minimization Of Mdds
54(4)
4.4.1 Pairing of 2-Valued Inputs
55(1)
4.4.2 Ordering of Multiple-Valued Variables
55(3)
4.5 Summary
58(3)
Chapter 5 TDM Realizations of Multiple-Output Functions
61(12)
5.1 Introduction
61(1)
5.2 Decision Diagrams For Multiple-Output Functions
62(3)
5.2.1 Shared Binary Decision Diagrams
62(1)
5.2.2 Shared Multiple-Valued Decision Diagrams
63(1)
5.2.3 Shared Multi-Terminal Multiple-Valued Decision Diagrams
63(2)
5.3 TDM Realizations
65(4)
5.3.1 TDM Realizations Based on SBDDs
65(1)
5.3.2 TDM Realizations Based on SMDDs
66(2)
5.3.3 TDM Realizations Based on SMTMDDs
68(1)
5.3.4 Comparison of TDM Realizations
68(1)
5.4 Reduction Of Smtmdds
69(1)
5.5 Upper Bounds On The Sizen Of DDS
70(1)
5.6 Summary
70(3)
Chapter 6 Multiple-Output Switching Functions
73(12)
6.1 Introduction
73(2)
6.2 Definitions And Basic Properties
75(1)
6.3 Decision Diagrams
76(1)
6.3.1 2-Valued Pseudo-Kronecker Decision Diagrams
76(1)
6.3.2 Multiple-Valued Pseudo-Kronecker Decision Diagrams
77(1)
6.4 Optimization Of 4-Valued Pkdds
77(5)
6.4.1 Pairing of 2-Valued Input Variables
77(2)
6.4.2 Ordering of 4-Valued Variables
79(2)
6.4.3 Selection of Expansions
81(1)
6.5 Summary
82(3)
Section II An Overview About Design Architectures of Multiple-Valued Circuits
Part 2
85(60)
Chapter 7 Multiple-Valued Flip-Flops Using Pass Transistor Logic
87(10)
7.1 Introduction
87(3)
7.1.1 Realization of Multiple Valued Flip-Flops Using Pass Transistor Logic
87(1)
7.1.2 Implementation of MVFF with Binary Coding and Decoding Using PTL
88(2)
7.2 MVFF Without Binary Encoding Or Decoding
90(5)
7.2.1 Properties of Pass Transistor and a Threshold Gate
90(2)
7.2.2 Realization of Multiple-Valued Inverter Using Threshold Gates
92(1)
7.2.3 Realization MVFF Using Multiple-Valued Pass Transistor Logic
93(2)
7.3 Summary
95(2)
Chapter 8 Voltage-Mode Pass Transistor-Based Multi-Valued Multiple-Output Logic Circuits
97(10)
8.1 Introduction
97(1)
8.2 Basic Definitions And Terminologies
98(1)
8.3 The Method
98(7)
8.3.1 Conversion of Binary Logic Functions into MVL Functions
99(1)
8.3.2 Pairing of the Functions
100(1)
8.3.3 Output Stage
101(1)
8.3.4 Basic Circuit Structure and Operation
101(3)
8.3.4.1 Literal Generation
104(1)
8.4 Summary
105(2)
Chapter 9 Multiple-Valued Input Binary-Valued Output Functions
107(14)
9.1 Introduction
107(1)
9.2 Basic Definitions
108(2)
9.3 Transformation Of Two-Valued Variables Into Multiple-Valued Variables
110(9)
9.3.1 Algorithms for Minimizing the Multiple-Valued Functions
112(7)
9.4 Summary
119(2)
Chapter 10 Digital Fuzzy Operations Using Multi-Valued Fredkin Gates
121(12)
10.1 Introduction
121(1)
10.2 Reversible Logic
122(2)
10.2.1 Some Basic Reversible Gates and Classical Digital Logic Using these Gates
122(2)
10.2.2 Multi-Valued Fredkin Gate
124(1)
10.3 Fuzzy Sets And Relation
124(4)
10.4 The Circuit
128(2)
10.4.1 Fuzzy Operations Using MVFG
128(2)
10.4.2 Systolic Array Structure for Composition of Fuzzy Relations
130(1)
10.5 Summary
130(3)
Chapter 11 Multiple-Valued Multiple-Output Logic Expressions Using LUT
133(12)
11.1 Introduction
133(1)
11.2 Basic Definitions And Properties
134(1)
11.2.1 Product Terms
134(1)
11.2.1.1 Prime Implicants
134(1)
11.2.2 Minimal Sops
134(1)
11.2.3 Mvsop Expressions Using KC
134(1)
11.3 The Method
135(2)
11.3.1 Support Set Matrix
135(1)
11.3.2 Pair Support Matrix
136(1)
11.4 The Algorithm For Minimization Of Mvmofs Using KC
137(1)
11.5 Realization Of Mvmofs Using Current Mode Cmos
138(3)
11.6 Summary
141(4)
Section III An Overview About Programmable Logic Devices
Part 3
145(178)
Chapter 12 Lut-Based Matrix Multiplication Using Neural Networks
149(8)
12.1 Introduction
149(1)
12.2 Basic Definitions
150(1)
12.3 The Method
150(5)
12.4 Summary
155(2)
Chapter 13 Easily Testable Plas Using Pass Transistor Logic
157(6)
13.1 Introduction
157(1)
13.2 Product Line Grouping
157(1)
13.3 The Design
158(2)
13.4 The Technique For Product Line Grouping
160(1)
13.5 Summary
161(2)
Chapter 14 Genetic Algorithm For Input Assignment For Decoded-Plas
163(22)
14.1 Introduction To Decoders
163(3)
14.1.1 Decoders As Product Generators
165(1)
14.2 Decoded Pla
166(3)
14.2.1 Advantages
168(1)
14.3 Basic Definitions
169(1)
14.4 Genetic Algorithm
170(5)
14.4.1 Ga Terminology
171(1)
14.4.2 The Simple Ga
172(1)
14.4.3 The Steady-State Genetic Algorithm
172(3)
14.5 Genetic Operators
175(1)
14.5.1 Selection
175(1)
14.6 Crossover
176(3)
14.6.1 Mutation
177(1)
14.6.2 Inversion
178(1)
14.7 Ga For Decoded-Plas
179(3)
14.7.1 Problem Encoding
179(1)
14.7.2 Fitness Function
180(1)
14.7.3 Developed Ga
181(1)
14.7.4 Decoded And-Exor Pla Implementation
181(1)
14.8 Summary
182(3)
Chapter 15 Fpga-Based Multiplier Using Lut Merging Theorem
185(12)
15.1 Introduction
185(1)
15.2 Lut Merging Theorem
186(1)
15.3 The Multiplier Circuit Using The Lut Merging Theorem
186(8)
15.4 Summary
194(3)
Chapter 16 Look-Up Table-Based Binary Coded Decimal Adder
197(10)
16.1 Introduction
197(1)
16.2 The Design Of Lut-Based Bcd Adder
197(8)
16.2.1 Parallel Bcd Addition Method
198(4)
16.2.2 Parallel Bcd Adder Circuit Using Lut
202(3)
16.3 Summary
205(2)
Chapter 17 Place And Route Algorithm For Field Programmable Gate Array
207(6)
17.1 Introduction
207(1)
17.2 Placing And Routing
208(1)
17.3 Partitioning Algorithm
208(1)
17.4 Kernighan-Lin Algorithm
208(3)
17.4.1 How K-L Works
209(1)
17.4.2 Implementation Of K-L Algorithm
209(1)
17.4.3 Steps Of Algorithm
210(1)
17.5 Summary
211(2)
Chapter 18 Lut-Based Bcd Multiplier Design
213(20)
18.1 Introduction
213(2)
18.2 Basic Properties
215(3)
18.3 The Algorithm
218(7)
18.3.1 The Bcd Multiplication Method
219(2)
18.3.2 The Lut Architecture
221(4)
18.4 Lut-Based Bcd Multiplier Circuit
225(6)
18.5 Summary
231(2)
Chapter 19 Lut-Based Matrix Multiplier Circuit Using Pigeonhole Principle
233(54)
19.1 Introduction
233(4)
19.2 Basic Definitions
237(15)
19.2.1 Binary Multiplication
237(1)
19.2.2 Matrix Multiplication
238(2)
19.2.3 Bcd Coding
240(1)
19.2.4 Bcd Addition
240(1)
19.2.5 Binary To Bcd Conversion
240(3)
19.2.6 Pigeonhole Principle
243(1)
19.2.7 Field Programmable Gate Arrays
243(1)
19.2.8 Look-Up Table
244(1)
19.2.9 Lut-Based Adder
245(2)
19.2.10 Bcd Adder
247(1)
19.2.11 Comparator
248(1)
19.2.12 Shift Register
249(2)
19.2.13 Literal Cost
251(1)
19.2.14 Gate Input Cost
251(1)
19.2.15 Xilinx Virtex 6 Fpga Slice
251(1)
19.3 The Matrix Multiplier
252(30)
19.3.1 The Efficient Matrix Multiplication Method
252(1)
19.3.1.1 The (1 × 1)-Digit Multiplication Algorithm
253(2)
19.3.1.2 The (Mxn)-Digit Multiplication Algorithm Using The (1 × 1)-Digit Multiplication Algorithm
255(3)
19.3.1.3 Binary To Bcd Conversion Algorithm
258(8)
19.3.1.4 Efficiency Of The (Mxw)-Digit Multiplication Algorithm
266(2)
19.3.2 The Matrix Multiplication Algorithm
268(4)
19.3.3 The Cost-Efficient Matrix Multiplier Circuit
272(1)
19.3.3.1 (1 × 1)-Digit Multiplier Circuit
272(7)
19.3.3.2 Binary To Bcd Converter Circuit For The Decimal Multiplier
279(1)
19.3.3.3 (Mxn)-Digit Multiplier Circuit
279(1)
19.3.3.4 Matrix Multiplier Circuit
280(2)
19.4 Summary
282(5)
Chapter 20 Bcd Adder Using A Lut-Based Field Programmable Gate Array
287(12)
20.1 Introduction
287(1)
20.2 BCD Adder Using Luts
288(7)
20.2.1 The BCD Addition Method
288(2)
20.2.2 The Architecture Of A Lut
290(4)
20.2.2.1 Working Mechanism Of The 2-Input Lut
294(1)
20.3 BCD Adder Circuit Using Luts
295(2)
20.4 Summary
297(2)
Chapter 21 Generic Complex Programmable Logic Device Board
299(12)
21.1 Introduction
299(1)
21.2 Hardware Design And Development
300(2)
21.2.1 Dc-Dc Converters
302(1)
21.2.2 JTAG Interface
302(1)
21.23 Led Interface
302(3)
21.2.4 Clock Circuit
302(1)
21.2.5 Cpld
303(2)
21.2.6 Seven-Segment Display
305(1)
21.2.7 Input/Output Connectors
305(1)
21.3 Internal Hardware Design Of Cpld
305(4)
21.3.1 A5/1 Algorithm
306(1)
21.3.2 Seven Segment Display Driver
306(1)
21.3.3 Binary 8-Bit Counter
307(2)
21.4 Applications
309(1)
21.5 Summary
309(2)
Chapter 22 Fpga-Based Programmable Logic Controller
311(12)
22.1 Introduction
311(1)
22.2 Fpga Technology For Plc
312(1)
22.3 System Design Procedure For Plc
313(2)
22.3.1 Ladder Program Structure
313(1)
22.3.2 Operating Modes Of Plc
314(1)
22.3.3 Ladder Scanning
314(1)
22.3.4 Ladder Execution
314(1)
22.3.5 System Implementation
315(1)
22.4 Design Considerations
315(3)
22.5 Summary
318(5)
Section IV An Overview About Design Architectures Of Digital Circuits
Part 4
323(134)
Chapter 23 Parallel Computation Of Quotients And Partial Remainders To Design Divider Circuits
325(64)
23.1 Introduction
325(6)
23.2 Basic Definitions
331(13)
23.2.1 Division Operation
331(1)
23.2.2 Shift Registers
331(1)
23.2.2.1 Serial-In To Parallel-Out Shift Register
332(2)
23.2.2.2 Serial-In To Serial-Out Shift Register
334(1)
23.2.2.3 Parallel-In Serial-Out Register
335(1)
23.2.2.4 Parallel-In To Parallel-Out Shift Register
336(1)
23.2.3 Complement Logic
336(1)
23.2.4 Comparator
337(1)
23.2.5 Adder
338(1)
23.2.6 Subtractor
339(2)
23.2.7 Look-Up Table
341(1)
23.2.8 Counter Circuit
342(2)
23.2.9 Reversible And Fault Tolerance Logic
344(1)
23.3 The Methodologies
344(41)
23.3.1 Division Algorithm
344(3)
23.3.1.1 Explanation Of Correctness Of The Division Algorithm
347(2)
23.3.2 Asic-Based Circuits
349(1)
23.3.2.1 Parallel W-Bit Counter Circuit
350(5)
23.3.2.2 N-Bit Comparator
355(4)
23.3.2.3 N-Bit Selection Block
359(5)
23.3.2.4 Circuit For Conversion To Zero
364(6)
23.3.2.5 Design Of The Divider Circuit
370(3)
23.3.3 Lut-Based Circuits
373(2)
23.3.3.1 Lut-Based Bit Counter Circuit
375(1)
23.3.3.2 Lut-Based Bit Comparator Circuit
376(3)
23.3.3.3 Lut-Based Selection Circuit
379(1)
23.3.3.4 Lut-Based Converter Circuit
380(2)
23.3.3.5 Design Of The Lut-Based Divider Circuit
382(1)
23.3.3.6 Reversible Fault Tolerant Lut-Based Divider Circuit
383(2)
23.4 Summary
385(4)
Chapter 24 Synthesis Of Boolean Functions Using Tant Networks
389(8)
24.1 Introduction
389(1)
24.2 Tant Minimization
389(2)
24.2.1 The Technique
390(1)
24.3 The Introduced Method Of Tant Minimization
391(3)
24.4 Algorithms Used In Different Stages
394(2)
24.5 Summary
396(1)
Chapter 25 Asymmetric High Radix Signed Digital Adder Using Neural Networks
397(6)
25.0.1 Introduction
397(1)
25.1 Basic Definitions
398(2)
25.1.1 Neural Network
398(1)
25.1.2 Asymmetric Number System
398(1)
25.1.3 Binary To Asymmetric Number System Conversion
399(1)
25.1.4 Addition Of Ahsd4 Number System
400(1)
25.2 The Design Of Adder Using Neural Network
400(1)
25.3 Ahsd Addition For Radix-5
401(1)
25.4 Summary
401(2)
Chapter 26 Wrapper/Tam Co-Optimization And Constrained Test Scheduling
403(10)
26.1 Introduction
403(1)
26.2 The Wrapper Design
404(2)
26.3 Tam Design And Test Scheduling
406(1)
26.4 Power Constrained Test Scheduling
407(4)
26.4.1 Data Structure
409(1)
26.4.2 Rectangle Construction
409(1)
26.4.3 Diagonal Length Calculation
410(1)
26.4.4 Tam Assignment
410(1)
26.5 Summary
411(2)
Chapter 27 Static Random Access Memory Using Memristor
413(10)
27.1 Introduction
413(2)
27.2 Memristor Characterization
415(1)
27.3 Memristor As A Switch
416(1)
27.4 Working Principle Of Memristor
417(1)
27.5 Memristor-Based Sram
418(2)
27.6 Summary
420(3)
Chapter 28 A Fault Tolerant Approach To Microprocessor Design
423(14)
28.1 Introduction
423(3)
28.1.1 Design Faults
423(1)
28.1.2 Manufacturing Defects
424(1)
28.1.3 Operational Faults
424(2)
28.2 Dynamic Verification
426(4)
28.2.1 System Architecture
426(2)
28.2.2 Checker Processor Architecture
428(2)
28.3 Physical Design
430(1)
28.4 Design Improvements For Additional Fault Coverage
431(4)
28.4.1 Operational Errors
431(1)
28.4.2 Manufacturing Errors
432(3)
28.5 Summary
435(2)
Chapter 29 Applications Of VLSI Circuits And Embedded Systems
437(20)
29.1 Applications Of VLSI Circuits
438(10)
29.1.1 Autonomous Robots In Industrial Plants
438(1)
29.1.2 Machines In Manufacturing
439(1)
29.1.3 Smart Vision Tech For Quality Control
440(2)
29.1.4 Wearables: Ensuring Security
442(1)
29.1.5 Computing Using The Cpu
442(1)
29.1.6 System On A Chip
443(1)
29.1.7 Cutting Edge Ai Handling
444(1)
29.1.8 VLSI In 5G Networks
445(1)
29.1.9 Fuzzy Logic And Decision Diagrams
445(3)
29.2 Application Of Embedded Systems
448(5)
29.2.1 Embedded System For Street Light Control
448(1)
29.2.2 Embedded System For Industrial Temperature Control
448(1)
29.2.3 Embedded System For Traffic Signal Control
448(1)
29.2.4 Embedded System For Vehicle Tracking
448(1)
29.2.5 Embedded System For War Field Spying Robot
448(1)
29.2.6 Automated Vending Machine
449(1)
29.2.7 Mechanical Arm Regulator
449(1)
29.2.8 Routers And Switches
449(1)
29.2.9 Industrial Field Programmable Gate Arrays
450(2)
29.2.10 Industrial Programmable Logic Circuits
452(1)
29.3 SUMMARY
453(4)
VLSI Circuits and Embedded Systems 457(4)
Index 461
Professor Dr. Hafiz Md. Hasan Babu is currently working as a Professor in the Department of Computer Science and Engineering, University of Dhaka, Bangladesh. He is also the former Chairman of the same department. Recently, he has completed his tenured as Pro-Vice-Chancellor of National University, Bangladesh, where he was on deputation from the Department of Computer Science and Engineering, University of Dhaka, Bangladesh. For his excellent academic and administrative capability, he also served as the Professor and founding Chairman of the Department of Robotics and Mechatronics Engineering, University of Dhaka, Bangladesh. He served as a World Bank Senior Consultant and General Manager of the Department of the Information Technology & the Department of Management Information Systems of Janata Bank Limited, Bangladesh. Dr. Hasan Babu was the World Bank Resident Information Technology Expert of the Supreme Court Project Implementation Committee, Supreme Court of Bangladesh. He was also the Information Technology Consultant of Health Economics Unit and the Ministry of Health and Family Welfare in the project "SSK (Shasthyo Shurokhsha Karmasuchi) and Social Health Protection Scheme" under the direct supervision and funding of German Financial Cooperation through KfW.
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