In these proceedings from the July 2005 conference, participants face the challenges of new nanotechnologies and their associated field failures, new questions about data and installation security, and the ever-shrinking time to market. General topics include transient fault modeling and analysis, hardening techniques for transient faults, SUE effects in FPGAs, robust design techniques for soft errors, simulation and mitigation of single event effects, self-calibrating design, on-line testing for secure and asynchronous chips, self-checking strategies, process variations, leakage, power supply noise detection and tolerance, testing issues, self-testing and fault tolerance, multiple bit upset evaluation and correction. Issues of timing, yield and reliability and mitigating soft errors to prevent a hard threat. These proceedings include the poster session. Annotation ©2005 Book News, Inc., Portland, OR (booknews.com)
