Seventy-four papers presented at the November 2004 symposium discuss advanced design for testability techniques for test cost reduction, system-on-a-chip test integration, and the diagnosis and repair of embedded digital, analog, and memory components. The researchers explore low power, cross-talk, functional, memory, analog, FPGA, delay, and built-in testing. Topics include multiple scan tree design with test vector modification, high level fault injection for attack simulation in smart cards, efficient test methodologies for conditional sum adders, and methods for completing fault-tolerant Hopfield neural networks functioning as associative memories. No subject index is provided in the book, but the CD-ROM is searchable. Annotation ©2004 Book News, Inc., Portland, OR (booknews.com)
