| Impact of New Materials, Changes in Physics and Continued ULSI Scaling on Failure Mechanisms and Analysis |
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1 | (9) |
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Session 1: Failure Analysis Techniques I |
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Invited Paper Can Failure Analysis Keep Peace with IC Technology Development? |
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9 | (6) |
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Laser Voltage Probe (LVP): A Novel Optical Probing Technology for Flip-Chip Packaged Microprocessors |
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15 | (6) |
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Session 2: Process and Device |
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Influence of Passivation Anneal Position on Metal Coverage Dependent Mismatch and Hot Carrier Reliability |
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21 | (4) |
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The Effect of Nitrogen Pre-Annealing on the Sidewall Oxidation of WSix and on the Related Electrical Properties of WSix/Poly Si Gate Structure |
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25 | (5) |
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Radiation-Induced Leakage Current of Ultra-thin Gate Oxide Under X-ray Lithography Conditions |
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30 | (4) |
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Excellent Quality Ultra-Thin Oxides Prepared by Room Temperature Anodic Oxidation |
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34 | (5) |
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Session 3: Packaging and Metallization I |
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Impact of Test Structure Design on Electromigration of Metal Interconnect |
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39 | (5) |
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Impact of Voids in Ti-Salicided p+ Polysilicon Lines on TiSi2 Electrical Properties |
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44 | (6) |
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Detection of Underfill Epoxy Defects in Flip Chip Packages with the Aid of SAM, Parallel Polishing & FIB |
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50 | (5) |
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Monte Carlo Simulation of Electromigration in Polycrystalline Metal Stripes |
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55 | (5) |
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Impact of Intermetal Dielectric Process on Al Via Electromigration Reliability |
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60 | (4) |
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Session 4: Failure Analysis Techniques II |
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Failure Analysis of μBGA - New Approaches in Fault Isolation |
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64 | (5) |
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New FIB-Supported Approaches for EELS-Capable TEM-Lamella Preparation |
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69 | (4) |
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Illumination-Sensitive Failure Mechanism - A Case Study on Transient Icc Failure |
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73 | (4) |
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Origin of the Substrate Current After Soft-Breakdown in Thin Oxide n-MOSFETs |
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77 | (4) |
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A Study of Quasi-Breakdown Mechanism in Ultra-Thin Gate Oxide by Using DCIV Technique |
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81 | (4) |
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A Detailed Analysis of the Pre-Breakdown Current Fluctuations in Thin Oxide MOS Capacitors |
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85 | (4) |
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A New DC Voltage-Voltage Method to Measure the Interface Traps in Deep Sub-Micron MOS Transistors |
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89 | (5) |
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Channel-Width Effect on Hot-Carrier Degradation in NMOSFETs with Recessed-LOCOS Isolation Structures |
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94 | (5) |
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Series Resistance and Effective Channel Mobility Degradation in LDD NMOSFETs Under Hot-Carrier Stressing |
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99 | (5) |
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Session 7: Failure Analysis Techniques III |
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Automatic DRAM Cell Location in the SEM |
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104 | (4) |
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Characterization and Application of Highly-Sensitive Infra-Red Emission Microscopy for Microprocessor Backside Failure Analysis |
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108 | (5) |
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An Integrated (Automated) Photon Emission Microscope and MOSFET Characterization System for Combined Microscopic and Macroscopic Device Analysis |
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113 | (6) |
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Novel Backside Sample Preparation Processes for Advanced CMOS Integrated Circuits Failure Analysis |
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119 | (4) |
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Session 8: Packaging and Metallization II |
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Impact of Failure Criteria on Electromigration of W-plug Contact |
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123 | (5) |
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Identification of Processing Defects by Focused Ion Beam (FIB) Induced Voltage Contrast |
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128 | (4) |
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Long Term Noise Measurements to Characterize Electromigration in Metal Lines of ICs |
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132 | (4) |
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Session 9: Dielectrics II |
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An Empirical Breakdown Model of the Gate Oxide Under Current Stress |
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136 | (4) |
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A Comparison of Interface Trap Generation by Fowler-Nordheim Electron Injection and Hot-Hole Injection Using the DCIV Method |
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140 | (5) |
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The Electric Field, Oxide Thickness, Time and Fluence Dependences of Trap Generation in Silicon Oxides and Their Support of the E-Model of Oxide Breakdown |
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145 | (6) |
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Session 10: EOS/ESD and Latchup |
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A Novel Dual-Direction IC ESD Protection Device |
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151 | (5) |
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Latent Damage Investigation on Lateral Non-Uniform Charge Generation and Stress-Induced Leakage Current in Silicon Dioxides Subjected to Low-Level Electrostatic Discharge Impulse Stressing |
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156 | (6) |
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An Analytical Model of Positive H.B.M. ESD Current Distribution and the Modified Multi-Finger Protection Structure |
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162 | (6) |
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A Latch-up Immunized Lateral Trench-Gate Conductivity Modulated Power Transistor |
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168 | (5) |
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Session 11: Physical Analysis and Reliability of Specialist Devices |
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Invited Paper Physical Analysis and Modeling of the Reliability of AlGaAs/GaAs HBTs |
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173 | (7) |
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Study on LED Degradation Using CL, EBIC and a Two-Diode Parameter Extraction Model |
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180 | (5) |
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Temperature Distribution in Power GaAs Field Effect Transistors Using Spatially Resolved Photoluminescence Mapping |
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185 | (6) |
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Analysis of Surface-State Effects on Gate-Lag Phenomena in Recessed-Gate and Buried-Gate GaAs MESFETs |
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191 | (4) |
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Session 12: Hot-Carrier II |
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Low-Voltage Forward Gated Diode: An Early Monitor of Hot-Carrier Degradations in Scaled MOSFETs |
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195 | (5) |
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A Comparative Study of Charge Trapping Effects in LDD Surface-Channel and Buried-Channel PMOS Transistors Using Charge Profiling and Threshold Voltage Shift Measurements |
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200 | (6) |
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Energy Dependence of Interface Trap Density - Investigated by the DCIV Method |
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206 | |
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