A final report on the IEEE International Integrated Reliability Workshop 2000. It covers: water level; reliability; test and test approaches; identification of reliability; effects; characterization and prediction; models to show; reliability test structures; designing in reliability; and more.
Foreword vi Keynote Abstract: Defect Generation and Reliability of Ultra-thin SiO2 at Low Voltage viii D.J. DiMaria J.H. Stathis PLATFORM TECHNICAL PRESENTATIONS Deep-Censoring Method For Early Reliability Assessment 1(8) H.A. Schafft L.M. Head J.A. Lechner J.P. Gill T.D. Sullivan Analysis & Optimization of Stress Conditions for Gate Oxide Wearout Using Monte Carlo Simulation 9(5) R.P. Vollersten A. Strong Design Rule Limitations Due to Hot Carrier Degradation of NMOS Transistor Under DC Stress 14(6) D. Regis C. Dekeukeleire W. Vanderbauwhede A. Demesmaeker A. Pergoot On the Methodology of Assessing Hot-Carrier Reliability of Analog Circuits 20(4) H. Le P.J. Marcoux W. Jiang J.E. Chung Fast-bit-limited Lifetime Modeling of Advanced Floating Gate Non-volatile Memories 24(5) A. Scarpa G. Tao J. Dijkstra F.G. Kuper Reliability Studies on Sub 100 nm SOI-MNSFETs 29(3) S. Mahapatra V.R. Rao J. Vasi B. Cheng J.C.S. Woo Fault-Tolerant Approaches Based on Evolvable Hardware & Using Reconfigurable Electronic Devices 32(8) D. Keymeulen A. Stoica R. Zebulum Y. Jin V. Duong Plasma-Induced-Damage (PID) Free 29A Nitrided Gate Oxide of 130 nm CMOS Devices for High Performance Microprocessor Manufacturing 40(5) G. Klein H. Nariman D. Wu J. Tao B. Bandyopadhyay D. Wristers E. Ibok M. McBride J. Tsiang D.H. Ju P. Fang Quasi-Breakdown in Ultra-thin Oxides: Some Insights on the Physical Mechanisms 45(6) S. Bruyere D. Roy E. Vincent G. Ghibaudo Soft Breakdown Model of 20 A Gate Oxide 51(3) C.-Y. Ko R.Y. Shiue J. Yue Gate Reliability Comparison of 110 & 100 Substrates 54(3) A. Strong E. Wu H. Tews D. Tibel R. Malik O. Cain Electromigration Testing on Via Line Structures with a SWEAT Method in Comparision to Standard Package Level Tests 57(4) A. Zitzelsberger A. Pietsch J. von Hagen Comparison of Isothermal, Constant Current & SWEAT Wafer Level EM Testing Methods 61(9) T.C. Lee D. Tibel T.D. Sullivan A Correlation Between Highly Accelerated Wafer Level & Standard Package Level Electromigration Tests on Deep Sub-Micron Via-Line Structures 70(4) M. Lepper R. Bauer A.E. Zitzelsberger The Effect of Stress Interruption & Pulsed Biased Stress on Ultra-Thin Gate Dielectric Reliability 74(6) B. Wang J.S. Suehle E.M. Vogel J.B. Bernstein Basic BEOL Parameters from Isothermal Wafer Level Electromigration Testing 80(5) T.D. Sullivan T.C. Lee D. Tibel New SWEAT Method for Fast, Accurate & Stable Electromigration Testing on Wafer Level 85(5) J. von Hagen G. Antonin J. Fazekas L.M. Head H.A. Schafft A Novel Electrical Test to Differentiate Gate-to-Source/Drain Silicide Short from Gate Oxide Short 90(5) A. Yassine K. Wieczorek K. Olasupo V. Heinig Threshold Voltage Drift in PMOSFETs due to NBTI & HCI 95(3) P. Chaparala J. Shibley P. Lim Negative Bias Temperature Instability (NBTI) in Deep Sub-micron p+-gate pMOSFETs 98(4) Y.F. Chen M.H. Lin C.H. Chou W.C. Chang S.C. Huang Y.J. Chang K.Y. Fu M.T. Lee C.H. Liu S.K. Fan Improving the Accuracy of ``Shift & Ratio Channel Length Extraction Method In Deep Submicron Technology 102(2) Q. Ye Y. Li W. R. Tonti W. Berry C. Parks R. Mohler Reliability of Via & Its Diagnosis by E-Beam Probing 104(3) W. Xia M. Villafana J. Tappan T. Watson M. Campbell Modeling Trap Generation Process In Thin Oxides 107(5) G. Bersuker Y. Jeon G. Gale J. Guan H. R. Huff Identification of Atomic Scale Defects Involved in Oxide Leakage Currents 112(4) P.M. Lenahan J.J. Mele J. Campbell A. Kang R.K. Lowry D. Woodbury S.T. Liu Stress-Induced Leakage Current Comparison of Giga-bit Scale DRAM Capacitors with OCS (One-Cylinder-Storage) Node 116(4) D. Park H. Ban S. Jung H. Yang W. Lee DISCUSSION GROUP SUMMARY REPORTS Thin Oxide 120(1) D.J. DiMaria J.S. Suehle Electromigration 121(2) H.A. Schafft T.D. Sullivan Burn-In 123(2) R. Multari R.-P. Vollertsen V. Reece POSTER PRESENTATIONS---REFEREED Effects of RTA and WSix-Polycide Gate Processes on MOSFET Reliability for Giga-bit Scale DRAMs 125(4) D. Park N.-J. Son J.-Y. Kim W. Lee LSF Technique to Analyze Intrinsic TDDB Failures of Gate Oxides 129(4) H. Katto Surface Roughness Effect on Gate Leakage and C-V Characteristics of Deep Submicron MOSFETs 133(4) J. Zhang J.S. Yuan Y. Ma A.S. Oates Hole Detrapping Effect on Gate Oxide Breakdown under DC and AC Stress 137(4) X. Duan W. Wu J.S. Yuan The Different Gate Oxide Degradation Mechanism under Constant Voltage/Current Stress & Ramp Voltage Stress 141(3) H. Luo Y. En X. Kong X. Zhang Reliability Issues of Ultra-Thick Gate Oxides 144(2) U. Schwalke M. Polzl T. Sekinger M. Kerber An Improved Substrate Current Model for Deep Submicron CMOS Transistors 146(3) W. Li J.S. Yuan S. Chetlur J. Zhou A.S. Oates Implementation of Short-time Classical HC Stresses for In-Line Reliability Control of sub-0.5 μm nMOSFETs 149(4) R. Gonella Developing Aged SPICE Model for Hot Carrier Reliability Simulation 153(2) Q. Ye H. Terletzki W. Tonti Improved Ring Oscillator Design Techniques to Generate Realistic AC Waveforms for Reliability Testing 155(3) H. Le B. Langley J. Cottle T.E. Kopley Off-State-Degradation of 170nm and 140nm Buried LDD pMOSFETs with Different HALO Implants 158(3) S. Holzhauser A. Narr Characterization of Extrusion Formation During High Temperature Anneal 161(4) J. Kelsey-Wynne F. Chen J. Furukawa T. Sullivan Electromigration Performance for Al/SiO2, Cu/SiO2, and Cu/low-k Interconnect Systems Including Joule Heating Effect 165(2) W. Wu S.H. Kang J.S. Yuan A.S. Oates Standardizing EM Structures for Evaluation and Qualification of Aluminum Alloys with Barrier Metals 167(4) M.J. Dion Fast Physics Based Wafer-Level Reliability Characterisation 171(4) V. Krozer M. Schussler H. Ganis M. Brandt C. Sydlo B. Motter S. Cassette S. Delage H.L. Hartnagel Wafer Level Reliability Testing of Heterojunction Bipolar Transistors 175(4) E. Sabin J. Scarpulla W. Kim E. Kaneshiro S. Dacus A Probabilistic-Physics-of-Failure/Short-Time-Test Approach to Reliability Assurance for High-Performance Chips: Models for Deep-Submicron Transistors and Optical Interconnects 179(6) A. Haggag W. McMahon K. Hess K. Cheng J. Lee J. Lyding Methods for Increasing Burn In Efficiency for DRAMS K. Nierle A. Norris 183(2) POSTER PRESENTATIONS---DROP IN Comparison of two Standard WLR Current-Ramped Tests for Oxide Reliability 185(2) B. Lanchava P. Baumgartner A. Martin A. Beyer E. Mueller Method for the Extraction of Extrinsic Data for Oxide Quality Assessment 187(2) A. Martin G. Diestel Time-dependent-dielectric Breakdown Used to Assess Copper Contamination Impact on Inter-level Dielectric Reliability 189(2) R. Gonella P. Motte J. Torres Process Steps Impact on Electrical and Electromigration Performances of Dual damascene Copper 191(2) R. Gonella J. Torres P. Motte E. van der Vegt J.M. Gilet Non-Volatile Memory Special Interest Group(SIG) Report 193(1) Tutorial Abstracts 194(1) Biographies 195
