Gathers the 12 papers presented during the January 2002 workshop on high performance computing, with an emphasis on low power design and network processing. Among the topics are reducing power with an L0 instruction cache using history-based prediction, tight nonlinear loop timing estimation, multigrain parallel processing for JPEG encoding on a single chip multiprocessor, and a low latency, high bandwidth network interface prototype for PC clusters. No subject index. Annotation c. Book News, Inc., Portland, OR (booknews.com)
