These 63 papers selected for the November 2006 symposium explore techniques for testing integrated circuits and systems, and are divided into sessions on test power reduction, memory tests, design verification, scan test methods, defect diagnosis, analog DFT, solutions for jitter problems, test compression, and network issues. Topics include a BIC sensor capable of adjusting IDDQ limit, test pattern generation for testing signal integrity, the diagnosis of transistor shorts in a logic test environment, and automation of IEEE 1149.6 boundary scan synthesis in an ASIC methodology. No subject index is provided. Annotation ©2007 Book News, Inc., Portland, OR (booknews.com)
