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60-GHz CMOS Phase-Locked Loops [Kõva köide]

  • Formaat: Hardback, 197 pages, kõrgus x laius: 235x155 mm, kaal: 1040 g, VIII, 197 p., 1 Hardback
  • Ilmumisaeg: 30-Aug-2010
  • Kirjastus: Springer
  • ISBN-10: 904819279X
  • ISBN-13: 9789048192793
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  • Formaat: Hardback, 197 pages, kõrgus x laius: 235x155 mm, kaal: 1040 g, VIII, 197 p., 1 Hardback
  • Ilmumisaeg: 30-Aug-2010
  • Kirjastus: Springer
  • ISBN-10: 904819279X
  • ISBN-13: 9789048192793
Abstract This chapter lays the foundation for the work presented in latter chapters. The potential of 60 GHz frequency bands for high data rate wireless transfer is discussed and promising applications are enlisted. Furthermore, the challenges related to 60 GHz IC design are presented and the chapter concludes with an outline of the book. Keywords Wireless communication 60 GHz Millimeter wave integrated circuit design Phase-locked loop CMOS Communication technology has revolutionized our way of living over the last century. Since Marconis transatlantic wireless experiment in 1901, there has been tremendous growth in wireless communication evolving from spark-gap telegraphy to todays mobile phones equipped with Internet access and multimedia capabilities. The omnipresence of wireless communication can be observed in widespread use of cellular telephony, short-range communication through wireless local area networks and personal area networks, wireless sensors and many others. The frequency spectrum from 1 to 6 GHz accommodates the vast majority of current wireless standards and applications. Coupled with the availability of low cost radio frequency (RF) components and mature integrated circuit (IC) techn- ogies, rapid expansion and implementation of these systems is witnessed. The downside of this expansion is the resulting scarcity of available bandwidth and allowable transmit powers. In addition, stringent limitations on spectrum and energy emissions have been enforced by regulatory bodies to avoid interference between different wireless systems.
1 Introduction 1(10)
2 Synthesizer System Architecture 11(24)
2.1 IEEE 802.15.3c Channelization
13(1)
2.2 60 GHz Frequency Conversion Techniques
14(3)
2.3 Proposed PLL Architecture: Flexible, Reusable, Multi-frequency
17(1)
2.3.1 Utilization in WiComm Project
18(1)
2.4 System Analysis and Design
18(10)
2.4.1 Phase-Lock Loop Basics
19(2)
2.4.2 Frequency Planning
21(1)
2.4.3 Synthesizer Parameters
22(6)
2.5 System Simulations
28(4)
2.6 Target Specifications
32(1)
2.7 Summary
33(2)
3 Layout and Measurements at mm-Wave Frequencies 35(22)
3.1 Layout Problems and Solutions
36(12)
3.1.1 Impact of Parasitics
37(4)
3.1.2 Mismatch Due to Layout Asymmetry and Device Orientation
41(1)
3.1.3 Substrate Losses
42(2)
3.1.4 Cross Talk Shielding and Grounding
44(4)
3.2 Measurement Setups
48(7)
3.2.1 Dedicated Instrumentation
49(2)
3.2.2 Calibration and De-embedding
51(3)
3.2.3 Stability and Repeatability
54(1)
3.3 Conclusions
55(2)
4 Design of High Frequency Components 57(94)
4.1 Prescaler
59(47)
4.1.1 Overview and Comparison of Prescaler Architectures
60(9)
4.1.2 35 GHz Static Frequency Divider
69(9)
4.1.3 40 GHz Divide-by-2 ILFD
78(10)
4.1.4 60 GHz Divide-by-3 ILFD
88(7)
4.1.5 Monolithic Transformer Design and Measurement
95(2)
4.1.6 Dual-Mode (Divide-by-2 and Divide-by-3) ILFD
97(7)
4.1.7 ILFD figure-of-Merit (FOM)
104(2)
4.1.8 Summary
106(1)
4.2 Voltage Controlled Oscillator
106(34)
4.2.1 Overview of VCO Architectures
107(4)
4.2.2 Theoretical Analysis of LC-VCOs
111(4)
4.2.3 40 GHz LC VCO
115(8)
4.2.4 60 GHz Actively Coupled I-Q VCO
123(6)
4.2.5 60 GHz Transformer Coupled I-Q VCO
129(8)
4.2.6 Dual-Band VCO for 40 and 60 GHz
137(3)
4.3 Synthesizer Front-Ends
140(8)
4.3.1 40 GHz VCO and Divide-by-2 ILFD
141(5)
4.3.2 60 GHz VCO and Divide-by-3 ILFD
146(2)
4.4 Conclusions
148(3)
5 Design of Low Frequency Components 151(14)
5.1 Feedback Division
152(8)
5.1.1 CML Based Divider Chain
152(5)
5.1.2 Mixer Based Division
157(3)
5.2 Phase-Frequency Detector, Charge-Pump and Loop Filter
160(4)
5.3 Conclusions
164(1)
6 Synthesizer Integration 165(18)
6.1 Synthesizer for 60 GHz Sliding-IF Frequency Conversion
166(9)
6.1.1 Comparison to Target Specifications
174(1)
6.2 Synthesizer with Down-Conversion Mixer in Feedback Loop
175(2)
6.3 Dual-Mode Synthesizer
177(3)
6.4 Conclusions
180(3)
7 Conclusions 183(2)
Appendix 185(6)
Appendix A Travelling Wave Divider Simulation Results
185(1)
Appendix B LC-VCOs Theory
186(5)
References 191