Introductory Section Welcoming Message 1(1) Steering Committee and Subcommittees 2(2) Technical Program Committee 4(4) ITC Technical Paper Evaluation and Selection Process 8(1) 1998 Paper Awards 9(2) 2000 Call for Papers 11(3) TTTC: Test Technology Technical Council 14(3) Technical Paper Reviewers 17 SESSION 1: PLENARY Mike Topsakal Yervant Zorian The Challenges of Design and Test for the World Wide Web 12(1) Patrick Gelsinger Using Neural Networks to Predict Reliability of Microelectromechanical Systems 13(10) J. Sebastian Perera SESSION 2: MCM & KNOWN-GOOD-DIE TESTING Russell Wagner David Keezer Exploiting Defect Clustering to Screen Bare Die for Infant Mortality Failures: An Experimental Study 23(8) D. R. Lakin, II* A. D. Singh A Probe Scheduling Algorithm for MCM Substrates 31(7) B. C. Kim* P. Jiang S. H. Park Testing an MCM for High-Energy Physics Experiments: A Case Study 38(9) A. Benso* S. Chiusano P. Prinetto S. Giovannetti R. Mariani S. Motto SESSION 3: DYNAMIC CURRENT TESTING Joan Figueras Robert Aitken Transient Current Testing in 0.25-μm CMOS Devices 47(10) B. Kruseman* P. Janssen V. Zieren Statistical Threshold Formulation For Dynamic IDD Test 57(10) W. Jiang* B. Vinnakota Defect Detection Using Power Supply Transient Signal Analysis 67(10) A. Germida Z. Yan J. F. Plusquellic* F. Muradali SESSION 4: LOW POWER AND DIAGNOSIS IN BIST Alfred Crouch Janusz Rajski Minimized Power Consumption for Scan-based BIST 77(8) S. Gerstendorfer* H. J. Wunderlich LT-RTPG: A New Test-per-Scan BIST TPG for Low Heat Dissipation 85(10) S. Wang S. K. Gupta* Fault Diagnosis in Scan-based BIST Using Both Time and Space Information 95(8) J. Ghosh-Dastidar* D. Das N. A. Touba SESSION 5: VOLUME PRODUCTION TESTING Tom Munns James Monzel Expediting Ramp-to-Volume Production 103(10) H. Balachandran* J. Parker G. Gammie J. Olson C. Force K. M. Butler S. Jandhyala Applications of Semiconductor Test Economics, and Multisite Testing to Lower Cost of Test 113(11) A. C. Evans Test Process Optimisation: Closing the Gap in the Defect Spectrum 124(6) N. Barrett S. Martin C. Dislis* SESSION 6: MICROPROCESSOR TESTING Magdy Abadir Scott Fetherston The Test and Debug Features of the AMD-K7™ Microprocessor 130(7) T. Wood DFT Advances in the Motorolas MPC7400, a PowerPC™ G4 Microprocessor 137(10) C. Pyron* M. Alexander J. Golab G. Joos B. Long R. Molyneaux R. Raina N. Tendolkar Towards Reducing ``Functional-Only Fails for the Ultra SPARC™ Microprocessors 147(8) A. Kinra SESSION 7: BOARD TEST-LECTURE SERIES Craig Soldat Joseph Mielke Breaking the Complexity Spiral in Board Test 155(1) S. Scheiber Breaking the Complexity Spiral in Board Test 155(4) S. Scheiber The Integration of Boundary-Scan Methods to a Mixed-Signal Environment 159(4) A. W. Ley Using LSSD to Test Modules at the Board Level 163(8) T. Ziaja SESSION 8: DELAY TESTING Prem Menon Scott Davidson Switch-Level Delay Test 171(10) S. Natarajan S. K. Gupta* M. A. Breuer Delay Testing Considering Power Supply Noise Effects 181(10) A. Krstic* Y. M. Jiang K. T. Cheng Test Generation for Crosstalk-Induced Delay in Integrated Circuits 191(10) W. Y. Chen* S. K. Gupta M. A. Breuer Accurate Path-Delay Fault Coverage is Feasible 201(10) S. Tragoudas SESSION 9: ANALOG TEST METHODS H. Alan Mantooth Bozena Kaminska High-Speed Digital Transceivers: A Challenge for Manufacturing 211(5) C. B. Cole* T. P. Warwick A New Approach to RF Impedance Test 216(5) D. R. Tao* Subband Filtering Scheme for Analog and Mixed-Signal Circuit Testing 221(9) J. Roh* J. A. Abraham Speed-up of Highly Accurate Analog Test Stimulus Optimization 230(7) A. Khouas* A. Derieux SESSION 10: VIRTUAL AND REAL TEST SOFTWARE Hira Ranga Art Downey Design of a Test Simulation Environment for Test Program Development 237(8) J. J. ORiordan Automatic Timing Margin Failure Location Analysis by Cycle Stretch Method 245(7) M. Matsumoto* Y. Ikeda Design for In-System Programming 252(8) D. Bonnett SESSION 11: DFT Nilanjan Mukherjee Magdy Abadir Robust Testability of Primitive Faults Using Test Points 260(9) R. Tekumalla* P. R. Menon Delay Testing of SOI Circuits: Challenges with the History Effect 269(7) E. MacDonald* N. A. Touba A DFT Technique for High-Performance Circuit Testing 276(10) M. Shashaani M. Sachdev* Testability Evaluation of Sequential Designs Incorporating the Multi-Mode Scannable Memory Element 286(8) A. D. Singh* E. S. Sogomonyan M. Goessel M. Seuring SESSION 12: EMBEDDED MEMORIES Betty Prince Rochit Rajsuman Practical Scan Test Generation and Application for Embedded FIFOs 294(7) J. Rearick Built-in Self-Test for GHz Embedded SRAMs Using Flexible Pattern Generator and New Repair Algorithm 301(10) S. Nakahara* K. Higeta M. Kohno T. Kohno T. Kawamura K. Kakitani An Algorithm for Row-Column Self-Repair of RAMs and Its Implementation in the Alpha 21264 311(8) D. K. Bhavsar SESSION 13: MEMS FAULT MODELING & TEST Andrew Richardson Rochit Rajsuman Fault Modeling of Suspended Thermal MEMS 319(10) B. Charlot* S. Mir E. F. Cota M. Lubaszewski B. Courtois Particulate Failures for Surface-Micromachined MEMS 329(9) T. Jiang* R. D. Blanton IMEMS Accelerometer Testing-Test Laboratory Development and Usage 338(10) R. W. Beegle* R. W. Brocato R. W. Grant SESSION 14: INDUSTRIAL APPLICATIONS OF BIST Steve Pateras Benoit Nadeau-Dostie Low-Overhead Test Point Insertion for Scan-based BIST 348(10) M. Nakao* S. Kobayashi K. Hatayama K. Iijima S. Terada Logic BIST for Large Industrial Designs: Real Issues and Case Studies 358(10) G. Hetherington* T. Fryars N. Tamarapalli M. Kassab A. Hassan J. Rajski Synthesis of Pattern Generators Based on Cellular Automata with Phase Shifters 368(10) G. Mrugalski J. Tyszer* J. Rajski SESSION 15: PRODUCTION WAFER TEST: WHERE THE PROBES MEET THE PROBES MEET THE PADS Frederick Taber William Mann Characterization and Optimization of the Production Probing Process 378(10) M. Quach* R. Samuelson D. Shaw RF (Gigahertz) ATE Production Testing on Wafer: Options and Tradeoffs 388(8) D. A. Gahagan Probe Contact Resistance Variations During Elevated-Temperature Wafer Test 396(10) J. J. Broz* R. M. Rincon SESSION 16: DESIGN VALIDATION & ANALYSIS FOR EVOLVING TECHNOLOGIES Tapan Chakraborty Prab Varma Sujit Dey Checking Sequence Generation for Asynchronous Sequential Elements 406(8) S. Goren* F. J. Ferguson Functional Verification of Intellectual Properties (IP): a Simulation-based Solution for an Application-Specific Instruction Set Processor 414(7) M. Stadler* T. Rower H. Kaeslin N. Felber W. Fichtner Critical Path Identification and Delay Tests of Dynamic Circuits 421(10) K. T. Lee* J. A. Abraham SESSION 17: BOARD TEST: INTERCONNECT TEST Brendan Davis Bernard Sutton An Embedded Technique for At-Speed Interconnect Testing 431(8) B. Nadeau-Dostie J. F. Cote H. Hulvershorn* S. Pateras Static Component Interconnect Test Technology (SCITT) a New Technology for Assembly Testing 439(10) A. Biewenga H. D. L. Hollmann F. de Jong M. Lousberg* Interconnect Delay Fault Testing with IEEE 1149.1 449(9) Y. Wu* P. Soong SESSION 18: ENHANCED TEST & DIAGNOSIS OF IC PROCESS DEFECTS Tracy Larrabee Jerry Soden Correlation of Logical Failures to a Suspect Process Step 458(9) H. Balachandran* J. Parker D. Shupp S. Butler K. M. Butler C. Force J. Smith Defect-based Delay Testing of Resistive Vias-Contacts: A Critical Evaluation 467(10) K. Baker G. Gronthoud M. Lousberg I. Schanstra C. Hawkins* Optimal Conditions for Boolean and Current Detection of Floating Gate Faults 477(10) M. Renovell* A. Ivanov Y. Bertrand F. Azais S. Rafiq SESSION 19: EMBEDDED CORE TEST Yervant Zorian Alex Orailoglu Embedded X86 Testing Methodology 487(6) L. Basto* A. Khan P. Hodakievic Testing Reusable IP-A Case Study 493(6) P. Harrod Testing a System-on-a-Chip with Embedded Microprocessor 499(10) R. Rajsuman SESSION 20: ISSUES IN TESTER ACCURACY Ulrich Schoettmer Donald Wheater Towards a Standardized Procedure for Automatic Test Equipment Timing Accuracy Evaluation 509(9) Y. Cai* W. R. Ortner C. T. Garrenton The Value of Tester Accuracy 518(6) W. Dalal* S. Miao An Accurate Simulation Model of the ATE Test Environment for Very-High-Speed Devices 524(8) T. P. Warwick* J. Cho Y. Cai B. Ortner SESSION 21: MIXED-SIGNAL BIST TECHNIQUES Mark Burns Gordon Roberts BIST for Phase-Locked Loops in Digital Applications 532(9) S. Sunter* A. Roy Auto-Calibrating Analog Timer for On-Chip Testing 541(8) B. Provost* E. Sanchez-Sinencio Effective Oscillation-based Test for Application to a DTMF Filter Bank 549(7) G. Huertas D. Vazquez A. Rueda* J. L. Huertas SESSION 22: BOARD TEST: PRACTICE MAKES PERFECT Kenneth Parker Bernard Sutton Static Component Interconnection Test Technology in Practice 556(10) F. de Jong* R. Raaijmakers S. Hellmold The HASS Development Process 566(11) D. Rahe Limited Access Testing of Analog Circuits: Handling Tolerances 577(10) C. Ahrikencheikh* M. Spears SESSION 23: FAULT SIMULATION FROM BRIDGES TO RTL Raj Raina Mahesh lyer A Comparison of Bridging Fault Simulation Methods 587(9) S. Ma* I. Shaik R. S. Fetherston Resistive Bridge Fault Modelling, Simulation and Test Generation 596(10) V. R. Sar-Dessai D. M. H. Walker* SymSim: Symbolic Fault Simulation of Data-Flow Data-Path Designs at the Register-Transfer Level 606(10) S. Yadavalli* S. Reddy SESSION 24: PRACTICING EMBEDDED CORE TEST Erik Jan Marinissen Alex Orailoglu Towards a Standards for Embedded Core Test: An Example 616(12) E. J. Marinissen Y. Zorian R. Kapur* T. Taylor L. Whetsel Trends in SLI Design and their Effect on Test 628(10) R. Aitken* F. Muradali Test Features of a Core-based Co-Processor Array for Video Applications 638(11) J. van Beers* H. van Herten SESSION 25: (PANEL) IS ANALOG FAULT SIMULATION A KEY TO PRODUCT QUALITY? PRACTICAL CONSIDERATIONS Bozena Kaminska Analog Fault Simulation: Need it? No. It is Already Done. 649(1) E. R. Atwood Analog Fault Simulation: Key to Product Quality, or a Foot in the Door 650(1) C. Force Closing the Gap Between Process Development and Mixed-Signal Design and Testing 651(1) H. Haggag SESSION 26: ON-LINE TESTING TECHNIQUES Laroussi Bouzaida Michael Nicolaidis Self-Checking Scheme for Very Fast Clocks Skew Correction 652(10) C. Metra* F. Giovanelli M. Soma, B. Ricco A Design Diversity Metric and Reliability Analysis for Redundant Systems 662(10) S. Mitra* N. R. Saxena E. J. McCluskey Finite State Machine Synthesis with Concurrent Error Detection 672(8) C. Zeng N. R. Saxena* E. J. McCluskey SESSION 27: SYSTEM TEST-LECTURE SERIES Joe Mielke Craig Soldat The Evolution of a System Test Process 680(9) S. Martin* R. Bleck C. Dislis D. Farren System Design Verification Test-An Overview 689(9) S. Stoica PC Manufacturing Test in a High-Volume Environment 698(7) D. Williams DFT, Test Lifecycles and the Product Lifecycle 705(9) G. D. Robinson SESSION 28: PRODUCTIONIDDQ TESTING BEYOND SINGLE-THRESHOLD MEASUREMENTS Anne Gattiker Keith Baker An Histogram-based Procedure for Current Testing of Active Defects 714(10) C. Thibeault IDDQ Testing In Deep-submicron Integrated Circuits 724(6) A. C. Miller Clustering-based Techniques for IDDQ Testing 730(8) S. Jandhyala* H. Balachandran A. Jayasumana Current Ratios: A Self-Scaling Technique for Production IDDQ Testing 738(9) P. Maxwell* P. ONeill R. Aitken R. Dudley N. Jaarsma M. Quach D. Wiseman SESSION 29: TESTING ANALOG TO DIGITAL CONVERTERS Andrew Evans Sandeep Kumar Gordon Roberts Linearity Testing Issues of Analog to Digital Converters 747(10) T. Kuyel Estimating the Integral Nonlinearity of AD-Converters via the Frequency Domain 757(6) N. Csizmadia* A. J. E. M. Janssen Testing High-Speed-Accuracy Analog to Digital Converters Embedded in Systems on a Chip 763(9) S. Max Relating Linearity Test Results to Design Flaws of Pipelined Analog to Digital Converters 772(8) T. Kuyel* H. Bilhan SESSION 30: ISSUES IN HIGH-SPEED TESTING Justin Woyke Donald Wheater Accuracy Requirements in At-Speed Functional Test 780(8) B. G. West A New Method for Jitter Decomposition Through its Distribution Tail Fitting 788(7) M. P. Li* J. Wilstrup R. Jessen D. Petrich At-Speed Structural Test 795(6) B. G. West Test Support Processors for Enhanced Testability of High-Performance Circuits 801(9) D. Keezer* Q. Zhou SESSION 31: TEST METHODOLOGY STATE OF PRACTICE & CASE STUDIES Scott Fetherston Nur Touba Design-for-Test Methodology for Motorola PowerPC™ Microprocessors 810(10) M. S. Abadir R. Raina* Testability of the Philips 80C51 Micro-Controller 820(10) M. H. Konijnenburg* J. T. van der Linden A. J. van de Goor Tradeoff Analysis for Producing High-Quality Tests for Custom Circuits in PowerPC™ 830(9) L. C. Wang* M. S. Abadir A Study of Test Quality/Tester Scan Memory Trade-Offs Using the SEMATECH Test Methods Data 839(9) K. M. Butler SESSION 32: SYSTEM TEST METHODS FROM DFT TO END OF LIFE Des Farren William Simpson Robust Test Methods Applied to Functional Design Verification 848(10) S. Stoica An Integrated Approach To Behavioral-Level Design-for-Testability Using Value-Range and Variable 858(10) S. Seshadri* M. S. Hsiao The Test Requirements Model (TeRM) Communicating Test Information Thoughout The Product Life Cycle 868(9) L. A. Shombert* D. C. Davis E. M. Bukata SESSION 33: DESIGN FOR Chau-chin Su Mary Kusko Design for (Physical) Debug for Silicon Microsurgery and Probing of Flip-Chip Packaged Integrated Circuits 877(6) R. H. Livengood* D. Medeiros The Attack of the ``Holey Shmoos: Case Study of Advanced DFD and Picosecond Imaging Circuit Analysis (PICA) 883(9) W. Huott* M. McManus D. Knebel S. Steen D. Manzer P. Sanda S. Wilson Y. Chan A. Pelella S. Polonsky Silicon Debug: Scan Chains Alone Are Not Enough 892(11) G. J. van Rootselaar* B. Vermeulen SESSION 34: TEST SYNTHESIS Vishwani Agrawal Kwang-Ting (Tim)Cheng A High-Level BIST Synthesis Method Based on a Region-wise Heuristic for an Integer Linear Programming 903(10) D. S. Ha H. B. Kim* The Testability Features of the 3rd Generation ColdFire® Family of Microprocessors 913(10) A. L. Crouch M. Mateja T. L. McLaurin* J. C. Potter D. Tran On Achieving Complete Coverage of Delay Faults in Full-Scan Circuits Using Locally Available Lines 923(9) I. Pomeranz* S. M. Reddy SESSION 35: MIXED-SIGNAL ATE ISSUES & OPTICAL PROBING Jim OReilly Donald Wheater Practical Optical Waveform Probing of Flip-Chip CMOS Devices 932(8) K. R. Wilsher* W. K. Lo Flexible ATE Module with Reconfiguration Circuit and Its Application 940(7) T. Kitagaki A Method to Improve the Performance of High-Speed Waveform Digitizing 947(8) K. Asami* S. Tajiri SESSION 36: ON-LINE TESTING FOR FP GAS AND PROCESSORS Michael Nicolaidis Michael Nicolaidis On-line Fault Detection in DSP Circuits using Extrapolated Checksums with Minimal Test Points 955(9) S. Chakrabarti* A. Chatterjee An Efficient On-line-Test and Backup Scheme for Embedded Processors 964(9) M. Pflanz F. Pompsch H. T. Vierhaus* Using Roving STARs for On-line Testing and Diagnosis of FPGAs in Fault-Tolerant Applications 973(10) M. Abramovici* C. Stroud C. Hamilton S. Wijesuriya V. Verma SESSION 37: MEMORY TESTING Bruce Cockburn Rochit Rajsuman Industrial Evaluation of Stress Combinations for March Tests Applied to SRAMs 983(10) I. Schanstra* A. J. van de Goor An On-line BISTed SRAM IP Core 993(8) M. Lobetti-Bodoni A. Pricco A. Benso S. Chiusano* P. Prinetto Port Interference Faults in Two-Port Memories 1001(10) S. Hamdioui* A. J. van de Goor SESSION 38: TEST GENERATION Fadi Maamari Mahesh Iyer Using VeriLog Simulation Libraries for ATPG 1011(10) P. Wohl* J. Waicukauski STAR-ATPG: A High-Speed Test Pattern Generator for Large Scan Designs 1021(10) K. H. Tsai* R. Tompson J. Rajski M. Marek-Sadowska Modeling the Probability of Defect Excitation for a Commercial IC with Implications for Stuck-at Fault-based ATPG Strategies 1031(7) J. Dworak M. R. Grimaila S. Lee L. C. Wang M. R. Mercer* SESSION 39: ADVANCED SOLUTIONS FOR SOC TEST Alex Orailoglu Alex Orailoglu HD-BIST: a Hierarchical Framework for BIST Scheduling and Diagnosis in SoCs 1038(7) A. Benso S. Cataldo S. Chiusano P. Prinetto* Delay Fault Testing of IP-based Designs via Symbolic Path Modeling 1045(10) H. Kim* J. P. Hayes Addressable Test Ports-An Approach to Testing Embedded Cores 1055(10) L. Whetsel SESSION 40: APPLYING DIAGNOSIS IN A PRODUCTION TEST ENVIRONMENT Hari Balachandran Kenneth Butler Eliminating the Ouiji® Board: Automatic Thresholds and Probabilistic IDDQ 1065(8) D. B. Lavo* T. Larrabee J. E. Colburn Diagnostic Techniques for the IBM S/390 600-MHz G5Microprocessor 1073(10) P. Song* F. Motika D. Knebel R. Rizzolo M. Kusko J. Lee M. McManus The Effects of Test Compaction on Fault Diagnosis 1083(7) Y. Shao R. Guo I. Pomeranz S. M. Reddy* SESSION 41: TIME-TO-MARKET: LECTURE SERIES Joe Mielke Joseph Mielke Is DFT Right for You? 1090(8) J. Johnson Design-for-Test and Time-to-Market-Friends or Foes? 1098(4) J. Turino Design for Testability: It is Time to Deliver it for Time-to-Market 1102(11) B. Dervisoglu PANEL 1: HIGH TIME FOR HIGH-LEVEL ATPG Mahesh A. Iyer High Time for High-Level ATPG 1113(1) W. T. Cheng Changing our Path to High-Level ATPG 1114(1) S. Davidson High-Level ATPG is Important and Is on Its Way! 1115(2) R. Kapur High Time for Higher-Level BIST 1117(1) C. Papachristou High-Level ATPG: A Real Topic or an Academic Amusement? 1118(1) M. S. Reorda High-Level ATPG for Early Power Analysis 1119(4) W. Roethig PANEL 2: PRODUCTION MEMORY TESTER-PRESENT AND FUTURE Gary Gillette Bin Bai PANEL 3: SIA ROADMAPS: SUNSET BOULEVARD FOR IDDQ Keith Baker PANEL 4: THIN GATE RELIABILITY Pete Maxwell Jeffrey Roehr Applying Lessons Learned from TDDB Testing 1123(3) J. Prendergast PANEL 5: WHAT DO WE NEED SYSTEM TEST FOR? Steve Strauss P.V. Sridhar PANEL 6: ITC99 BENCHMARK CIRCUITS-PRELIMINARY RESULTS Scott Davidson Scan Insertion to the Behavioral Level 1126(1) C. Aktouf Benchmarking DAT with the ITC99 ATPG Benchmarks 1127(1) M. Konijnenburg H. van der Linden J. Geuzebrock Application of Tools Developed at the University of Iowa to ITC-99 Benchmarks 1128(1) S. M. Reddy High-Level Test Bench Generation Using Software Engineering Concepts 1129(1) J. F. Santucci C. Paoli Automatic Functional Test Generation-A Reality 1130(2) R. S. Tupuri PANEL 7: INCREASING TEST COVERAGE IN A VLSI DESIGN Vishwani D. Agrawal Position Statement: Increasing Test Coverage in a VLSI Design Course 1132(1) J. A. Abraham Increasing Test Coverage in a VLSI Design Course 1133(1) M. L. Bushnell VLSI Design 101 - The Test Module 1134(1) J. Harrington Increasing Test Coverage in a VLSI design Course 1135(1) M. Robert Panel Statement: Increasing Test Coverage in a VLSI Design 1136(1) M. Soma Position Statement: Testing in a VLSI Design Course 1137(2) W. Wolf PANEL 8: SCITT: BACK TO BASICS IN MASS PRODUCTION TESTING Ben Bennetts Frans de Jong SCITT: Bringing DRAMs Into the Test Fold 1139(1) F. W. Angelotti Static Component Interconnection Test Technology (SCITT) 1140(3) S. Hellmold PANEL 9: DFT IS ALL I CAN AFFORD, WHO CARES ABOUT DESIGN FOR YIELD OR DESIGN FOR RELIABILITY! Edward McCluskey David M. Wu It Makes Sense to Combine DFT and DFR/DFY 1143(1) R. C. Aitken DFT, DFY, DFR: Who Cares? 1144(1) S. Fetherston DFT, DFY, and DFR; Which One(s) Do You Worry About? 1145(1) J. A. Monzel Design for Yield and Reliability is MORE Important Than DFT 1146(1) D. M. H. Walker ``DFY and DFR are More Important Than DFT 1147(2) D. M. Wu PANEL 10: OUTPUT IN STIL, INPUT IN STIL Greg Maston Peter Wohl STIL: The Device-oriented Database for the Test Development Lifecycle 1149(1) N. Biggs Using STIL to Describe Embedded Core Test Requirements 1150(1) B. Keller Is There a STIL for Mixed-Signal Testing? 1151(1) M. Loranger 1998 ITC Best Paper: Failure Analysis of Timing and IDDQ-only Failures from the SEMATECH Test Methods Experiment 1152(10) P. Nigh D. Vallett A. Patel J. Wright F. Motika D. Forlenza R. Kurtulik W. Chong Author Index 1162
