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Advanced Hardware Design for Error Correcting Codes 2015 ed. [Kõva köide]

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  • Formaat: Hardback, 192 pages, kõrgus x laius: 235x155 mm, kaal: 4691 g, 25 Illustrations, color; 56 Illustrations, black and white; IX, 192 p. 81 illus., 25 illus. in color., 1 Hardback
  • Ilmumisaeg: 11-Nov-2014
  • Kirjastus: Springer International Publishing AG
  • ISBN-10: 331910568X
  • ISBN-13: 9783319105680
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  • Formaat: Hardback, 192 pages, kõrgus x laius: 235x155 mm, kaal: 4691 g, 25 Illustrations, color; 56 Illustrations, black and white; IX, 192 p. 81 illus., 25 illus. in color., 1 Hardback
  • Ilmumisaeg: 11-Nov-2014
  • Kirjastus: Springer International Publishing AG
  • ISBN-10: 331910568X
  • ISBN-13: 9783319105680
This book provides thorough coverage of error correcting techniques. It includes essential basic concepts and the latest advances on key topics in design, implementation, and optimization of hardware/software systems for error correction. The books chapters are written by internationally recognized experts in this field. Topics include evolution of error correction techniques, industrial user needs, architectures, and design approaches for the most advanced error correcting codes (Polar Codes, Non-Binary LDPC, Product Codes, etc). This book provides access to recent results, and is suitable for graduate students and researchers of mathematics, computer science, and engineering.

Examines how to optimize the architecture of hardware design for error correcting codes;

Presents error correction codes from theory to optimized architecture for the current and the next generation standards;

Provides coverage of industrial user needs advanced error correcting techniques.

Advanced Hardware Design for Error Correcting Codes includes a foreword by Claude Berrou.
1 User Needs
1(6)
David Gnaedig
2 Challenges and Limitations for Very High Throughput Decoder Architectures for Soft-Decoding
7(26)
Norbert Wehn
Stefan Scholl
Philipp Schlafer
Timo Lehnigk-Emden
Matthias Alles
3 Implementation of Polar Decoders
33(14)
Gabi Sarkis
Warren J. Gross
4 Parallel Architectures for Turbo Product Codes Decoding
47(26)
Camille Leroux
Christophe Jego
Patrick Adde
5 VLSI Implementations of Sphere Detectors
73(32)
Johanna Ketonen
Markus Myllyla
Yang Sun
Joseph R. Cavallaro
6 Stochastic Decoders for LDPC Codes
105(24)
Francois Leduc-Primeau
Vincent C. Gaudet
Warren J. Gross
7 MP-SoC/NoC Architectures for Error Correction
129(22)
Carlo Condo
Maurizio Martina
Guido Masera
8 ASIP Design for Multi-Standard Channel Decoders
151(26)
Purushotham Murugappa
Amer Baghdadi
Michel Jezequel
9 Hardware Design of Parallel Interleaver Architectures: A Survey
177
Cyrille Chavet
Awais Hussain Sani
Philippe Coussy
Cyrille Chavet is an Associate Professor at Associate Professors at Université de Bretagne Sud, Lorient, France. Philippe Coussy is an Associate Professor at Associate Professors at Université de Bretagne Sud, Lorient, France.