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Analog IC Reliability in Nanometer CMOS 2013 ed. [Pehme köide]

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  • Formaat: Paperback / softback, 198 pages, kõrgus x laius: 235x155 mm, kaal: 3343 g, XVI, 198 p., 1 Paperback / softback
  • Sari: Analog Circuits and Signal Processing
  • Ilmumisaeg: 19-Jun-2015
  • Kirjastus: Springer-Verlag New York Inc.
  • ISBN-10: 1489986308
  • ISBN-13: 9781489986306
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Analog IC Reliability in Nanometer CMOS 2013 ed.Suurem pilt
  • Formaat: Paperback / softback, 198 pages, kõrgus x laius: 235x155 mm, kaal: 3343 g, XVI, 198 p., 1 Paperback / softback
  • Sari: Analog Circuits and Signal Processing
  • Ilmumisaeg: 19-Jun-2015
  • Kirjastus: Springer-Verlag New York Inc.
  • ISBN-10: 1489986308
  • ISBN-13: 9781489986306
Teised raamatud teemal:
Püsilink: https://www.kriso.ee/db/9781489986306.html
Märksõnad:
This book covers modeling, simulation and analysis of analog circuit aging, nanometer CMOS physical effects resulting in unreliability, transistor aging compact models for circuit simulation, methods for efficient circuit reliability simulation and more.

This book focuses on modeling, simulation and analysis of analog circuit aging. First, all important nanometer CMOS physical effects resulting in circuit unreliability are reviewed. Then, transistor aging compact models for circuit simulation are discussed and several methods for efficient circuit reliability simulation are explained and compared. Ultimately, the impact of transistor aging on analog circuits is studied. Aging-resilient and aging-immune circuits are identified and the impact of technology scaling is discussed.

The models and simulation techniques described in the book are intended as an aid for device engineers, circuit designers and the EDA community to understand and to mitigate the impact of aging effects on nanometer CMOS ICs.

1 Introduction
1(14)
1.1 Introduction
1(1)
1.2 Reliability Engineering: A Brief History
1(2)
1.3 Reliability of Electronic Systems
3(2)
1.4 Reliability in Nanometer CMOS
5(4)
1.4.1 Reduction of the Effective Oxide Thickness
5(2)
1.4.2 Introduction of New Materials and Devices
7(1)
1.4.3 Atomic-Scale Dimensions
8(1)
1.4.4 Mission Profiles
9(1)
1.4.5 Time and Money Constraints
9(1)
1.5 Design for Reliability
9(5)
1.5.1 Define
10(1)
1.5.2 Identify
11(1)
1.5.3 Analyze and Assess
12(1)
1.5.4 Quantify, Improve and Validate
13(1)
1.5.5 Monitor and Control
13(1)
1.6 Conclusions
14(1)
2 CMOS Reliability Overview
15(22)
2.1 Introduction
15(1)
2.2 The Origin of CMOS Unreliability
15(3)
2.3 Spatial Unreliability
18(5)
2.3.1 Systematic Effects
19(1)
2.3.2 Random Effects
19(4)
2.4 Temporal Unreliability
23(11)
2.4.1 Aging Effects
23(9)
2.4.2 Transient Effects
32(2)
2.5 Conclusions
34(3)
3 Transistor Aging Compact Modeling
37(42)
3.1 Introduction
37(1)
3.2 Hot Carrier Injection
38(9)
3.2.1 Background
38(2)
3.2.2 A HCI Compact Model for Circuit Simulation
40(6)
3.2.3 HCI in Sub-45 nm CMOS
46(1)
3.3 Bias Temperature Instability
47(22)
3.3.1 Background
47(8)
3.3.2 A BTI Compact Model for Circuit Simulation
55(6)
3.3.3 Model Calibration and Validation
61(7)
3.3.4 BTI in Sub-45 nm CMOS
68(1)
3.4 Time-Dependent Dielectric Breakdown
69(4)
3.4.1 Hard Breakdown
70(1)
3.4.2 Soft Breakdown
71(2)
3.5 Aging-Equivalent Transistor Model
73(2)
3.5.1 Threshold Voltage
73(1)
3.5.2 Carrier Mobility
74(1)
3.5.3 Oxide Breakdown
75(1)
3.6 Aging Model for Hand Calculations
75(1)
3.7 Conclusions
76(3)
4 Background on IC Reliability Simulation
79(14)
4.1 Introduction
79(1)
4.2 Literature Overview
80(4)
4.2.1 Berkeley Reliability Tools (BERT)
80(3)
4.2.2 Other Reliability Simulators
83(1)
4.3 Commercial Reliability Simulators
84(5)
4.3.1 The Mentor Graphics Reliability Simulator
84(2)
4.3.2 The Cadence Reliability Simulator (BERT/RelXpert)
86(1)
4.3.3 The Synopsys Reliability Simulator (MOSRA)
87(2)
4.4 Discussion
89(2)
4.5 Conclusions
91(2)
5 Analog IC Reliability Simulation
93(58)
5.1 Introduction
93(1)
5.2 Deterministic Reliability Simulation
94(15)
5.2.1 Problem Statement
94(1)
5.2.2 Implementation
95(8)
5.2.3 Circuit Example
103(6)
5.3 Stochastic Reliability Simulation
109(27)
5.3.1 Problem Statement
109(3)
5.3.2 Implementation 1: Monte-Carlo Simulation
112(3)
5.3.3 Implementation 2: A Response Surface Methodology
115(16)
5.3.4 Circuit Example
131(5)
5.4 Hierarchical Reliability Simulation
136(13)
5.4.1 Problem Statement
136(1)
5.4.2 Implementation
137(9)
5.4.3 Circuit Example
146(3)
5.5 Conclusions
149(2)
6 Integrated Circuit Reliability
151(30)
6.1 Introduction
151(1)
6.2 Assessment
152(8)
6.2.1 Observed Performance Parameter
153(2)
6.2.2 Process Capability Index
155(3)
6.2.3 Technology
158(1)
6.2.4 Circuit Design
159(1)
6.2.5 Stress Conditions
160(1)
6.3 Failure-Resilient Circuits
160(4)
6.3.1 Intrinsically Robust Circuits
161(2)
6.3.2 Self-healing Circuits
163(1)
6.4 Case Study 1: IDAC
164(7)
6.4.1 Technology
166(1)
6.4.2 Conventional Design
167(1)
6.4.3 Reliability-Aware Design: Fixed Topology
168(2)
6.4.4 Reliability-Aware Design: Digitally-Assisted Analog
170(1)
6.5 Case Study 2: Digital Circuits
171(8)
6.5.1 Digital Circuit Lifetime
172(1)
6.5.2 Minimum Circuit Lifetime
173(2)
6.5.3 Example Circuit
175(4)
6.6 Conclusions
179(2)
7 Conclusions
181(4)
7.1 General Conclusions
181(4)
Bibliography 185(10)
Index 195