Klienditugi: 7440010 (E-R 10-18)

Analog Integrated Circuit Design 2nd Revised edition [Kõva köide]

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Tony Chan Carusone (University of Toronto, Canada), David A. Johns (University of Toronto, Canada), Kenneth W. Martin (University of Toronto, Canada)

Formaat: Hardback, 816 pages, kõrgus x laius x paksus: 239x198x33 mm, kaal: 1406 g
Ilmumisaeg: 18-Nov-2011
Kirjastus: John Wiley & Sons Ltd
ISBN-10: 0470770104
ISBN-13: 9780470770108

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Formaat: Hardback, 816 pages, kõrgus x laius x paksus: 239x198x33 mm, kaal: 1406 g
Ilmumisaeg: 18-Nov-2011
Kirjastus: John Wiley & Sons Ltd
ISBN-10: 0470770104
ISBN-13: 9780470770108

Teised raamatud teemal:

Circuits & components - (Hetkel poes: 1 nimetust)

Püsilink: https://www.kriso.ee/db/9780470770108.html

Märksõnad:

The 2^nd Edition of Analog Integrated Circuit Design focuses on more coverage about several types of circuits that have increased in importance in the past decade. Furthermore, the text is enhanced with material on CMOS IC device modeling, updated processing layout and expanded coverage to reflect technical innovations. CMOS devices and circuits have more influence in this edition as well as a reduced amount of text on BiCMOS and bipolar information. New chapters include topics on frequency response of analog ICs and basic theory of feedback amplifiers.

Chapter 1 Integrated-Circuit Devices and Modelling

(72)

1.1 Semiconductors and pn Junctions

(13)

1.1.1 Diodes

(2)

1.1.2 Reverse-Biased Diodes

(3)

1.1.3 Graded Junctions

(2)

1.1.4 Large-Signal Junction Capacitance

(1)

1.1.5 Forward-Biased Junctions

(1)

1.1.6 Junction Capacitance of Forward-Biased Diode

(1)

1.1.7 Small-Signal Model of a Forward-Biased Diode

(1)

1.1.8 Schottky Diodes

(1)

1.2 MOS Transistors

(24)

1.2.1 Symbols for MOS Transistors

(1)

1.2.2 Basic Operation

(5)

1.2.3 Large-Signal Modelling

(3)

1.2.4 Body Effect

(1)

1.2.5 p-Channel Transistors

(1)

1.2.6 Low-Frequency Small-Signal Modelling in the Active Region

(5)

1.2.7 High-Frequency Small-Signal Modelling in the Active Region

(3)

1.2.8 Small-Signal Modelling in the Triode and Cutoff Regions

(3)

1.2.9 Analog Figures of Merit and Trade-offs

(2)

1.3 Device Model Summary

(4)

1.3.1 Constants

(1)

1.3.2 Diode Equations

(1)

1.3.3 MOS Transistor Equations

(2)

1.4 Advanced MOS Modelling

(8)

1.4.1 Subthreshold Operation

(2)

1.4.2 Mobility Degradation

(3)

1.4.3 Summary of Subthreshold and Mobility Degradation Equations

(1)

1.4.4 Parasitic Resistances

(1)

1.4.5 Short-Channel Effects

(1)

1.4.6 Leakage Currents

(1)

1.5 SPICE Modelling Parameters

(4)

1.5.1 Diode Model

(1)

1.5.2 MOS Transistors

(1)

1.5.3 Advanced SPICE Models of MOS Transistors

(3)

1.6 Passive Devices

(6)

1.6.1 Resistors

(4)

1.6.2 Capacitors

(2)

1.7 Appendix

(8)

1.7.1 Diode Exponential Relationship

(2)

1.7.2 Diode-Diffusion Capacitance

(2)

1.7.3 MOS Threshold Voltage and the Body Effect

(2)

1.7.4 MOS Triode Relationship

(2)

1.8 Key Points

(1)

1.9 References

(1)

1.10 Problems

(4)

Chapter 2 Processing and Layout

(44)

2.1 CMOS Processing

(13)

2.1.1 The Silicon Wafer

(1)

2.1.2 Photolithography and Well Definition

(2)

2.1.3 Diffusion and Ion Implantation

(2)

2.1.4 Chemical Vapor Deposition and Defining the Active Regions

(1)

2.1.5 Transistor Isolation

(3)

2.1.6 Gate-Oxide and Threshold-Voltage Adjustments

(1)

2.1.7 Polysilicon Gate Formation

(1)

2.1.8 Implanting the Junctions, Depositing SiO2, and Opening Contact Holes

(2)

2.1.9 Annealing, Depositing and Patterning Metal, and Overglass Deposition

(1)

2.1.10 Additional Processing Steps

(2)

2.2 CMOS Layout and Design Rules

(10)

2.2.1 Spacing Rules

(8)

2.2.2 Planarity and Fill Requirements

(1)

2.2.3 Antenna Rules

(1)

2.2.4 Latch-Up

(1)

2.3 Variability and Mismatch

(7)

2.3.1 Systematic Variations Including Proximity Effects

(2)

2.3.2 Process Variations

(1)

2.3.3 Random Variations and Mismatch

(4)

2.4 Analog Layout Considerations

103

(10)

2.4.1 Transistor Layouts

103

(1)

2.4.2 Capacitor Matching

104

(3)

2.4.3 Resistor Layout

107

(2)

2.4.4 Noise Considerations

109

(4)

2.5 Key Points

113

(1)

2.6 References

114

(1)

2.7 Problems

114

(3)

Chapter 3 Basic Current Mirrors and Single-Stage Amplifiers

117

(27)

3.1 Simple CMOS Current Mirror

118

(2)

3.2 Common-Source Amplifier

120

(2)

3.3 Source-Follower or Common-Drain Amplifier

122

(2)

3.4 Common-Gate Amplifier

124

(3)

3.5 Source-Degenerated Current Mirrors

127

(2)

3.6 Cascode Current Mirrors

129

(2)

3.7 Cascode Gain Stage

131

(4)

3.8 MOS Differential Pair and Gain Stage

135

(3)

3.9 Key Points

138

(1)

3.10 References

139

(1)

3.11 Problems

139

(5)

Chapter 4 Frequency Response of Electronic Circuits

144

(60)

4.1 Frequency Response of Linear Systems

144

(21)

4.1.1 Magnitude and Phase Response

145

(2)

4.1.2 First-Order Circuits

147

(7)

4.1.3 Second-Order Low-Pass Transfer Functions with Real Poles

154

(3)

4.1.4 Bode Plots

157

(6)

4.1.5 Second-Order Low-Pass Transfer Functions with Complex Poles

163

(2)

4.2 Frequency Response of Elementary Transistor Circuits

165

(16)

4.2.1 High-Frequency MOS Small-Signal Model

165

(1)

4.2.2 Common-Source Amplifier

166

(3)

4.2.3 Miller Theorem and Miller Effect

169

(4)

4.2.4 Zero-Value Time-Constant Analysis

173

(3)

4.2.5 Common-Source Design Examples

176

(3)

4.2.6 Common-Gate Amplifier

179

(2)

4.3 Cascode Gain Stage

181

(6)

4.4 Source-Follower Amplifier

187

(6)

4.5 Differential Pair

193

(4)

4.5.1 High-Frequency T-Model

193

(1)

4.5.2 Symmetric Differential Amplifier

194

(1)

4.5.3 Single-Ended Differential Amplifier

195

(1)

4.5.4 Differential Pair with Active Load

196

(1)

4.6 Key Points

197

(1)

4.7 References

198

(1)

4.8 Problems

199

(5)

Chapter 5 Feedback Amplifiers

204

(38)

5.1 Ideal Model of Negative Feedback

204

(4)

5.1.1 Basic Definitions

204

(1)

5.1.2 Gain Sensitivity

205

(2)

5.1.3 Bandwidth

207

(1)

5.1.4 Linearity

207

(1)

5.1.5 Summary

208

(1)

5.2 Dynamic Response of Feedback Amplifiers

208

(5)

5.2.1 Stability Criteria

209

(2)

5.2.2 Phase Margin

211

(2)

5.3 First- and Second-Order Feedback Systems

213

(7)

5.3.1 First-Order Feedback Systems

213

(4)

5.3.2 Second-Order Feedback Systems

217

(3)

5.3.3 Higher-Order Feedback Systems

220

(1)

5.4 Common Feedback Amplifiers

220

(15)

5.4.1 Obtaining the Loop Gain, L(s)

222

(4)

5.4.2 Non-Inverting Amplifier

226

(5)

5.4.3 Transimpedance (Inverting) Amplifiers

231

(4)

5.5 Summary of Key Points

235

(1)

5.6 References

235

(1)

5.7 Problems

236

(6)

Chapter 6 Basic Opamp Design and Compensation

242

(60)

6.1 Two-Stage CMOS Opamp

242

(12)

6.1.1 Opamp Gain

243

(2)

6.1.2 Frequency Response

245

(4)

6.1.3 Slew Rate

249

(3)

6.1.4 n-Channel or p-Channel Input Stage

252

(1)

6.1.5 Systematic Offset Voltage

252

(2)

6.2 Opamp Compensation

254

(7)

6.2.1 Dominant-Pole Compensation and Lead Compensation

254

(1)

6.2.2 Compensating the Two-Stage Opamp

255

(4)

6.2.3 Making Compensation Independent of Process and Temperature

259

(2)

6.3 Advanced Current Mirrors

261

(7)

6.3.1 Wide-Swing Current Mirrors

261

(2)

6.3.2 Enhanced Output-Impedance Current Mirrors and Gain Boosting

263

(3)

6.3.3 Wide-Swing Current Mirror with Enhanced Output Impedance

266

(1)

6.3.4 Current-Mirror Symbol

267

(1)

6.4 Folded-Cascode Opamp

268

(7)

6.4.1 Small-Signal Analysis

270

(2)

6.4.2 Slew Rate

272

(3)

6.5 Current Mirror Opamp

275

(4)

6.6 Linear Settling Time Revisited

279

(2)

6.7 Fully Differential Opamps

281

(7)

6.7.1 Fully Differential Folded-Cascode Opamp

283

(1)

6.7.2 Alternative Fully Differential Opamps

284

(2)

6.7.3 Low Supply Voltage Opamps

286

(2)

6.8 Common-Mode Feedback Circuits

288

(4)

6.9 Summary of Key Points

292

(1)

6.10 References

293

(1)

6.11 Problems

294

(8)

Chapter 7 Biasing, References, and Regulators

302

(29)

7.1 Analog Integrated Circuit Biasing

302

(5)

7.1.1 Bias Circuits

303

(2)

7.1.2 Reference Circuits

305

(1)

7.1.3 Regulator Circuits

306

(1)

7.2 Establishing Constant Transconductance

307

(3)

7.2.1 Basic Constant-Transconductance Circuit

307

(2)

7.2.2 Improved Constant-Transconductance Circuits

309

(1)

7.3 Establishing Constant Voltages and Currents

310

(11)

7.3.1 Bandgap Voltage Reference Basics

310

(4)

7.3.2 Circuits for Bandgap References

314

(5)

7.3.3 Low-Voltage Bandgap Reference

319

(1)

7.3.4 Current Reference

320

(1)

7.4 Voltage Regulation

321

(6)

7.4.1 Regulator Specifications

322

(1)

7.4.2 Feedback Analysis

322

(2)

7.4.3 Low Dropout Regulators

324

(3)

7.5 Summary of Key Points

327

(1)

7.6 References

327

(1)

7.7 Problems

328

(3)

Chapter 8 Bipolar Devices and Circuits

331

(32)

8.1 Bipolar-Junction Transistors

331

(13)

8.1.1 Basic Operation

331

(10)

8.1.2 Analog Figures of Merit

341

(3)

8.2 Bipolar Device Model Summary

344

(1)

8.3 SPICE Modeling

345

(1)

8.4 Bipolar and BICMOS Processing

346

(3)

8.4.1 Bipolar Processing

346

(1)

8.4.2 Modern SiGe BiCMOS HBT Processing

347

(1)

8.4.3 Mismatch in Bipolar Devices

348

(1)

8.5 Bipolar Current Mirrors and Gain Stages

349

(7)

8.5.1 Current Mirrors

349

(1)

8.5.2 Emitter Follower

350

(3)

8.5.3 Bipolar Differential Pair

353

(3)

8.6 Appendix

356

(3)

8.6.1 Bipolar Transistor Exponential Relationship

356

(3)

8.6.2 Base Charge Storage of an Active BJT

359

(1)

8.7 Summary of Key Points

359

(1)

8.8 References

360

(1)

8.9 Problems

360

(3)

Chapter 9 Noise and Linearity Analysis and Modelling

363

(50)

9.1 Time-Domain Analysis

363

(4)

9.1.1 Root Mean Square (rms) Value

364

(1)

9.1.2 SNR

365

(1)

9.1.3 Units of dBm

365

(1)

9.1.4 Noise Summation

366

(1)

9.2 Frequency-Domain Analysis

367

(10)

9.2.1 Noise Spectral Density

367

(2)

9.2.2 White Noise

369

(1)

9.2.3 1/f, or Flicker, Noise

370

(1)

9.2.4 Filtered Noise

371

(2)

9.2.5 Noise Bandwidth

373

(2)

9.2.6 Piecewise Integration of Noise

375

(2)

9.2.7 1/f Noise Tangent Principle

377

(1)

9.3 Noise Models for Circuit Elements

377

(10)

9.3.1 Resistors

378

(1)

9.3.2 Diodes

378

(2)

9.3.3 Bipolar Transistors

380

(1)

9.3.4 MOSFETS

380

(2)

9.3.5 Opamps

382

(1)

9.3.6 Capacitors and Inductors

382

(2)

9.3.7 Sampled Signal Noise

384

(1)

9.3.8 Input-Referred Noise

384

(3)

9.4 Noise Analysis Examples

387

(10)

9.4.1 Opamp Example

387

(3)

9.4.2 Bipolar Common-Emitter Example

390

(2)

9.4.3 CMOS Differential Pair Example

392

(3)

9.4.4 Fiber-Optic Transimpedance Amplifier Example

395

(2)

9.5 Dynamic Range Performance

397

(8)

9.5.1 Total Harmonic Distortion (THD)

398

(2)

9.5.2 Third-Order Intercept Point (IP3)

400

(2)

9.5.3 Spurious-Free Dynamic Range (SFDR)

402

(2)

9.5.4 Signal-to-Noise and Distortion Ratio (SNDR)

404

(1)

9.6 Key Points

405

(1)

9.7 References

406

(1)

9.8 Problems

406

(7)

Chapter 10 Comparators

413

(31)

10.1 Comparator Specifications

413

(2)

10.1.1 Input Offset and Noise

413

(1)

10.1.2 Hysteresis

414

(1)

10.2 Using an Opamp for a Comparator

415

(3)

10.2.1 Input-Offset Voltage Errors

417

(1)

10.3 Charge-Injection Errors

418

(8)

10.3.1 Making Charge-Injection Signal Independent

421

(1)

10.3.2 Minimizing Errors Due to Charge-Injection

421

(3)

10.3.3 Speed of Multi-Stage Comparators

424

(2)

10.4 Latched Comparators

426

(5)

10.4.1 Latch-Mode Time Constant

427

(3)

10.4.2 Latch Offset

430

(1)

10.5 Examples of CMOS and BiCMOS Comparators

431

(6)

10.5.1 Input-Transistor Charge Trapping

435

(2)

10.6 Examples of Bipolar Comparators

437

(2)

10.7 Key Points

439

(1)

10.8 References

440

(1)

10.9 Problems

440

(4)

Chapter 11 Sample-and-Hold and Translinear Circuits

444

(25)

11.1 Performance of Sample-and-Hold Circuits

444

(2)

11.1.1 Testing Sample and Holds

445

(1)

11.2 MOS Sample-and-Hold Basics

446

(6)

11.3 Examples of CMOS S/H Circuits

452

(4)

11.4 Bipolar and BiCMOS Sample-and-Holds

456

(4)

11.5 Translinear Gain Cell

460

(2)

11.6 Translinear Multiplier

462

(2)

11.7 Key Points

464

(1)

11.8 References

465

(1)

11.9 Problems

466

(3)

Chapter 12 Continuous-Time Filters

469

(68)

12.1 Introduction to Continuous-Time Filters

469

(2)

12.1.1 First-Order Filters

470

(1)

12.1.2 Second-Order Filters

470

(1)

12.2 Introduction to Gm-C Filters

471

(8)

12.2.1 Integrators and Summers

472

(2)

12.2.2 Fully Differential Integrators

474

(1)

12.2.3 First-Order Filter

475

(2)

12.2.4 Biquad Filter

477

(2)

12.3 Transconductors Using Fixed Resistors

479

(5)

12.4 CMOS Transconductors Using Triode Transistors

484

(9)

12.4.1 Transconductors Using a Fixed-Bias Triode Transistor

484

(2)

12.4.2 Transconductors Using Varying Bias-Triode Transistors

486

(5)

12.4.3 Transconductors Using Constant Drain-Source Voltages

491

(2)

12.5 CMOS Transconductors Using Active Transistors

493

(7)

12.5.1 CMOS Pair

493

(1)

12.5.2 Constant Sum of Gate-Source Voltages

494

(1)

12.5.3 Source-Connected Differential Pair

495

(1)

12.5.4 Inverter-Based

495

(2)

12.5.5 Differential-Pair with Floating Voltage Sources

497

(2)

12.5.6 Bias-Offset Cross-Coupled Differential Pairs

499

(1)

12.6 Bipolar Transconductors

500

(6)

12.6.1 Gain-Cell Transconductors

500

(1)

12.6.2 Transconductors Using Multiple Differential Pairs

501

(5)

12.7 BiCMOS Transconductors

506

(3)

12.7.1 Tunable MOS in Triode

506

(1)

12.7.2 Fixed-Resistor Transconductor with a Translinear Multiplier

507

(1)

12.7.3 Fixed Active MOS Transconductor with a Translinear Multiplier

508

(1)

12.8 Active RC and MOSFET-C Filters

509

(7)

12.8.1 Active RC Filters

510

(2)

12.8.2 MOSFET-C Two-Transistor Integrators

512

(3)

12.8.3 Four-Transistor Integrators

515

(6)

12.8.4 R-MOSFET-C Filters

521

12.9 Tuning Circuitry

516

(9)

12.9.1 Tuning Overview

517

(2)

12.9.2 Constant Transconductance

519

(1)

12.9.3 Frequency Tuning

520

(2)

12.9.4 Q-Factor Tuning

522

(1)

12.9.5 Tuning Methods Based on Adaptive Filtering

523

(2)

12.10 Introduction to Complex Filters

525

(6)

12.10.1 Complex Signal Processing

525

(1)

12.10.2 Complex Operations

526

(1)

12.10.3 Complex Filters

527

(1)

12.10.4 Frequency-Translated Analog Filters

528

(3)

12.11 Key Points

531

(1)

12.12 References

532

(2)

12.13 Problems

534

(3)

Chapter 13 Discrete-Time Signals

537

(20)

13.1 Overview of Some Signal Spectra

537

(1)

13.2 Laplace Transforms of Discrete-Time Signals

537

(4)

13.2.1 Spectra of Discrete-Time Signals

540

(1)

13.3 z-Transform

541

(2)

13.4 Downsampling and Upsampling

543

(2)

13.5 Discrete-Time Filters

545

(7)

13.5.1 Frequency Response of Discrete-Time Filters

545

(3)

13.5.2 Stability of Discrete-Time Filters

548

(2)

13.5.3 IIR and FIR Filters

550

(1)

13.5.4 Bilinear Transform

550

(2)

13.6 Sample-and-Hold Response

552

(2)

13.7 Key Points

554

(1)

13.8 References

555

(1)

13.9 Problems

555

(2)

Chapter 14 Switched-Capacitor Circuits

557

(49)

14.1 Basic Building Blocks

557

(3)

14.1.1 Opamps

557

(1)

14.1.2 Capacitors

558

(1)

14.1.3 Switches

558

(1)

14.1.4 Nonoverlapping Clocks

559

(1)

14.2 Basic Operation and Analysis

560

(10)

14.2.1 Resistor Equivalence of a Switched Capacitor

560

(1)

14.2.2 Parasitic-Sensitive Integrator

560

(5)

14.2.3 Parasitic-Insensitive Integrators

565

(4)

14.2.4 Signal-Flow-Graph Analysis

569

(1)

14.3 Noise in Switched-Capacitor Circuits

570

(2)

14.4 First-Order Filters

572

(5)

14.4.1 Switch Sharing

575

(1)

14.4.2 Fully Differential Filters

575

(2)

14.5 Biquad Filters

577

(8)

14.5.1 Low-Q Biquad Filter

577

(1)

14.5.2 High-Q Biquad Filter

577

(8)

14.6 Charge Injection

585

(3)

14.7 Switched-Capacitor Gain Circuits

588

(5)

14.7.1 Parallel Resistor-Capacitor Circuit

588

(1)

14.7.2 Resettable Gain Circuit

588

(3)

14.7.3 Capacitive-Reset Gain Circuit

591

(2)

14.8 Correlated Double-Sampling Techniques

593

(1)

14.9 Other Switched-Capacitor Circuits

594

(6)

14.9.1 Amplitude Modulator

594

(1)

14.9.2 Full-Wave Rectifier

595

(1)

14.9.3 Peak Detectors

596

(1)

14.9.4 Voltage-Controlled Oscillator

596

(2)

14.9.5 Sinusoidal Oscillator

598

(2)

14.10 Key Points

600

(1)

14.11 References

601

(1)

14.12 Problems

602

(4)

Chapter 15 Data Converter Fundamentals

606

(17)

15.1 Ideal D/A Converter

606

(2)

15.2 Ideal A/D Converter

608

(1)

15.3 Quantization Noise

609

(3)

15.3.1 Deterministic Approach

609

(1)

15.3.2 Stochastic Approach

610

(2)

15.4 Signed Codes

612

(2)

15.5 Performance Limitations

614

(6)

15.5.1 Resolution

614

(1)

15.5.2 Offset and Gain Error

615

(1)

15.5.3 Accuracy and Linearity

615

(5)

15.6 Key Points

620

(1)

15.7 References

620

(1)

15.8 Problems

620

(3)

Chapter 16 Nyquist-Rate D/A Converters

623

(23)

16.1 Decoder-Based Converters

623

(5)

16.1.1 Resistor String Converters

623

(2)

16.1.2 Folded Resistor-String Converters

625

(1)

16.1.3 Multiple Resistor-String Converters

625

(2)

16.1.4 Signed Outputs

627

(1)

16.2 Binary-Scaled Converters

628

(6)

16.2.1 Binary-Weighted Resistor Converters

629

(1)

16.2.2 Reduced-Resistance-Ratio Ladders

630

(1)

16.2.3 R-2R-Based Converters

630

(2)

16.2.4 Charge-Redistribution Switched-Capacitor Converters

632

(1)

16.2.5 Current-Mode Converters

633

(1)

16.2.6 Glitches

633

(1)

16.3 Thermometer-Code Converters

634

(6)

16.3.1 Thermometer-Code Current-Mode D/A Converters

636

(1)

16.3.2 Single-Supply Positive-Output Converters

637

(1)

16.3.3 Dynamically Matched Current Sources

638

(2)

16.4 Hybrid Converters

640

(2)

16.4.1 Resistor-Capacitor Hybrid Converters

640

(1)

16.4.2 Segmented Converters

640

(2)

16.5 Key Points

642

(1)

16.6 References

643

(1)

16.7 Problems

643

(3)

Chapter 17 Nyquist-Rate A/D Converters

646

(50)

17.1 Integrating Converters

646

(4)

17.2 Successive-Approximation Converters

650

(12)

17.2.1 DAC-Based Successive Approximation

652

(1)

17.2.2 Charge-Redistribution A/D

653

(5)

17.2.3 Resistor-Capacitor Hybrid

658

(1)

17.2.4 Speed Estimate for Charge-Redistribution Converters

658

(1)

17.2.5 Error Correction in Successive-Approximation Converters

659

(3)

17.2.6 Multi-Bit Successive-Approximation

662

(1)

17.3 Algorithmic (or Cyclic) A/D Converter

662

(3)

17.3.1 Ratio-Independent Algorithmic Converter

662

(3)

17.4 Pipelined A/D Converters

665

(8)

17.4.1 One-Bit-Per-Stage Pipelined Converter

667

(2)

17.4.2 1.5 Bit Per Stage Pipelined Converter

669

(3)

17.4.3 Pipelined Converter Circuits

672

(1)

17.4.4 Generalized k-Bit-Per-Stage Pipelined Converters

673

(1)

17.5 Flash Converters

673

(4)

17.5.1 Issues in Designing Flash A/D Converters

675

(2)

17.6 Two-Step A/D Converters

677

(3)

17.6.1 Two-Step Converter with Digital Error Correction

679

(1)

17.7 Interpolating A/D Converters

680

(3)

17.8 Folding A/D Converters

683

(4)

17.9 Time-Interleaved A/D Converters

687

(3)

17.10 Key Points

690

(1)

17.11 References

691

(1)

17.12 Problems

692

(4)

Chapter 18 Oversampling Converters

696

(42)

18.1 Oversampling without Noise Shaping

696

(6)

18.1.1 Quantization Noise Modelling

697

(1)

18.1.2 White Noise Assumption

697

(2)

18.1.3 Oversampling Advantage

699

(2)

18.1.4 The Advantage of 1-Bit D/A Converters

701

(1)

18.2 Oversampling with Noise Shaping

702

(9)

18.2.1 Noise-Shaped Delta-Sigma Modulator

703

(1)

18.2.2 First-Order Noise Shaping

704

(2)

18.2.3 Switched-Capacitor Realization of a First-Order A/D Converter

706

(1)

18.2.4 Second-Order Noise Shaping

706

(2)

18.2.5 Noise Transfer-Function Curves

708

(1)

18.2.6 Quantization Noise Power of 1-Bit Modulators

709

(1)

18.2.7 Error-Feedback Structure

709

(2)

18.3 System Architectures

711

(3)

18.3.1 System Architecture of Delta-Sigma A/D Converters

711

(2)

18.3.2 System Architecture of Delta-Sigma D/A Converters

713

(1)

18.4 Digital Decimation Filters

714

(4)

18.4.1 Multi-Stage

715

(2)

18.4.2 Single Stage

717

(1)

18.5 Higher-Order Modulators

718

(3)

18.5.1 Interpolative Architecture

718

(1)

18.5.2 Multi-Stage Noise Shaping (MASH) Architecture

719

(2)

18.6 Bandpass Oversampling Converters

721

(1)

18.7 Practical Considerations

722

(5)

18.7.1 Stability

722

(1)

18.7.2 Linearity of Two-Level Converters

723

(2)

18.7.3 Idle Tones

725

(1)

18.7.4 Dithering

726

(1)

18.7.5 Opamp Gain

726

(1)

18.8 Multi-Bit Oversampling Converters

727

(3)

18.8.1 Dynamic Element Matching

727

(1)

18.8.2 Dynamically Matched Current Source D/S Converters

728

(1)

18.8.3 Digital Calibration A/D Converter

728

(1)

18.8.4 A/D with Both Multi-Bit and Single-Bit Feedback

729

(1)

18.9 Third-Order A/D Design Example

730

(2)

18.10 Key Points

732

(2)

18.11 References

734

(1)

18.12 Problems

735

(3)

Chapter 19 Phase-Locked Loops

738

(49)

19.1 Basic Phase-Locked Loop Architecture

738

(10)

19.1.1 Voltage Controlled Oscillator

739

(1)

19.1.2 Divider

740

(1)

19.1.3 Phase Detector

741

(5)

19.1.4 Loop Filer

746

(1)

19.1.5 The PLL in Lock

747

(1)

19.2 Linearized Small-Signal Analysis

748

(8)

19.2.1 Second-Order PLL Model

749

(2)

19.2.2 Limitations of the Second-Order Small-Signal Model

751

(3)

19.2.3 PLL Design Example

754

(2)

19.3 Jitter and Phase Noise

756

(9)

19.3.1 Period Jitter

760

(1)

19.3.2 P-Cycle Jitter

761

(1)

19.3.3 Adjacent Period Jitter

761

(1)

19.3.4 Other Spectral Representations of Jitter

762

(2)

19.3.5 Probability Density Function of Jitter

764

(1)

19.4 Electronic Oscillators

765

(12)

19.4.1 Ring Oscillators

766

(5)

19.4.2 LC Oscillators

771

(1)

19.4.3 Phase Noise of Oscillators

772

(5)

19.5 Jitter and Phase Noise in PLLS

777

(4)

19.5.1 Input Phase Noise and Divider Phase Noise

777

(1)

19.5.2 VCO Phase Noise

778

(1)

19.5.3 Loop Filter Noise

779

(2)

19.6 Key Points

781

(1)

19.7 References

782

(1)

19.8 Problems

782

(5)

Index

787

Tony Chan Carusone completed the B.A.Sc. and Ph.D. degrees at the University of Toronto in 1997 and 2002 respectvely, during which tme he received the Governor-General's Silver Medal. Since 2001, he has been with the Department of Electrical and Computer Engineering at the University of Toronto where he is currently an Associate Professor. From 2002 to 2007 he held the Canada Research Chair in Integrated Systems and in 2008 was a visitng researcher at the University of Pavia. He is also an occasional consultant to industry, having worked for Snowbush Inc., Gennum Corp., and Intel Corp., all in the area of high-speed links. Tony was a co-author of the best student papers at both the 2007 and 2008 Custom Integrated Circuits Conference and the best paper at the 2005 Compound Semiconductor Integrated Circuits Symposium. He is an appointed member of the Administratve Commitee of the IEEE Solid-State Circuits Society, a member and past chair of the Analog Signal Processing Technical Commitee for the IEEE Circuits and Systems Society, and a past member and chair of the Wireline Communicatons subcommitee of the Custom Integrated Circuits Conference. He has served as a guest editor for both the IEEE Journal of Solid-State Circuits and the IEEE Transactons on Circuits and Systems I: Regular Papers, and served on the editorial board of the IEEE Transactons on Circuits and Systems II: Express Briefs from 2006 untl 2009 when he was Editor-in-Chief.

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