| Overview of SEMI and the IEEE |
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Keynote: The Challenges of Enabling Sub 100nm Technology |
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| Advanced FEOL Processing |
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Invited: In-Line Electrical Characterization Of Ultrathin Gate Dielectric Films |
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1 | (5) |
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Alternative Smart-cut-like Process for Ultra-thin SOI Fabrication |
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6 | (5) |
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A Manufacturable Shallow Trench Isolation Process for Sub-0.2um DRAM Technologies |
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11 | (6) |
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Controlling Lithographic Imaging Performance at Sub-100 nm CD with Optical Measurements |
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17 | (4) |
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A Robust Shallow Trench Isolation (STI) with SiN Pull-Back Process for Advanced DRAM Technology |
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21 | (6) |
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Flexible Polishing Surface (FPS) vs Rigid Polishing Surface (RPS) in CMP: Pros and Cons |
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27 | (6) |
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| Fab Dynamics |
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Invited: A Simulation of Periodical Priority Dispatching of WIP for Product-mix Fabrication |
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33 | (5) |
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Characterization of Film Uniformity in LPCVD TEOS Vertical Furnace |
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38 | (5) |
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Fulfilling the Speed Imperative: New Product Development and Enterprise Project Management in the New Economy |
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43 | (6) |
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Distributed WIP Control in Advanced Semiconductor Manufacturing |
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49 | (6) |
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Dynamic Deployment Modeling Tool for Photolithography WIP Management |
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55 | (4) |
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Automated System Infrastructure to Facilitate Design of Experiments (DOE) Data Analysis |
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59 | (5) |
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| Yield Enhancement Tools and Methods |
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Invited: Wafer Back Side Applications for Yield Protection and Enhancement |
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64 | (8) |
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Methodology for Targeted Defect Reduction and Inspection Optimization |
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72 | (5) |
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A Statistical Method for Reducing Systematic Defects in the Initial Stages of Production |
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77 | (5) |
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Yield Prediction Using Critical Area Analysis with Inline Defect Data |
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82 | (5) |
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Accuracy of Yield Impact Calculation Based on Kill Ratio |
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87 | (5) |
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Advanced Defect Detection Methods for CMP Process Modules in Semiconductor Manufacturing |
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92 | (6) |
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| Process Control Methodology |
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Invited: Advanced Process Control: Benefits For Photolithography Process Control |
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98 | (3) |
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Advance Process Control Solutions for Semiconductor Manufacturing |
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101 | (6) |
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Arulkumar Shanmugasundram |
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Shallow Trench Isolation Run-to-Run Control Project at Infineon Technologies Richmond |
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107 | (6) |
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HandMon-ISPM: Handling Monitoring in a Loading Station of a Furnace |
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113 | (6) |
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Line-profile and Critical Dimension Measurements Using a Normal Incidence Optical Metrology System |
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119 | (6) |
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Development and Deployment of a Multi-Component Advanced Process Control System for an Epitaxy Tool |
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125 | (6) |
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| Poster Session |
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BF2+ Implant: A Fluorine Bubble Induced ET Failure |
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131 | (3) |
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Direct Wafer Temperature Measurements for Etch Chamber Diagnostics and Process Control |
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134 | (6) |
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Epi Resistivity Profiles Without Wafer Damage |
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140 | (4) |
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Failure Rate and Yield Limiting W-plug Corrosion Diagnosis using Characterization Test Vehicles |
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144 | (6) |
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Innovations for Economical 300/450mm IC Fabricators |
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150 | (5) |
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KFAB Decision Site: An Interactive, Exploratory Yield Analysis Framework |
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155 | (4) |
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Manufacturing Execution System (MES) Operating System Migration to Integrate Leading-Edge Methodologies and Leverage Emerging Technologies |
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159 | (6) |
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A MEMS-Based, High Sensitivity Pressure Sensor for Ultraclean Semiconductor Applications |
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165 | (4) |
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Optimization of Oxide Spacer Etch Process for 0.35 um CMOS Transistor |
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169 | (3) |
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Plasma Chemical Cleaning of Chip Carrier in a Downstream Hollow Cathode Discharge |
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172 | (5) |
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Pt/PZT/Pt and Pt/Barrier Stack Etches for MEMS Devices in a Dual Frequency High Density Plasma Reactor |
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177 | (7) |
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Reduce Scrap: Control Oxide Loss in SC1 |
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184 | (3) |
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Robust Optimization of Experimental Designs in Microelectronics Processes using a Stochastic Approach |
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187 | (6) |
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Spelunking in the Data Mine: On Data Mining as an Analysis Tool for the Optimization of Microprocessor Speed |
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193 | (6) |
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STI Trench Recess Feed Forward Control for Self-Aligned Contact Processes to Reduce PMOS Contact Leakage |
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199 | (3) |
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Tool Commonality Analysis for Yield Enhancement |
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202 | (4) |
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Ultra-dilute Silicon Wafer Clean Chemistry for Fabrication of RF Microwave Devices |
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206 | (6) |
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Wafer Level Packaging and 3D Interconnect for IC Technology |
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212 | (6) |
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Keynote: Semiconductor Manufacturing Outlook: Growth...When? Where? Why? |
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| Resource Productivity Management |
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Invited: Equipment Productivity Improvement via Inline Qualification Implementation |
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218 | (5) |
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Data Acquistion Approach for Real-time Equipment Monitoring and Control |
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223 | (5) |
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Semiconductor Fab Maintenance Challenge and BKM in Downturn Economy |
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228 | (3) |
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Development of National Skill Standards for Technicians Working in Highly Automated (300mm) Environments |
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231 | (3) |
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Modeling Staffing Requirements within a Semiconductor Manufacturing Environment |
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234 | (6) |
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| Yield Modeling, Analysis and Enhancement |
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Invited: A Manufacturing Perspective of Physical Design Characterization |
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240 | (7) |
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Beyond DFM: When Manufacturability has to be Guaranteed by Design |
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247 | (5) |
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Yield/Reliability Enhancement using Automated Minor Layout Modifications |
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252 | (10) |
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Application of Decision Trees for Integrated Circuit Yield Improvement |
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262 | (4) |
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Statistical Modeling and Analysis of Wafer Test Fail Counts |
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266 | (6) |
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| Defect Free Manufacturing |
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Invited: Physical Removal of Nano-Scale Defects from Surfaces |
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272 | (6) |
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Planarization Yield Limiters for Wafer-Scale 3D ICs |
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278 | (6) |
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An Approach for Improving Yield with Intentional Defects |
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284 | (5) |
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Transporting FOUPs as a Driver for ESD-Induced EMI |
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289 | (6) |
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An Approach to Recipe Control in Wafer Fab |
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295 | (4) |
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Keynote: Achieving the Benefits of 300mm |
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| Contamination Free Manufacturing |
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Invited: The Effect of Hafnium or Zirconium Contamination on MOS Processes |
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299 | (5) |
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Cleaning of High Aspect Ratio Submicron Trenches |
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304 | (5) |
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Study of Airborne Molecular Contamination in Minienvironments |
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309 | (5) |
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A Model for Outgassing of Organic Contamination from Wafer Carrier Boxes |
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314 | (5) |
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Trace Gas Analysis by Diode Laser Cavity Ring-Down Spectroscopy |
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319 | (5) |
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| Cost Management Methodologies |
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Yield Learning and the Sources of Profitability in Semiconductor Manufacturing and Process Development |
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324 | (6) |
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A Hierarchical Approach to Cost Analysis for Next Generation Semiconductor Processes |
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330 | (6) |
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ABC Modeling: Advanced Features |
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336 | (4) |
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Water Usage Reduction in a Semiconductor Fabricator |
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340 | (7) |
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Spare Parts Expense Management System |
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347 | (4) |
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Keynote: Silicon Micromachines for Lightwave Networks: The Little Machines that are Making it BIG!! |
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| Advanced BEOL Processing |
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Characterization of Copper Voids in Dual Damascene Processes |
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351 | (5) |
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Manufacturing Implementation of Low-k Dielectrics for Copper Damascene Technology |
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356 | (6) |
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Surfacant Behavior and Study in Slurry |
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362 | (6) |
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Sidewall Clean Effect Upon Titanium Salicide Filaments |
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368 | (4) |
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Clint Montgomery Randy Pak |
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Supercritical Fluid Processes for Semiconductor Device Fabrication |
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372 | (4) |
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Opitimization of Resist Strip Recipe for Aluminum Metal Etch Processes |
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376 | (5) |
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| Advanced Metrology |
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Invited: Scanner Focus and CD Response Characterization Metrology for Sub 180nm Lithography |
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381 | (9) |
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Comprehensive and Easy to Use SEM Analysis Structures for BiCMOS Process Development |
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390 | (6) |
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Metro-3D: An Efficient Three Dimensional Wafer Inspection Simulator for Next Generation Lithography |
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396 | (6) |
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Automated Residual Metal Inspection |
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402 | (6) |
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The Implementation of AFM for Process Monitoring and Metrology in Trench MOSFET Device Manufacturing |
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408 | (7) |
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Neural Network Modeling of Reactive Ion Etching Using Principal Component Analysis of Optical Emission Spectroscopy Data |
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415 | (6) |
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| Biographies of Speakers |
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