This book presents an evaluation methodology to design future FPGA fabrics incorporating hard embedded blocks (HEBs) to accelerate applications. This methodology will be useful for selection of blocks to be embedded into the fabric and for evaluating the performance gain that can be achieved by such an embedding. The authors illustrate the use of their methodology by studying the impact of HEBs on two important bioinformatics applications: protein docking and genome assembly. The book also explains how the respective HEBs are designed and how hardware implementation of the application is done using these HEBs. It shows that significant speedups can be achieved over pure software implementations by using such FPGA-based accelerators. The methodology presented in this book may also be used for designing HEBs for accelerating software implementations in other domains besides bioinformatics. This book will prove useful to students, researchers, and practicing engineers alike.
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3 | (1) |
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1.2 DSE of Application Acceleration Using FPGAs with Hard Embedded Blocks |
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1.2.1 Challenges in Design Space Exploration |
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2.1 Accelerator Architectures |
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2.1.1 Challenges in Designing Accelerators |
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2.2 FPGA-Based Acceleration |
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2.2.2 FPGA-Based Accelerators |
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2.2.3 Hard Embedded Blocks in FPGAs |
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17 | (7) |
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18 | (3) |
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21 | (3) |
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24 | (5) |
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24 | (5) |
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3 Methodology for Implementing Accelerators |
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29 | (10) |
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3.1 Design Space Exploration |
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29 | (3) |
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3.2 Tools for Carrying Out Design Space Exploration |
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32 | (2) |
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32 | (2) |
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3.3 Design of FPGAs with Hard Embedded Blocks |
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34 | (1) |
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3.4 Methodology for Designing FPGAs with Custom Hard Embedded Blocks |
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35 | (2) |
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3.4.1 Performance Estimation of Application Acceleration |
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37 | (1) |
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4 FPGA-Based Acceleration of Protein Docking |
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39 | (6) |
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4.1.1 Shape Complementarity |
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41 | (2) |
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4.1.2 Electrostatic Complementarity |
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43 | (2) |
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45 | (1) |
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45 | (1) |
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4.2.2 Earlier Attempts to Speedup |
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46 | (1) |
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4.3 Choice of Single Precision |
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4.4 FPGA Resource Mapping |
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50 | (3) |
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53 | (2) |
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54 | (1) |
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5 FPGA-Based Acceleration of De Novo Genome Assembly |
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55 | (3) |
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5.1.1 Related Work with FPGA-Based Acceleration |
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58 | (7) |
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5.2.2 Algorithm to Architecture |
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5.3 Hardware Implementation |
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5.3.1 FASTA File to Bit File Converter |
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5.3.2 Processing Element Design |
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5.4 Results and Discussion |
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5.4.1 Resource Utilization and Operating Frequency |
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5.4.2 Speedups over Software |
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74 | (3) |
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77 | (1) |
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78 | (3) |
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6 Design of Accelerators with Hard Embedded Blocks |
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6.1 Acceleration of FTDock Using Hard Embedded Blocks |
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6.1.2 FPGA Resource Mapping |
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6.1.3 Hard Embedded Block Design Space Exploration |
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6.1.4 Results and Discussion |
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6.2 Acceleration of Genome Assembly Using Hard Embedded Blocks |
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90 | (8) |
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91 | (1) |
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6.2.2 FPGA Resource Mapping |
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91 | (1) |
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6.2.3 Hard Embedded Block Design Space Exploration |
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92 | (2) |
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6.2.4 Results and Discussion |
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94 | (4) |
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98 | (3) |
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7 System-Level Design Space Exploration |
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7.2 Design Space Exploration |
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7.2.2 Hardware Implementation |
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105 | (2) |
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7.2.3 System-C Implementation |
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7.3 Multi-FPGA Implementation |
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7.4 Results and Discussion |
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116 | (1) |
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| Index |
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121 | |
B. Sharat Chandra Varma is Research Associate in the Department of Electrical & Electronic Engineering at The University of Hong Kong, Hong Kong. He obtained his PhD from IIT Delhi, New Delhi. He completed his B.E. (2003) from Visvesvaraya Technological University Karnataka and MSc. (2007) from Manipal University, Karnataka. His research interest areas are re-configurable computing, FPGA, hardware-software co-design, hardware accelerators, and computer architecture. Dr. Varma has over 10 years of research and industrial experience and has several journal publications to his credit.
Kolin Paul is presently Associate Professor with the department of Computer Science and Engineering at Indian Institute of Technology Delhi, New Delhi. His academic degrees include M.Sc. (1995) from Jadavpur University and Ph.D. (2002) from Bengal Engineering College, Calcutta, India. Dr. Paul has several papers published in refereed journal and conference proceedings.
M. Balakrishnan isa Professor in the CSE Department at IIT Delhi, New Delhi, India. He completed his PhD in 1984 from IIT Delhi. He has 16 journal articles, 63 refereed conference publications, one book chapter and two patents to his credit. Dr. Balakrishnan has been a part of many research projects and consultancies from leading EDA/VLSI companies. He is a reviewer for major international journals, a member of key academic bodies. He has supervised 8 PhDs, 3 MS(R) and 78 M.Tech students. His areas of specialization are behavioral and system level synthesis, system level design and modeling, computer architecture, hardware-software co-design, embedded system design, and assistive devices for the visually impaired.
