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1 | (18) |
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2 | (2) |
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3 | (1) |
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3 | (1) |
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4 | (3) |
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5 | (1) |
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6 | (1) |
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1.3 Energy Scavenging Techniques |
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7 | (3) |
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1.3.1 Super-capacitor Size Estimation |
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9 | (1) |
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1.3.2 Battery Size Estimation |
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10 | (1) |
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1.4 General Wireless Node Requirements |
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10 | (4) |
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10 | (1) |
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11 | (1) |
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1.4.3 Range and Sensitivity |
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11 | (2) |
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1.4.4 Turn-on and Synchronization Time |
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13 | (1) |
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1.4.5 Technology Comparison and Trade-offs |
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13 | (1) |
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14 | (2) |
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1.5.1 Research in Industries |
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14 | (1) |
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1.5.2 Research in Universities |
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15 | (1) |
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1.6 The Objectives of This Book |
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16 | (1) |
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17 | (2) |
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2 System-Level and Architectural Trade-offs |
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19 | (26) |
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2.1 Modulation Schemes for Ultra-low Power Wireless Nodes |
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19 | (12) |
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2.1.1 Impulse Radio Transceivers |
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20 | (1) |
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2.1.2 Back-scattering for RFID Applications |
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21 | (1) |
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21 | (1) |
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22 | (1) |
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2.1.5 Spread-Spectrum Systems |
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22 | (9) |
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31 | (5) |
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2.2.1 Constant Duty-Cycle |
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33 | (1) |
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2.2.2 Constant Time Between Two Consecutive Transmissions |
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34 | (2) |
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2.3 Transmitter Architectures |
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36 | (3) |
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36 | (1) |
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2.3.2 Two-Step Conversion |
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37 | (1) |
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38 | (1) |
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2.4 Receiver Architectures |
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39 | (3) |
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39 | (1) |
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40 | (1) |
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41 | (1) |
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42 | (3) |
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3 FHSS Systems: State-of-the-Art and Power Trade-offs |
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45 | (48) |
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45 | (6) |
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3.1.1 Stepped Serial Search |
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47 | (1) |
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3.1.2 Matched Filter Acquisition |
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48 | (1) |
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3.1.3 Two-Level Acquisition |
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49 | (1) |
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3.1.4 Acquisition Methods Comparison |
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49 | (2) |
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3.2 State-of-the-Art FHSS Systems |
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51 | (3) |
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3.3 FH Synthesizer Architectures |
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54 | (1) |
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3.4 Specifications for Ultra-low-power Frequency-Hopping Synthesizers |
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55 | (7) |
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56 | (2) |
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58 | (4) |
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3.5 PLL Power Estimation Model |
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62 | (8) |
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62 | (2) |
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64 | (1) |
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64 | (1) |
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3.5.4 PFD and Frequency Divider |
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65 | (1) |
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3.5.5 Complete PLL Power Model |
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65 | (5) |
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3.6 DDFS Power Estimation Model |
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70 | (18) |
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3.6.1 DDFS Specifications for Frequency-Hopping Synthesizers |
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70 | (3) |
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3.6.2 AA-filter Power Consumption |
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73 | (2) |
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3.6.3 Phase Accumulator and ROM Power Consumption Estimation |
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75 | (3) |
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3.6.4 DAC Power Consumption Estimation |
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78 | (7) |
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3.6.5 Power Dissipation of the Whole DDFS |
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85 | (3) |
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3.7 Summarizing Discussion |
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88 | (2) |
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90 | (3) |
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4 A One-Way Link Transceiver Design |
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93 | (74) |
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4.1 General Guidelines for Transmitter Design |
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93 | (1) |
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4.2 Transmitter Architecture |
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94 | (39) |
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4.2.1 Concepts and Block Diagrams |
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96 | (3) |
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4.2.2 Frequency Planning and Pre-distortion |
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99 | (7) |
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4.2.3 Transmitter Specifications |
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106 | (5) |
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4.2.4 Oscillator-Divider Based Architecture |
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111 | (19) |
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4.2.5 Power-VCO Based Architecture |
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130 | (3) |
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4.3 Receiver Architecture |
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133 | (18) |
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4.3.1 RX-TX Center Frequency Alignment Algorithm |
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134 | (9) |
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4.3.2 Residual Frequency Error after Pre-distortion |
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143 | (8) |
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4.4 Implementation and Experimental Results |
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151 | (13) |
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4.4.1 TX Node Implementation |
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151 | (8) |
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159 | (1) |
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4.4.3 Measurement Results |
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159 | (5) |
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164 | (1) |
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164 | (3) |
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5 A Two-Way Link Transceiver Design |
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167 | (52) |
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5.1 Transmitter Design General Guidelines |
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168 | (1) |
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5.2 Transmitter Architecture |
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169 | (1) |
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170 | (19) |
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5.3.1 Baseband Frequency Hopping Synthesizer Specifications |
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171 | (1) |
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5.3.2 Baseband Frequency-Hopping Synthesizer Architecture |
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172 | (7) |
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5.3.3 Baseband Frequency Hopping Synthesizer Implementation |
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179 | (10) |
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5.4 Generation of a 288-MHz Reference Clock |
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189 | (2) |
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5.5 Receiver Design at System Level |
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191 | (16) |
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5.5.1 Receiver Link Budget Analysis |
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192 | (10) |
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5.5.2 Receiver Building Blocks State-of-the-Art |
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202 | (5) |
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5.6 Simulation and Experimental Results |
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207 | (10) |
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5.6.1 Baseband Synthesizer Without the LP-notch Filter |
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208 | (3) |
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5.6.2 Stand Alone Tunable LP-notch Filter |
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211 | (1) |
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5.6.3 Complete Frequency Hopping Baseband Synthesizer |
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212 | (2) |
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214 | (3) |
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217 | (2) |
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6 Summary and Conclusions |
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219 | (4) |
Appendix Walsh Based Harmonic Rejection Sensitivity Analysis |
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223 | (4) |
References |
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227 | (6) |
Index |
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233 | |