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Architectures and Synthesizers for Ultra-low Power Fast Frequency-Hopping WSN Radios 2011 ed. [Kõva köide]

  • Formaat: Hardback, 236 pages, kõrgus x laius: 235x155 mm, kaal: 1160 g, XII, 236 p., 1 Hardback
  • Sari: Analog Circuits and Signal Processing
  • Ilmumisaeg: 08-Dec-2010
  • Kirjastus: Springer
  • ISBN-10: 9400701829
  • ISBN-13: 9789400701823
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  • Formaat: Hardback, 236 pages, kõrgus x laius: 235x155 mm, kaal: 1160 g, XII, 236 p., 1 Hardback
  • Sari: Analog Circuits and Signal Processing
  • Ilmumisaeg: 08-Dec-2010
  • Kirjastus: Springer
  • ISBN-10: 9400701829
  • ISBN-13: 9789400701823
Teised raamatud teemal:
This book covers architectural and circuit level solutions for ultra-low power, robust,  uni-directional and bi-directional radio links. It guides the reader through the system, circuit and technology trade-offs faced in the design of communication systems.

Wireless sensor networks have the potential to become the third wireless revolution after wireless voice networks in the 80s and wireless data networks in the late 90s. Unfortunately, radio power consumption is still a major bottleneck to the wide adoption of this technology. Different directions have been explored to minimize the radio consumption, but the major drawback of the proposed solutions is a reduced wireless link robustness.The primary goal of Architectures and Synthesizers for Ultra-low Power Fast Frequency-Hopping WSN Radios is to discuss, in detail, existing and new architectural and circuit level solutions for ultra-low power, robust, uni-directional and bi-directional radio links.Architectures and Synthesizers for Ultra-low Power Fast Frequency-Hopping WSN Radios guides the reader through the many system, circuit and technology trade-offs he will be facing in the design of communication systems for wireless sensor networks. Finally, this book, through different examples realized in both advanced CMOS and bipolar technologies opens a new path in the radio design, showing how radio link robustness can be guaranteed by techniques that were previously exclusively used in radio systems for middle or high end applications like Bluetooth and military communications while still minimizing the overall system power consumption.
1 Introduction
1(18)
1.1 Application Field
2(2)
1.1.1 One-Way Link
3(1)
1.1.2 Two-Way Link
3(1)
1.2 System Requirements
4(3)
1.2.1 One-Way Link
5(1)
1.2.2 Two-Way Link
6(1)
1.3 Energy Scavenging Techniques
7(3)
1.3.1 Super-capacitor Size Estimation
9(1)
1.3.2 Battery Size Estimation
10(1)
1.4 General Wireless Node Requirements
10(4)
1.4.1 Link Robustness
10(1)
1.4.2 Data Rate
11(1)
1.4.3 Range and Sensitivity
11(2)
1.4.4 Turn-on and Synchronization Time
13(1)
1.4.5 Technology Comparison and Trade-offs
13(1)
1.5 State of the Art
14(2)
1.5.1 Research in Industries
14(1)
1.5.2 Research in Universities
15(1)
1.6 The Objectives of This Book
16(1)
1.7 Outline of the Book
17(2)
2 System-Level and Architectural Trade-offs
19(26)
2.1 Modulation Schemes for Ultra-low Power Wireless Nodes
19(12)
2.1.1 Impulse Radio Transceivers
20(1)
2.1.2 Back-scattering for RFID Applications
21(1)
2.1.3 Sub-sampling
21(1)
2.1.4 Super-regenerative
22(1)
2.1.5 Spread-Spectrum Systems
22(9)
2.2 Optimal Data-Rate
31(5)
2.2.1 Constant Duty-Cycle
33(1)
2.2.2 Constant Time Between Two Consecutive Transmissions
34(2)
2.3 Transmitter Architectures
36(3)
2.3.1 Direct Conversion
36(1)
2.3.2 Two-Step Conversion
37(1)
2.3.3 Offset PLL
38(1)
2.4 Receiver Architectures
39(3)
2.4.1 Zero-IF
39(1)
2.4.2 Super-heterodyne
40(1)
2.4.3 Low-IF
41(1)
2.5 Conclusions
42(3)
3 FHSS Systems: State-of-the-Art and Power Trade-offs
45(48)
3.1 Synchronization
45(6)
3.1.1 Stepped Serial Search
47(1)
3.1.2 Matched Filter Acquisition
48(1)
3.1.3 Two-Level Acquisition
49(1)
3.1.4 Acquisition Methods Comparison
49(2)
3.2 State-of-the-Art FHSS Systems
51(3)
3.3 FH Synthesizer Architectures
54(1)
3.4 Specifications for Ultra-low-power Frequency-Hopping Synthesizers
55(7)
3.4.1 PLL Based
56(2)
3.4.2 DDFS Based
58(4)
3.5 PLL Power Estimation Model
62(8)
3.5.1 VCO
62(2)
3.5.2 Loop Filter
64(1)
3.5.3 Charge Pump
64(1)
3.5.4 PFD and Frequency Divider
65(1)
3.5.5 Complete PLL Power Model
65(5)
3.6 DDFS Power Estimation Model
70(18)
3.6.1 DDFS Specifications for Frequency-Hopping Synthesizers
70(3)
3.6.2 AA-filter Power Consumption
73(2)
3.6.3 Phase Accumulator and ROM Power Consumption Estimation
75(3)
3.6.4 DAC Power Consumption Estimation
78(7)
3.6.5 Power Dissipation of the Whole DDFS
85(3)
3.7 Summarizing Discussion
88(2)
3.8 Conclusions
90(3)
4 A One-Way Link Transceiver Design
93(74)
4.1 General Guidelines for Transmitter Design
93(1)
4.2 Transmitter Architecture
94(39)
4.2.1 Concepts and Block Diagrams
96(3)
4.2.2 Frequency Planning and Pre-distortion
99(7)
4.2.3 Transmitter Specifications
106(5)
4.2.4 Oscillator-Divider Based Architecture
111(19)
4.2.5 Power-VCO Based Architecture
130(3)
4.3 Receiver Architecture
133(18)
4.3.1 RX-TX Center Frequency Alignment Algorithm
134(9)
4.3.2 Residual Frequency Error after Pre-distortion
143(8)
4.4 Implementation and Experimental Results
151(13)
4.4.1 TX Node Implementation
151(8)
4.4.2 RG Implementation
159(1)
4.4.3 Measurement Results
159(5)
4.4.4 Benchmarking
164(1)
4.5 Conclusions
164(3)
5 A Two-Way Link Transceiver Design
167(52)
5.1 Transmitter Design General Guidelines
168(1)
5.2 Transmitter Architecture
169(1)
5.3 Synthesizer Design
170(19)
5.3.1 Baseband Frequency Hopping Synthesizer Specifications
171(1)
5.3.2 Baseband Frequency-Hopping Synthesizer Architecture
172(7)
5.3.3 Baseband Frequency Hopping Synthesizer Implementation
179(10)
5.4 Generation of a 288-MHz Reference Clock
189(2)
5.5 Receiver Design at System Level
191(16)
5.5.1 Receiver Link Budget Analysis
192(10)
5.5.2 Receiver Building Blocks State-of-the-Art
202(5)
5.6 Simulation and Experimental Results
207(10)
5.6.1 Baseband Synthesizer Without the LP-notch Filter
208(3)
5.6.2 Stand Alone Tunable LP-notch Filter
211(1)
5.6.3 Complete Frequency Hopping Baseband Synthesizer
212(2)
5.6.4 Benchmarking
214(3)
5.7 Conclusions
217(2)
6 Summary and Conclusions
219(4)
Appendix Walsh Based Harmonic Rejection Sensitivity Analysis 223(4)
References 227(6)
Index 233