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Asian Test Symposium (Ats) 11th [Pehme köide]

  • Formaat: Paperback / softback, 437 pages, illustrations
  • Ilmumisaeg: 31-Dec-2002
  • Kirjastus: IEEE Computer Society Press,U.S.
  • ISBN-10: 0769518257
  • ISBN-13: 9780769518251
Teised raamatud teemal:
Asian Test Symposium (Ats) 11thSuurem pilt
  • Formaat: Paperback / softback, 437 pages, illustrations
  • Ilmumisaeg: 31-Dec-2002
  • Kirjastus: IEEE Computer Society Press,U.S.
  • ISBN-10: 0769518257
  • ISBN-13: 9780769518251
Teised raamatud teemal:
Püsilink: https://www.kriso.ee/db/9780769518251.html
Märksõnad:
Held in Guam in November of 2002, the symposium on the test technologies and research issues related to silicon chip production, resulted in the 74 papers presented here. The papers are organized into sections related to the symposium sessions on test generation, on-line testing, analog and mixed signal testing, test set compaction, design for testability, memory testing, delay fault testing, test synthesis, crosstalk fault testing, built-in self test, fault-tolerance, fault detection and diagnosis, software testing, test strategies and case studies for system-on-Chip in industries, test power reduction, verification and simulation, test systems, and current testing. Annotation c. Book News, Inc., Portland, OR (booknews.com)
General Chair's Message xi
Program Chair's Message xii
ATS'01 Best Paper Award xiii
ATS Steering Committee xiv
Organizing Committee xv
Program Committee and Voluntary Reviewers xvi
TTTC Activities Board xix
Session 1A: Test Generation
On Generating High Quality Tests for Transition Faults
1(8)
Y. Shao
I. Pomeranz
S. Reddy
Exact Computation of Maximally Dominating Faults and Its Application to n-Detection Tests
9(6)
I. Polian
I. Pomeranz
B. Becker
Maximum Distance Testing
15(6)
S. Xu
J. Chen
Session 1B: On-Line Testing
High Precision Result Evaluation of VLSI
21(6)
J. Hirase
A Totally Self-Checking Dynamic Asynchronous Datapath
27(6)
J.-L. Yang
C.-S. Choy
C.-F. Chan
K.-P. Pun
Non-intrusive Design of Concurrently Self-Testable FSMs
33(6)
P. Drineas
Y. Makris
Session 1C: Analog and Mixed Signal Testing
Test Limitations of Parametric Faults in Analog Circuits
39(6)
J. Savir
Z. Guo
Effects of Amplitude Modulation in Jitter Tolerance Measurements of Communication Devices
45(4)
M. Ishida
T. Yamaguchi
M. Soma
H. Musha
On-Chip Analog Response Extraction with 1-Bit ΣΔ Modulators
49(6)
H.-C. Hong
J.-L. Huang
K.-T. Cheng
C.-W. Wu
Session 2A: Test Set Compaction
A State Reduction Method for Non-scan Based FSM Testing with Don't Care Inputs Identification Technique
55(6)
T. Hosokawa
H. Date
M. Muraoka
Improving the Efficiency of Static Compaction Based on Chronological Order Enumeration of Test Sequences
61(6)
I. Pomeranz
S. Reddy
Test Data Compression Using Don't-Care Identification and Statistical Encoding
67(6)
S. Kajihara
K. Taniguchi
K. Miyase
I. Pomeranz
S. Reddy
Session 2B: Design for Testability
Design for Two-Pattern Testability of Controller-Data Path Circuits
73(7)
Md. Altaf-Ul-Amin
S. Ohtake
H. Fujiwara
MD-SCAN Method for Low Power Scan Testing
80(6)
T. Yoshida
M. Watari
Non-scan Design for Testability Based on Fault Oriented Conflict Analysis
86(6)
D. Xiang
S. Gu
H. Fujiwara
Session 2C: Memory Testing 1
Specification and Design of a New Memory Fault Simulator
92(6)
A. Benso
S. Di Carlo
G. Di Natale
P. Prinetto
DRAM Specific Approximation of the Faulty Behavior of Cell Defects
98(6)
Z. Al-Ars
Ad J. van de Goor
An Access Timing Measurement Unit of Embedded Memory
104(6)
S.-R. Lee
M.-J. Hsiao
T.-Y. Chang
Session 3A: Delay Fault Testing
A Partitioning and Storage Based Built-in Test Pattern Generation Method for Delay Faults in Scan Circuits
110(6)
I. Pomeranz
S. Reddy
Optimal Seed Generation for Delay Fault Detection BIST
116(6)
L. Tong
K. Suzuki
H. Ito
On-Chip Tap-Delay Measurements for a Digital Delay-Line Used in High-Speed Inter-Chip Data Communications
122(6)
O. Petre
H. Kerkhoff
Session 3B: Test Synthesis
A Scheduling Method in High-Level Synthesis for Acyclic Partial Scan Design
128(6)
T. Inoue
T. Miura
A. Tamura
H. Fujiwara
Test Requirement Analysis for Low Cost Hierarchical Test Path Construction
134(6)
Y. Makris
A. Orailoglu
Testable Realizations for ESOP Expressions of Logic Functions
140(5)
P. Zhongliang
Session 3C: Memory Testing 2
DPSC SRAM Transparent Test Algorithm
145(6)
H.-S. Kim
S. Kang
Tests for Word-Oriented Content Addressable Memories
151(6)
Z. Xuemei
Y. Yizheng
C. Chunxu
A High Performance IDDQ Testable Cache for Scaled CMOS Technologies
157(6)
S. Bhunia
H. Li
K. Roy
Session 4A: Crosstalk Fault Testing
Enhanced Crosstalk Fault Model and Methodology to Generate Tests for Arbitrary Inter-core Interconnect Topology
163(7)
W. Sirisaengtaksin
S. Gupta
A Testing Scheme for Crosstalk Faults Based on the Oscillation Test Signal
170(6)
M. Wu
C. Lee
C. Chang
J. Chen
Crosstalk Fault Reduction and Simulation for Clock-Delayed Domino Circuits
176(6)
K. Shimizu
N. Itazaki
K. Kinoshita
A Concurrent Fault Simulation for Crosstalk Faults in Sequential Circuits
182(6)
M. Phadoongsidhi
K. Le
K. Saluja
Session 4B: Built-in Self Test 1
Efficient Circuit Specific Pseudoexhaustive Testing with Cellular Automata
188(6)
S. Chattopadhyay
Fault Set Partition for Efficient Width Compression
194(6)
E. Gizdarski
H. Fujiwara
A Reseeding Technique for LFSR-Based BIST Applications
200(6)
N.-C. Lai
S.-J. Wang
A ROMless LFSR Reseeding Scheme for Scan-Based BIST
206(6)
E. Kalligeros
X. Kavousianos
D. Nikolos
Session 4C: Fault-Tolerance
A Fault-Tolerant Architecture for Symmetric Block Ciphers
212(6)
M.-K. Joo
J.-H. Kim
Y.-H. Choi
A New Learning Approach to Design Fault Tolerant ANNs: Finally a Zero HW-SW Overhead
218(6)
F. Vargas
D. Lettnin
D. Brum
D. Prestes
Experimental Results of a Recovery Block Scheme to Handle Noise in Speech Recognition Systems
224(6)
F. Vargas
R. Fagundes
D. Barros, Jr.
Easily Testable and Fault-Tolerant Design of FFT Butterfly Networks
230(6)
S.-K. Lu
C.-H. Yeh
Session 5A: Fault Detection and Diagnosis
Fault Detection and Fault Diagnosis Techniques for Lookup Table FPGA's
236(6)
S.-K. Lu
C.-Y. Chen
Reduction of Target Fault List for Crosstalk-Induced Delay Faults by Using Layout Constraints
242(6)
K. Keller
H. Takahashi
K. Le
K. Saluja
Y. Takamatsu
Diagnosis of Byzantine Open-Segment Faults
248(6)
S.-Y. Huang
Session 5B: Built-in Self Test 2
Robust Space Compaction of Test Responses
254(6)
A. Dmitriev
M. Gossel
K. Chakrabarty
An Evolutionary Strategy to Design an On-Chip Test Pattern Generator without Prohibited Pattern Set (PPS)
260(6)
N. Ganguly
A. Nandi
S. Das
B. Sikdar
P. Chaudhuri
An Embedded Built-in-Self-Test Approach for Analog-to-Digital Converters
266(6)
S.-H. Hsieh
M.-J. Hsiao
T.-Y. Chang
Session 5C: Software Testing
Statistical Analysis of Time Series Data on the Number of Faults Detected by Software Testing
272(6)
S. Amasaki
T. Yoshitomi
O. Mizuno
T. Kikuno
Y. Takagi
An Analytic Software Testability Model
278(6)
J.-C. Lin
S.-W. Lin
Effective Automated Testing: A Solution of Graphical Object Verification
284(8)
J. Takahashi
Y. Kakuda
Session 6: Special Session -- Test Strategies and Case Studies for SoC in Industries
At-Speed Built-in Test for Logic Circuits with Multiple Clocks
292(6)
K. Hatayama
M. Nakao
Y. Sato
A Test Point Insertion Method to Reduce the Number of Test Patterns
298(7)
M. Yoshimura
T. Hosokawa
M. Ohta
A SoC Test Strategy Based on a Non-scan DFT Method
305(6)
H. Date
T. Hosokawa
M. Muraoka
Embedded Test Solution as a Breakthrough in Reducing Cost of Test for System on Chips
311(6)
K. Iijima
A. Akar
C. McDonald
D. Burek
Manufacturing Test of SoCs
317(3)
R. Kapur
T. Williams
Recent Advances in Test Planning for Modular Testing of Core-Based SoCs
320(6)
V. Iyengar
K. Chakrabarty
E. Jan Marinissen
Session 7A: Test Power Reduction
A Method to Reduce Power Dissipation during Test for Sequential Circuits
326(6)
Y. Higami
S.-Y. Kobayashi
Y. Takamatsu
Test Power Optimization Techniques for CMOS Circuits
332(6)
Z. Luo
X. Li
H. Li
S. Yang
Y. Min
Reducing Test Application Time and Power Dissipation for Scan-Based Testing via Multiple Clock Disabling
338(6)
K.-J. Lee
J.-J. Chen
Session 7B: System-on-Chip Testing 1
A Simple Wrapped Core Linking Module for SoC Test Access
344(6)
J. Song
S. Park
Testing System-on-Chip by Summations of Cores' Test Output Voltages
350(6)
K. Ko
M. Wong
Y. Lee
Test Scheduling of BISTed Memory Cores for SoC
356(6)
C.-W. Wang
J.-R. Huang
Y.-F. Lin
K.-L. Cheng
C.-T. Huang
C.-W. Wu
Session 7C: Verification and Simulation
Effective Error Diagnosis for RTL Designs in HDLs
362(6)
T.-Y. Jiang
C.-N. Liu
J.-Y. Jou
Evolutionary Test Program Induction for Microprocessor Design Verification
368(6)
F. Corno
G. Cumani
M. Reorda
G. Squillero
Hierarchical Fault Simulation Using Behavioral and Gate Level Hardware Models
374(6)
S. Mirkhani
M. Lavasani
Z. Navabi
Session 8A: Test Systems
Testing Embedded Systems by Using a C++ Script Interpreter
380(6)
H. Zainzinger
Extending EDA Environment from Design to Test
386(6)
R. Rajsuman
Vector Memory Expansion System for T33xx Logic Tester
392(5)
K. Yamada
Y. Takahashi
Session 8B: System-on-Chip Testing 2
Integrated Test Scheduling, Test Parallelization and TAM Design
397(8)
E. Larsson
K. Arvidsson
H. Fujiwara
Z. Peng
Core - Clustering Based SoC Test Scheduling Optimization
405(6)
Y. Huang
S. Reddy
W.-T. Cheng
Test Scheduling and Test Access Architecture Optimization for System-on-Chip
411(6)
H.-S. Hsu
J.-R. Huang
K.-L. Cheng
C.-W. Wang
C.-T. Huang
C.-W. Wu
Y.-L. Lin
Session 8C: Current Testing
CMOS Floating Gate Defect Detection Using IDDQ Test with DC Power Supply Superposed by AC Component
417(6)
H. Michinishi
T. Yokohira
T. Okamoto
T. Kobayashi
T. Hondo
Test Time Reduction for IDDQ Testing by Arranging Test Vectors
423(6)
H. Yotsuyanagi
M. Hashizume
T. Tamesada
Time Slot Specification Based Approach to Analog Fault Diagnosis Using Built-in Current Sensors and Test Point Insertion
429(6)
S. Upadhyaya
J. Lee
P. Nair
Author Index 435(2)
Call for Papers of ATS'03 437