Muutke küpsiste eelistusi

Asynchronous On-Chip Networks and Fault-Tolerant Techniques [Kõva köide]

,
  • Formaat: Hardback, 362 pages, kõrgus x laius: 229x152 mm, kaal: 680 g, 20 Tables, black and white; 180 Line drawings, black and white; 180 Illustrations, black and white
  • Ilmumisaeg: 11-May-2022
  • Kirjastus: CRC Press
  • ISBN-10: 1032255757
  • ISBN-13: 9781032255750
Teised raamatud teemal:
Asynchronous On-Chip Networks and Fault-Tolerant TechniquesSuurem pilt
  • Formaat: Hardback, 362 pages, kõrgus x laius: 229x152 mm, kaal: 680 g, 20 Tables, black and white; 180 Line drawings, black and white; 180 Illustrations, black and white
  • Ilmumisaeg: 11-May-2022
  • Kirjastus: CRC Press
  • ISBN-10: 1032255757
  • ISBN-13: 9781032255750
Teised raamatud teemal:
Püsilink: https://www.kriso.ee/db/9781032255750.html
Märksõnad:

This book is the first comprehensive study of fault-tolerance and fault-caused deadlock effects in asynchronous on-chip networks, aiming to overcome these drawbacks and ensure greater reliability of applications.
As a promising alternative to the widely used synchronous on-chip networks for multicore processors, asynchronous on-chip networks can be vulnerable to faults even if they can deliver the same performance with much lower energy and area compared with their synchronous counterparts - faults can not only corrupt data transmission but also cause a unique type of deadlock. By adopting a new redundant code along with a dynamic fault detection and recovery scheme, the authors demonstrate that asynchronous on-chip networks can be efficiently hardened to tolerate both transient and permanent faults and overcome fault-caused deadlocks.
This book will serve as an essential guide for researchers and students studying interconnection networks, fault tolerant computing, asynchronous system design, circuit design and on-chip networking, as well as for professionals interested in designing fault-tolerant and high-throughput asynchronous circuits.



This book is the first comprehensive study of fault-tolerance and fault-caused deadlock effects in asynchronous on-chip networks, aiming to overcome these drawbacks and ensure greater reliability of applications.

Preface xv
Chapter 1 Introduction 1(12)
1.1 Asynchronous Circuits
2(1)
1.2 Asynchronous On-Chip Networks
3(3)
1.3 Fault-Tolerant Asynchronous On-Chip Networks
6(7)
1.3.1 Protection For QDI Links
10(1)
1.3.2 Deadlock Detection
10(1)
1.3.3 Network Recovery
11(2)
Chapter 2 Asynchronous Circuits 13(44)
2.1 Circuit Classification
13(4)
2.1.1 Delay-Insensitive
14(1)
2.1.2 Quasi-Delay-Insensitive
14(1)
2.1.3 Speed-Independent
15(1)
2.1.4 Relaxed QDI
16(1)
2.1.5 Self-Timed
16(1)
2.2 Handshake Protocols
17(2)
2.2.1 Return-To-Zero
17(1)
2.2.2 Non-Return-To-Zero
18(1)
2.3 Data Encoding
19(5)
2.3.1 Non-Delay-Insensitive Codes
19(1)
2.3.2 Delay-Insensitive Codes
20(3)
2.3.2.1 1-Of-N Encoding
20(1)
2.3.2.2 M-Of-N Encoding
21(2)
2.3.2.3 Other DI Encoding
23(1)
2.3.3 Code Evaluation
23(1)
2.4 Asynchronous Pipelines
24(7)
2.4.1 Bundled-Data Pipeline
25(1)
2.4.2 Multi-Rail Pipeline
26(3)
2.4.3 Performance Comparison
29(2)
2.4.3.1 Pipeline Delay
29(1)
2.4.3.2 Pipeline Throughput
29(1)
2.4.3.3 Area And Power Consumption
30(1)
2.5 Implementation Of Asynchronous Circuits
31(26)
2.5.1 Functional Analysis
31(3)
2.5.2 Common Circuit Components
34(13)
2.5.2.1 Basic Components
34(5)
2.5.2.2 Arbiters
39(5)
2.5.2.3 Allocators
44(3)
2.5.3 Metastability And Synchronization
47(2)
2.5.4 Optimization With Traditional EDA Tools
49(9)
2.5.4.1 Loop Elimination
50(3)
2.5.4.2 Speed Optimization
53(4)
Chapter 3 Asynchronous Networks-On-Chip 57(32)
3.1 Concepts Of Networks-On-Chip
58(20)
3.1.1 Network Layer Model
59(1)
3.1.2 Network Topology
60(3)
3.1.3 Switching Techniques
63(9)
3.1.3.1 Circuit Switching And Packet Switching
64(3)
3.1.3.2 Virtual Channel
67(3)
3.1.3.3 Other Flow Control Methods
70(1)
3.1.3.4 Quality Of Service
71(1)
3.1.4 Routing Algorithms
72(6)
3.1.4.1 Deterministic And Non-Deterministic
73(2)
3.1.4.2 Deadlock And Livelock
75(3)
3.2 Asynchronous Networks-On-Chip
78(11)
3.2.1 Taxonomy Of Asynchronous On-Chip Networks
78(4)
3.2.2 Previous Asynchronous NoCs
82(7)
3.2.2.1 SpiNNaker
82(1)
3.2.2.2 ASPIN
83(2)
3.2.2.3 QoS NoC
85(1)
3.2.2.4 ANOC
85(1)
3.2.2.5 MANGO
86(1)
3.2.2.6 QNoC
87(2)
Chapter 4 Optimizing Asynchronous On-Chip Networks 89(78)
4.1 Channel Slicing
89(15)
4.1.1 Synchronization Overhead
90(2)
4.1.2 Channel Slicing
92(3)
4.1.3 Lookahead Pipeline
95(2)
4.1.4 Channel Sliced Wormhole Router
97(7)
4.1.4.1 Router Structure
98(4)
4.1.4.2 Performance Evaluation
102(2)
4.2 Spatial Division Multiplexing
104(25)
4.2.1 Problems Of The Virtual Channel Flow Control
105(2)
4.2.1.1 Slow Switch Allocation
105(1)
4.2.1.2 Large Area Overhead
106(1)
4.2.1.3 Long Pipeline Synchronization Latency
107(1)
4.2.2 Spatial Division Multiplexing
107(3)
4.2.3 SDM Router
110(4)
4.2.3.1 Router Structure
110(3)
4.2.3.2 Performance Evaluation
113(1)
4.2.4 Comparison Between SDM And VC
114(15)
4.2.4.1 Area Model
114(3)
4.2.4.2 Latency Model
117(4)
4.2.4.3 Model For VC Routers
121(1)
4.2.4.4 Performance Analysis
122(7)
4.3 Area Reduction Using Clos Networks
129(38)
4.3.1 Clos Switching Networks
130(4)
4.3.2 Dispatching Algorithm
134(10)
4.3.2.1 Concurrent Round-Robin Dispatching
134(2)
4.3.2.2 Asynchronous Dispatching
136(4)
4.3.2.3 Performance Of CRRD And AD
140(4)
4.3.3 Asynchronous Clos Scheduler
144(11)
4.3.3.1 Implementation
144(8)
4.3.3.2 Performance
152(3)
4.3.4 Sdm Router Using 2-Stage Clos Switch
155(13)
4.3.4.1 Asynchronous 2-Stage Clos Switch
155(2)
4.3.4.2 Router Implementation
157(6)
4.3.4.3 Performance Evaluation
163(4)
Chapter 5 Fault-Tolerant Asynchronous Circuits 167(58)
5.1 Fault Classification
168(5)
5.1.1 Transient Faults
169(2)
5.1.2 Permanent Faults
171(2)
5.1.3 Intermittent Faults
173(1)
5.2 Fault-Tolerant Techniques
173(3)
5.2.1 Masking Factors
173(1)
5.2.2 Redundancy Techniques
174(2)
5.3 Impact Of Transient Faults On QDI Pipelines
176(8)
5.3.1 Faults On Synchronous And QDI Pipelines
177(2)
5.3.2 Impact Modeling Of Transient Faults
179(5)
5.3.2.1 Faults On Data With Positive Ack
180(2)
5.3.2.2 Faults On Data With Negative Ack
182(1)
5.3.2.3 Faults On Completion Detector And Ack
183(1)
5.3.2.4 Physical-Layer Deadlock
183(1)
5.4 Deadlock Modeling
184(20)
5.4.1 Deadlock Caused By Permanent Faults
186(4)
5.4.2 Deadlock Caused By Transient Faults
190(10)
5.4.3 Deadlock Analysis
200(4)
5.5 Related Work
204(18)
5.5.1 Tolerating Transient Faults
204(9)
5.5.1.1 Information Redundancy
205(4)
5.5.1.2 Physical And Other Redundancy
209(4)
5.5.2 Management For Permanent Faults And Deadlocks
213(13)
5.5.2.1 Conventional Techniques
213(4)
5.5.2.2 Fault-Caused Physical-Layer Deadlocks
217(5)
5.6 General Deadlock Management Strategy
222(3)
Chapter 6 Fault-Tolerant Coding 225(46)
6.1 Comparison With Related Work
226(4)
6.1.1 Non-QDI Designs
227(1)
6.1.2 QDI Designs
228(1)
6.1.3 Unordered And Systematic Codes
228(2)
6.2 DIRC Coding Scheme
230(8)
6.2.1 Arithmetic Rules
231(1)
6.2.1.1 Rules For 1-Of-N Codes
231(1)
6.2.1.2 Rules For M-Of-N Codes
231(1)
6.2.2 Delay-Insensitive Redundant Check Codes
232(1)
6.2.3 Check Generation And Error Correction
233(1)
6.2.4 Error Filtering
234(3)
6.2.5 Code Evaluation
237(1)
6.3 Implementation Of DIRC Pipelines
238(10)
6.3.1 1-Of-N Adders And Error Filters
238(2)
6.3.2 Generation Of Check Words
240(1)
6.3.3 Redundant Protection Of Acknowledge Wires
241(1)
6.3.4 Variants Of DIRC Pipelines
242(6)
6.3.4.1 Latency And Area
245(1)
6.3.4.2 Different Construction Patterns
245(2)
6.3.4.3 DIRC In Asynchronous NoCs
247(1)
6.4 Latency And Area Models
248(11)
6.4.1 Latency Analysis
249(2)
6.4.2 Area Model For One Stage
251(4)
6.4.3 Models For Different Constructions
255(4)
6.5 Experimental Results
259(10)
6.5.1 Performance Evaluation
260(5)
6.5.2 Fault-Tolerance Evaluation
265(2)
6.5.3 Comparison With Related Work
267(2)
6.6 Summary
269(2)
Chapter 7 Deadlock Detection 271(32)
7.1 Baseline QDI NoC
271(2)
7.1.1 Network Principles
271(1)
7.1.2 Asynchronous Protocols
272(1)
7.2 Fault Impact On Data Path
273(4)
7.2.1 Fault Classifications
273(1)
7.2.2 General Fault Impact
274(3)
7.3 Detecting Permanent Fault On Data Path
277(17)
7.3.1 Data Path Partition
278(1)
7.3.2 Deadlock Caused By Permanent Link Fault
279(4)
7.3.3 Deadlock Patterns Due To Permanent Link Fault
283(3)
7.3.4 Time-Out Detection Mechanism
286(6)
7.3.5 Detection Of Permanent Router Fault
292(2)
7.4 Handling Deadlocks Caused By Different Faults
294(6)
7.4.1 Fault Diagnosis
295(3)
7.4.2 Modified Time-Out Mechanism
298(2)
7.5 Summary
300(3)
Chapter 8 Deadlock Recovery 303(20)
8.1 Deadlock Removal By Drain And Release
304(7)
8.1.1 The Drain Operation
305(1)
8.1.2 Buffer Controller At Router Input
306(2)
8.1.3 The Release Operation
308(3)
8.2 Faulty Link Isolation By Using SDM
311(3)
8.2.1 Spatial Division Multiplexing
311(1)
8.2.2 Switch Allocator Reconfiguration
312(2)
8.3 Recovery From Intermittent And Transient Faults
314(2)
8.4 Technical Issues
316(4)
8.5 Summary
320(3)
Chapter 9 Summary 323(6)
9.1 Overall Remarks
324(3)
9.2 Future Work
327(2)
Bibliography 329
Wei Song is Associate Professor in the State Key Laboratory of Information Security, Institute of Information Engineering, at the Chinese Academy of Science, China. His current research focuses on the security of computer architectures.

Guangda Zhang is Associate Professor in the Defense Innovation Institute, at the Academy of Military Sciences, China. His current research focuses on asynchronous circuit, microprocessor and computer architecture, and fault tolerance.