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Autonomic Networking-on-Chip: Bio-Inspired Specification, Development, and Verification [Kõva köide]

Edited by (Nguyen Tat Thanh University, Ho Chi Minh City, Vietnam)
  • Formaat: Hardback, 288 pages, kõrgus x laius: 234x156 mm, kaal: 635 g, 21 Tables, black and white; 68 Illustrations, black and white
  • Sari: Embedded Multi-Core Systems
  • Ilmumisaeg: 07-Dec-2011
  • Kirjastus: CRC Press Inc
  • ISBN-10: 143982911X
  • ISBN-13: 9781439829110
Teised raamatud teemal:
Autonomic Networking-on-Chip: Bio-Inspired Specification, Development, and VerificationSuurem pilt
  • Formaat: Hardback, 288 pages, kõrgus x laius: 234x156 mm, kaal: 635 g, 21 Tables, black and white; 68 Illustrations, black and white
  • Sari: Embedded Multi-Core Systems
  • Ilmumisaeg: 07-Dec-2011
  • Kirjastus: CRC Press Inc
  • ISBN-10: 143982911X
  • ISBN-13: 9781439829110
Teised raamatud teemal:
Püsilink: https://www.kriso.ee/db/9781439829110.html
Märksõnad:
For readers who already have a basic understanding of network-on-chip (NoC) paradigm, computer scientists explain an approach that is inspired by the human autonomic nervous network. Balancing theory with applications, they discuss a bio-inspired architecture for autonomous NoC, bio-inspired architecture optimization, an architecture using a heuristic technique for virtual-channel sharing, the evolutionary design of collective communications on wormhole NoCs, formal aspects of parallel processing on bio-inspired NoCs, a monitoring-centric design approach for adaptive parallel computing, toward self-placing applications on NoCs of two and three dimensions, and self-adaptation in system-on-chips. Annotation ©2012 Book News, Inc., Portland, OR (booknews.com) Despite the growing mainstream importance and unique advantages of autonomic networking-on-chip (ANoC) technology, Autonomic Networking-On-Chip: Bio-Inspired Specification, Development, and Verification is among the first books to evaluate research results on formalizing this emerging NoC paradigm, which was inspired by the human nervous system.The FIRST Book to Assess Research Results, Opportunities, & Trends in BioChipNetsThe third book in the Embedded Multi-Core Systems series from CRC Press, this is an advanced technical guide and reference composed of contributions from prominent researchers in industry and academia around the world. A response to the critical need for a global information exchange and dialogue, it is written for engineers, scientists, practitioners, and other researchers who have a basic understanding of NoC and are now ready to learn how to specify, develop, and verify ANoC using rigorous approaches.Offers Expert Insights Into Technical Topics Including:Bio-inspired NoCHow to map applications onto ANoCANoC for FPGAs and structured ASICsMethods to apply formal methods in ANoC developmentWays to formalize languages that enable ANoCMethods to validate and verify techniques for ANoC Use of self- processes in ANoC (self-organization, configuration, healing, optimization, protection, etc.)Use of calculi for reasoning about context awareness and programming models in ANoCWith illustrative figures to simplify contents and enhance understanding, this resource contains original, peer-reviewed chapters reporting on new developments and opportunities, emerging trends, and open research problems of interest to both the autonomic computing and network-on-chip communities. Coverage includes state-of-the-art ANoC architectures, protocols, technologies, and applications. This volume thoroughly explores the theory behind ANoC to illustrate strategies that enable readers to use formal ANoC methods yet still make sound judgments and allow for reasonable justifications in practice.
List of Figures
xi
List of Tables
xv
Foreword xvii
Preface xix
About the Editor xxiii
List of Contributors
xxv
1 A Bio-Inspired Architecture for Autonomic Network-on-Chip
1(20)
M. Bakhouya
1.1 Introduction
2(1)
1.2 Infrastructure level
3(4)
1.2.1 Topology customization
4(1)
1.2.2 Bandwidth allocation
5(1)
1.2.3 Buffer allocation
6(1)
1.3 Communication level
7(4)
1.3.1 Switching modes
7(1)
1.3.2 Routing schemes
8(1)
1.3.3 Flow control schemes
9(2)
1.4 Application level
11(1)
1.5 BNoC Architecture
12(7)
1.5.1 Immune system principles
13(1)
1.5.2 BNoC principles
14(2)
1.5.3 Simulation results
16(3)
1.6 Conclusions
19(2)
2 Bio-Inspired NoC Architecture Optimization
21(26)
A.A. Morgan
H. Elmiligi
M.W. El-Kharashi
F. Gebali
2.1 Introduction
22(1)
2.2 Related work
23(2)
2.2.1 Employment of known standard architectures
24(1)
2.2.2 Generation of semi-custom architectures
24(1)
2.2.3 Generation of fully-custom architectures
25(1)
2.3 Bio-inspired optimization techniques
25(1)
2.4 Graph theory representation of NoC applications
26(1)
2.5 Problem formulation
26(7)
2.5.1 Power model
28(2)
2.5.2 Area model
30(1)
2.5.3 Delay model
31(1)
2.5.4 Reliability model
32(1)
2.5.5 Optimization objective function formulation
32(1)
2.6 Custom architecture generation using GA
33(5)
2.6.1 Legality criteria for generated architectures
34(2)
2.6.2 Methodology for custom architecture generation
36(2)
2.7 Experimental results
38(7)
2.8 Conclusions
45(2)
3 An Autonomic NoC Architecture Using Heuristic Technique for Virtual-Channel Sharing
47(22)
K. Latif
A.M. Rahmani
T. Seceleanu
H. Tenhunen
3.1 Introduction
48(3)
3.2 Background
51(1)
3.3 Resource utilization analysis
52(2)
3.3.1 Link load analysis
52(1)
3.3.2 Real application-based analysis
53(1)
3.4 The proposed router architecture: PVS-NoC
54(10)
3.4.1 Packet format
56(2)
3.4.2 The input controller and buffer allocation
58(2)
3.4.3 The output controller and routing algorithm
60(1)
3.4.4 Comparison with existing architectures
61(2)
3.4.5 Virtual-channel sharing under faults
63(1)
3.5 Experimental results
64(2)
3.5.1 Synthetic traffic
65(1)
3.5.2 Real application traffic
65(1)
3.6 Conclusions
66(2)
3.7 Glossary
68(1)
4 Evolutionary Design of Collective Communications on Wormhole NoCs
69(36)
J. Jaros
V. Dvorak
4.1 Introduction
70(1)
4.2 Collective communications
71(6)
4.2.1 A model of communication
72(2)
4.2.2 Classification of collective communications
74(1)
4.2.3 The lower bounds on time complexity
75(2)
4.3 State-of-the-art
77(1)
4.4 Evolutionary design of collective communications
78(7)
4.4.1 Input data structure and preprocessing
80(1)
4.4.2 Scatter encoding
80(1)
4.4.3 Broadcast encoding
81(2)
4.4.4 Fitness function definition
83(1)
4.4.5 Acceleration and restoration heuristics
84(1)
4.4.6 The mutation operator
84(1)
4.5 Optimization tools and parameters adjustments
85(4)
4.5.1 Experimental comparison of optimization quality
86(1)
4.5.2 Experimental comparison of optimization speed
86(1)
4.5.3 Experimental comparison of optimization scalability
87(2)
4.5.4 Tools assessment
89(1)
4.6 Experimental results of the quest for high-quality schedules
89(9)
4.6.1 Experimental results on common topologies
89(2)
4.6.2 Experimental results on novel and fat nodes topologies
91(3)
4.6.3 Experimental results on fault-tolerant topologies and many-to-many patterns
94(4)
4.7 Conclusions
98(7)
4.7.1 Contributions of the proposed technique
101(1)
4.7.2 Future work
102(3)
5 Formal Aspects of Parallel Processing on Bio-Inspired on-Chip Networks
105(30)
P.C. Vinh
5.1 Introduction
106(2)
5.2 Outline
108(1)
5.3 Related work
108(1)
5.4 Basic concepts
109(5)
5.4.1 Category definition
109(1)
5.4.1.1 Category as a graph
109(1)
5.4.1.2 Identity morphism and composition of morphisms
110(2)
5.4.1.3 Identity and associativity for composition of morphisms
112(1)
5.4.2 Functor
112(1)
5.4.3 Isomorphism
112(1)
5.4.4 Natural isomorphism
113(1)
5.4.5 Element of a set
113(1)
5.5 Processing BioChipNet tasks
114(10)
5.5.1 Parallel composition of BioChipNet tasks
114(1)
5.5.2 BioChipNet Tasks
115(1)
5.5.3 Categorical characteristics of BioChipNet tasks
116(2)
5.5.4 Core-to-core networks
118(1)
5.5.4.1 Self-configuration of core-to-core networks
118(2)
5.5.4.2 Category of core-to-core networks
120(1)
5.5.4.3 Extensional monoidal category of core-to-core networks
121(1)
5.5.4.4 Pushout of self-configuring core-to-core networks
122(2)
5.6 Processing BioChipNet data
124(8)
5.6.1 BioChipNet agents
124(2)
5.6.2 Category of BioChipNet data types
126(1)
5.6.3 Extensional monoidal category of BioChipNet data types
127(2)
5.6.4 Parallel composition of BioChipNet agents
129(3)
5.7 Notes and remarks
132(2)
5.8 Conclusions
134(1)
6 HAMSoC: A Monitoring-Centric Design Approach for Adaptive Parallel Computing
135(30)
L. Guang
J. Plosila
J. Isoaho
H. Tenhunen
6.1 Introduction
136(1)
6.2 Hierarchical agent monitoring design approach
137(7)
6.2.1 Monitoring-centric design methodology
137(2)
6.2.2 Hierarchical agent monitoring
139(2)
6.2.3 Hierarchical agent monitored system-on-chip
141(3)
6.3 Formal specification of HAMSoC
144(12)
6.3.1 Specification framework of HAMSoC
144(3)
6.3.2 Specification of agents and resources
147(1)
6.3.2.1 Formal specification of resources
147(2)
6.3.2.2 Formal specification of agents
149(1)
6.3.3 Specification of monitoring operations
150(1)
6.3.3.1 Specification format
150(1)
6.3.3.2 Types of monitoring operation
151(1)
6.3.4 State transition of agents and resources
152(1)
6.3.4.1 State transition of resources
153(2)
6.3.4.2 State transition of agents
155(1)
6.4 Design example: hierarchical power monitoring in HAMNoC
156(7)
6.4.1 System description
157(2)
6.4.2 Specification of resources
159(1)
6.4.3 Specification of agents and monitoring operations
159(2)
6.4.4 Formal modeling of state transitions
161(2)
6.5 Conclusions
163(1)
6.6 Glossary
164(1)
7 Toward Self-Placing Applications on 2D and 3D NoCs
165(24)
L. Petre
K. Sere
L. Tsiopoulos
P. Liljeberg
J. Plosila
7.1 Introduction
165(3)
7.2 Related work
168(4)
7.3 NoC-oriented MIDAS
172(7)
7.3.1 Conservative extension
174(2)
7.3.2 Enabledness
176(2)
7.3.3 Location-updating code
178(1)
7.3.4 Updating replicated memory units
179(1)
7.4 Placing and replacing resources
179(8)
7.4.1 The placing algorithm
179(4)
7.4.2 Replacing
183(4)
7.5 Conclusions
187(2)
8 Self-Adaption in SoCs
189(26)
H. Zakaria
E. Yahya
L. Fesquet
8.1 Introduction
190(3)
8.1.1 Power consumption
190(1)
8.1.2 Process variability
191(1)
8.1.3 Yield
192(1)
8.2 Power management techniques
193(10)
8.2.1 Leakage power management
194(1)
8.2.2 Dynamic power management
194(3)
8.2.2.1 DVFS architecture overview
197(3)
8.2.2.2 DC/DC converter
200(1)
8.2.2.3 Clock generator
201(1)
8.2.2.4 Sensing the computational activity
202(1)
8.3 Controlling uncertainty and handling process variability
203(4)
8.4 Data synchronization in GALS system
207(5)
8.4.1 GALS wrapper with pausible clocking
208(1)
8.4.2 FIFO solutions
209(1)
8.4.3 Boundary synchronization
210(2)
8.5 Conclusions
212(1)
8.6 Glossary
213(2)
Bibliography 215(28)
Index 243
Phan Cong-Vinh received a Ph.D in computer science from London South Bank University (LSBU) in the United Kingdom, a BS in mathematics and an MS in computer science from Vietnam National University (VNU) in Ho Chi Minh City, and a BA in English from Hanoi University of Foreign Languages Studies in Vietnam. He finished his PhD dissertation with the title Formal Aspects of Dynamic Reconfigurability in Reconfigurable Computing Systems supervised by Prof. Jonathan P. Bowen at LSBU where he was affiliated with the Centre for Applied Formal Methods (CAFM) at the Institute for Computing Research (ICR). From 1983 to 2000, he was a lecturer in mathematics and computer science at VNU, Posts and Telecommunications Institute of Technology (PTIT) and several other universities in Vietnam before he joined research with Dr. Tomasz Janowski at the International Institute for Software Technology (IIST) in Macao SAR, China, as a fellow in 2000. His research interests center on all aspects of formal methods, autonomic computing and networking, reconfigurable computing, ubiquitous computing, and applied categorical structures in computer science.