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Boundary-scan Handbook: Analog and Digital 2nd Revised edition [Kõva köide]

  • Formaat: Hardback, 320 pages, kõrgus: 230 mm, figures, tables, references, index
  • Ilmumisaeg: 30-Sep-1998
  • Kirjastus: Kluwer Academic Publishers
  • ISBN-10: 0792382773
  • ISBN-13: 9780792382775
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  • Formaat: Hardback, 320 pages, kõrgus: 230 mm, figures, tables, references, index
  • Ilmumisaeg: 30-Sep-1998
  • Kirjastus: Kluwer Academic Publishers
  • ISBN-10: 0792382773
  • ISBN-13: 9780792382775
Teised raamatud teemal:
Boundary-Scan, formally known as IEEE/ANSI Standard 1149.1-1990, is a collection of design rules applied principally at the Integrated Circuit (IC) level that allow software to alleviate the growing cost of designing, producing and testing digital systems. A fundamental benefit of the standard is its ability to transform extremely difficult printed circuit board testing problems that could only be attacked with ad-hoc testing methods into well-structured problems that software can easily deal with.
IEEE standards, when embraced by practicing engineers, are living entities that grow and change quickly.The Boundary-Scan Handbook, Second Edition: Analog and Digital is intended to describe these standards in simple English rather than the strict and pedantic legalese encountered in the standards.
The 1149.1 standard is now over eight years old and has a large infrastructure of support in the electronics industry. Today, the majority of custom ICs and programmable devices contain 1149.1. New applications for the 1149.1 protocol have been introduced, most notably the `In-System Configuration' (ISC) capability for Field Programmable Gate Arrays (FPGAs).
The Boundary-Scan Handbook, Second Edition: Analog and Digital updates the information about IEEE Std. 1149.1, including the 1993 supplement that added new silicon functionality and the 1994 supplement that formalized the BSDL language definition. In addition, the new second edition presents completely new information about the newly approved 1149.4 standard often termed `Analog Boundary-Scan'. Along with this is a discussion of Analog Metrology needed to make use of 1149.1. This forms a toolset essential for testing boards and systems of the future.
List of Figures
xiii(5)
List of Tables
xviii(2)
List of Design-for-Test Rules xix(2)
Preface to the First Edition xxi(2)
Preface to the Second Edition xxiii(2)
Acknowledgement xxv
1 Boundary-Scan Basics and Vocabulary
1(48)
1.1 Digital Test Before Boundary-Scan
2(5)
1.1.1 Edge-Connector Functional Testing
2(2)
1.1.2 In-Circuit Testing
4(3)
1.2 The Philosophy of 1149.1-1990
7(1)
1.3 Basic Architecture
8(24)
1.3.1 The TAP Controller
10(6)
1.3.2 The Instruction Register
16(4)
1.3.3 Data Registers
20(1)
1.3.4 The Boundary Register
21(6)
1.3.5 Optimizing a Boundary Register Cell Design
27(2)
1.3.6 Architecture Summary
29(1)
1.3.7 Field-Programmable IC Devices
30(1)
1.3.8 Boundary-Scan Chains
31(1)
1.4 Non-Invasive Operational Modes
32(4)
1.4.1 BYPASS
33(1)
1.4.2 IDCODE
33(1)
1.4.3 USERCODE
34(1)
1.4.4 SAMPLE
35(1)
1.4.5 PRELOAD
35(1)
1.5 Pin-Permission Operational Modes
36(4)
1.5.1 EXTEST
36(1)
1.5.2 INTEST
37(1)
1.5.3 RUNBIST
38(1)
1.5.4 HIGHZ
39(1)
1.5.5 CLAMP
39(1)
1.5.6 Exceptions Due to Clocking
39(1)
1.6 Extensibility
40(1)
1.7 Subordination of IEEE 1149.1
41(1)
1.8 Costs and Benefits
42(4)
1.8.1 Costs
42(1)
1.8.2 Benefits
43(2)
1.8.3 Trends
45(1)
1.9 Other Testability Standards
46(3)
2 Boundary-Scan Description Language (BSDL)
49(56)
2.1 The Scope of BSDL
52(5)
2.1.1 Testing
52(1)
2.1.2 Compliance Assurance
53(2)
2.1.3 Synthesis
55(2)
2.2 Structure of BSDL
57(4)
2.3 Entity Descriptions
61(17)
2.3.1 Generic Parameter
62(1)
2.3.2 Logical Port Description
62(1)
2.3.3 Standard USE Statement
63(1)
2.3.4 Use Statements
64(1)
2.3.5 Component Conformance Statement
64(1)
2.3.6 Device Package Pin Mappings
65(1)
2.3.7 Grouped Port Identification
66(1)
2.3.8 TAP Port Identification
67(1)
2.3.9 Compliance Enable Description
68(1)
2.3.10 Instruction Register Description
69(1)
2.3.11 Optional Register Description
70(1)
2.3.12 Register Access Description
71(1)
2.3.13 Boundary-Scan Register Description
72(3)
2.3.14 RUNBIST Execution Description
75(1)
2.3.15 INTEST Execution Description
76(1)
2.3.16 User Extensions to BSDL
77(1)
2.3.17 Design Warnings
77(1)
2.4 Some advanced BSDL Topics
78(2)
2.4.1 Merged Cells
78(2)
2.4.2 Asymmetrical Drivers
80(1)
2.5 BSDL Description of 74BCT8374
80(4)
2.6 Packages and Package Bodies
84(17)
2.6.1 STD 1149 1 1999
85(4)
2.6.2 Cell Description Constants
89(2)
2.6.3 Basic Cell Definitions BC 0 to BC 7
91(8)
2.6.4 User-Defined Boundary Cells
99(1)
2.6.5 Definition of BSDL Extensions
100(1)
2.7 Writing BSDL
101(2)
2.8 Summary
103(2)
3 Boundary-Scan Testing
105(40)
3.1 Basic Boundary-Scan Testing
106(13)
3.1.1 The 1149.1 Scanning Sequence
106(6)
3.1.2 Basic Test Algorithm
112(1)
3.1.3 The "Personal Tester" Versus ATE
113(1)
3.1.4 In-Circuit Boundary-Scan
114(2)
3.1.5 IC Test
116(2)
3.1.6 IC BIST
118(1)
3.2 Testing with Boundary-Scan Chains
119(23)
3.2.1 1149.1 Chain Integrity
119(3)
3.2.2 Interconnect Tests
122(14)
3.2.3 Connection Tests
136(2)
3.2.4 Interaction Tests
138(3)
3.2.5 BIST and Custom Tests
141(1)
3.3 Porting Boundary-Scan Tests
142(2)
3.4 Summary
144(1)
4 Advanced Boundary-Scan Topics
145(22)
4.1 DC Parametric IC Tests
146(1)
4.2 Sample Mode Tests
147(3)
4.3 Concurrent Monitoring
150(1)
4.4 Non-Scan IC Testing
151(3)
4.5 Non-Digital Device Testing
154(1)
4.6 Mixed Digital/Analog Testing
155(2)
4.7 Multi-Chip Module Testing
157(2)
4.8 Firmware Development Support
159(1)
4.9 In-System Configuration
160(3)
4.10 Hardware Fault Insertion
163(4)
5 Design for Boundary-Scan Test
167(30)
5.1 Integrated Circuit Level DFT
169(13)
5.1.1 TAP Pin Placement
169(1)
5.1.2 Power and Ground Distribution
170(4)
5.1.3 Instruction Capture Pattern
174(1)
5.1.4 Damage Resistant Drivers
175(1)
5.1.5 Output Pins
176(1)
5.1.6 Bidirectional Pins
177(1)
5.1.7 Post-Lobotomy Behavior
178(1)
5.1.8 IDCODEs
178(1)
5.1.9 User-Defined Instructions
179(1)
5.1.10 Creation and Verification of BSDL
180(2)
5.2 Board-Level DFT
182(11)
5.2.1 Chain Configurations
182(3)
5.2.2 TCK/TMS Distribution
185(1)
5.2.3 Mixed Logic Families
186(1)
5.2.4 Board Level Conflicts
187(1)
5.2.5 Control of Critical Nodes
188(2)
5.2.6 Power Distribution
190(1)
5.2.7 Boundary-Scan Masters
190(2)
5.2.8 Post-Lobotomy Board Behavior
192(1)
5.3 System-Level DFT
193(2)
5.3.1 The MultiDrop Problem
194(1)
5.3.2 Coordination with Other Standards
195(1)
5.4 Summary
195(2)
6 Analog Measurement Basics
197(24)
6.1 Analog In-Circuit Testing
197(14)
6.1.1 Analog Failures
198(2)
6.1.2 Measuring an Impedance
200(4)
6.1.3 Errors and Corrections
204(2)
6.1.4 Measurement Hardware
206(5)
6.2 Limited Access Testing
211(6)
6.2.1 Node Voltage Analysis
212(1)
6.2.2 Testing With Node Voltages
213(2)
6.2.3 Limited Access Node Voltage Testing
215(2)
6.3 The Mixed-Signal Test Environment
217(3)
6.4 Summary
220(1)
7 IEEE 1149.4 Analog Boundary-Scan
221(42)
7.1 1149.4 Vocabulary and Basics
222(5)
7.1.1 The Target Fault Spectrum
223(1)
7.1.2 Extended Interconnect
223(2)
7.1.3 Digital Pins
225(1)
7.1.4 Analog Pins
226(1)
7.2 General Architecture of an 1149.4 IC
227(16)
7.2.1 Silicon "Switches"
229(1)
7.2.2 The Analog Test Access Port (ATAP)
230(1)
7.2.3 The Test Bus Interface Circuit (TBIC)
231(5)
7.2.4 The Analog Boundary Module (ABM)
236(6)
7.2.5 The Digital Boundary Module (DBM)
242(1)
7.3 The 1149.4 Instruction Set
243(7)
7.3.1 The EXTEST Instruction
244(3)
7.3.2 The CLAMP Instruction
247(1)
7.3.3 The HIGHZ Instruction
247(1)
7.3.4 The PROBE Instruction
247(1)
7.3.5 The RUNBIST Instruction
248(1)
7.3.6 The INTEST Instruction
248(2)
7.4 Other Provisions of 1149.4
250(7)
7.4.1 Differential ATAP Port
250(1)
7.4.2 Differential I/O
251(2)
7.4.3 Partitioned Internal Test Buses
253(3)
7.4.4 Specifications and Limits
256(1)
7.5 Design for 1149.4 Testability
257(4)
7.5.1 Integrated Circuit Level
257(2)
7.5.2 Board Level
259(1)
7.5.3 System Level
260(1)
7.6 Summary
261(1)
7.7 Eilog: What Next for 1149.1/1149.4?
262(1)
APPENDIX A: BSDL Syntax Specifications 263(12)
A.1 Conventions 263(1)
A.2 Lexical elements of BSDL 264(3)
A.3 Notes on syntax definition 267(2)
A.4 BSDL Syntax 269(4)
A.5 User Package Syntax 273(2)
Bibliography 275(6)
Index 281