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xiii | (5) |
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xviii | (2) |
List of Design-for-Test Rules |
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xix | (2) |
Preface to the First Edition |
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xxi | (2) |
Preface to the Second Edition |
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xxiii | (2) |
Acknowledgement |
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xxv | |
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1 Boundary-Scan Basics and Vocabulary |
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1 | (48) |
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1.1 Digital Test Before Boundary-Scan |
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2 | (5) |
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1.1.1 Edge-Connector Functional Testing |
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2 | (2) |
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4 | (3) |
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1.2 The Philosophy of 1149.1-1990 |
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7 | (1) |
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8 | (24) |
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10 | (6) |
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1.3.2 The Instruction Register |
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16 | (4) |
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20 | (1) |
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1.3.4 The Boundary Register |
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21 | (6) |
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1.3.5 Optimizing a Boundary Register Cell Design |
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27 | (2) |
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1.3.6 Architecture Summary |
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29 | (1) |
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1.3.7 Field-Programmable IC Devices |
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30 | (1) |
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1.3.8 Boundary-Scan Chains |
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31 | (1) |
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1.4 Non-Invasive Operational Modes |
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32 | (4) |
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33 | (1) |
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33 | (1) |
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34 | (1) |
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35 | (1) |
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35 | (1) |
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1.5 Pin-Permission Operational Modes |
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36 | (4) |
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36 | (1) |
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37 | (1) |
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38 | (1) |
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39 | (1) |
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39 | (1) |
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1.5.6 Exceptions Due to Clocking |
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39 | (1) |
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40 | (1) |
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1.7 Subordination of IEEE 1149.1 |
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41 | (1) |
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42 | (4) |
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42 | (1) |
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43 | (2) |
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45 | (1) |
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1.9 Other Testability Standards |
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46 | (3) |
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2 Boundary-Scan Description Language (BSDL) |
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49 | (56) |
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52 | (5) |
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52 | (1) |
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2.1.2 Compliance Assurance |
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53 | (2) |
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55 | (2) |
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57 | (4) |
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61 | (17) |
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62 | (1) |
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2.3.2 Logical Port Description |
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62 | (1) |
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2.3.3 Standard USE Statement |
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63 | (1) |
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64 | (1) |
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2.3.5 Component Conformance Statement |
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64 | (1) |
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2.3.6 Device Package Pin Mappings |
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65 | (1) |
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2.3.7 Grouped Port Identification |
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66 | (1) |
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2.3.8 TAP Port Identification |
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67 | (1) |
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2.3.9 Compliance Enable Description |
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68 | (1) |
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2.3.10 Instruction Register Description |
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69 | (1) |
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2.3.11 Optional Register Description |
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70 | (1) |
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2.3.12 Register Access Description |
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71 | (1) |
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2.3.13 Boundary-Scan Register Description |
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72 | (3) |
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2.3.14 RUNBIST Execution Description |
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75 | (1) |
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2.3.15 INTEST Execution Description |
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76 | (1) |
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2.3.16 User Extensions to BSDL |
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77 | (1) |
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77 | (1) |
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2.4 Some advanced BSDL Topics |
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78 | (2) |
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78 | (2) |
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2.4.2 Asymmetrical Drivers |
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80 | (1) |
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2.5 BSDL Description of 74BCT8374 |
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80 | (4) |
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2.6 Packages and Package Bodies |
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84 | (17) |
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85 | (4) |
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2.6.2 Cell Description Constants |
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89 | (2) |
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2.6.3 Basic Cell Definitions BC 0 to BC 7 |
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91 | (8) |
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2.6.4 User-Defined Boundary Cells |
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99 | (1) |
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2.6.5 Definition of BSDL Extensions |
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100 | (1) |
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101 | (2) |
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103 | (2) |
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105 | (40) |
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3.1 Basic Boundary-Scan Testing |
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106 | (13) |
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3.1.1 The 1149.1 Scanning Sequence |
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106 | (6) |
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3.1.2 Basic Test Algorithm |
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112 | (1) |
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3.1.3 The "Personal Tester" Versus ATE |
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113 | (1) |
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3.1.4 In-Circuit Boundary-Scan |
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114 | (2) |
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116 | (2) |
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118 | (1) |
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3.2 Testing with Boundary-Scan Chains |
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119 | (23) |
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3.2.1 1149.1 Chain Integrity |
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119 | (3) |
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122 | (14) |
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136 | (2) |
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138 | (3) |
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3.2.5 BIST and Custom Tests |
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141 | (1) |
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3.3 Porting Boundary-Scan Tests |
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142 | (2) |
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144 | (1) |
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4 Advanced Boundary-Scan Topics |
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145 | (22) |
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4.1 DC Parametric IC Tests |
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146 | (1) |
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147 | (3) |
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4.3 Concurrent Monitoring |
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150 | (1) |
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151 | (3) |
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4.5 Non-Digital Device Testing |
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154 | (1) |
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4.6 Mixed Digital/Analog Testing |
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155 | (2) |
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4.7 Multi-Chip Module Testing |
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157 | (2) |
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4.8 Firmware Development Support |
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159 | (1) |
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4.9 In-System Configuration |
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160 | (3) |
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4.10 Hardware Fault Insertion |
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163 | (4) |
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5 Design for Boundary-Scan Test |
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167 | (30) |
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5.1 Integrated Circuit Level DFT |
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169 | (13) |
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169 | (1) |
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5.1.2 Power and Ground Distribution |
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170 | (4) |
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5.1.3 Instruction Capture Pattern |
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174 | (1) |
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5.1.4 Damage Resistant Drivers |
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175 | (1) |
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176 | (1) |
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177 | (1) |
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5.1.7 Post-Lobotomy Behavior |
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178 | (1) |
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178 | (1) |
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5.1.9 User-Defined Instructions |
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179 | (1) |
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5.1.10 Creation and Verification of BSDL |
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180 | (2) |
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182 | (11) |
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5.2.1 Chain Configurations |
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182 | (3) |
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5.2.2 TCK/TMS Distribution |
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185 | (1) |
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5.2.3 Mixed Logic Families |
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186 | (1) |
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5.2.4 Board Level Conflicts |
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187 | (1) |
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5.2.5 Control of Critical Nodes |
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188 | (2) |
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190 | (1) |
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5.2.7 Boundary-Scan Masters |
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190 | (2) |
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5.2.8 Post-Lobotomy Board Behavior |
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192 | (1) |
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193 | (2) |
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5.3.1 The MultiDrop Problem |
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194 | (1) |
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5.3.2 Coordination with Other Standards |
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195 | (1) |
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195 | (2) |
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6 Analog Measurement Basics |
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197 | (24) |
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6.1 Analog In-Circuit Testing |
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197 | (14) |
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198 | (2) |
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6.1.2 Measuring an Impedance |
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200 | (4) |
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6.1.3 Errors and Corrections |
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204 | (2) |
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6.1.4 Measurement Hardware |
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206 | (5) |
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6.2 Limited Access Testing |
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211 | (6) |
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6.2.1 Node Voltage Analysis |
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212 | (1) |
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6.2.2 Testing With Node Voltages |
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213 | (2) |
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6.2.3 Limited Access Node Voltage Testing |
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215 | (2) |
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6.3 The Mixed-Signal Test Environment |
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217 | (3) |
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220 | (1) |
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7 IEEE 1149.4 Analog Boundary-Scan |
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221 | (42) |
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7.1 1149.4 Vocabulary and Basics |
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222 | (5) |
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7.1.1 The Target Fault Spectrum |
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223 | (1) |
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7.1.2 Extended Interconnect |
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223 | (2) |
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225 | (1) |
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226 | (1) |
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7.2 General Architecture of an 1149.4 IC |
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227 | (16) |
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229 | (1) |
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7.2.2 The Analog Test Access Port (ATAP) |
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230 | (1) |
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7.2.3 The Test Bus Interface Circuit (TBIC) |
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231 | (5) |
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7.2.4 The Analog Boundary Module (ABM) |
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236 | (6) |
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7.2.5 The Digital Boundary Module (DBM) |
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242 | (1) |
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7.3 The 1149.4 Instruction Set |
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243 | (7) |
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7.3.1 The EXTEST Instruction |
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244 | (3) |
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7.3.2 The CLAMP Instruction |
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247 | (1) |
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7.3.3 The HIGHZ Instruction |
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247 | (1) |
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7.3.4 The PROBE Instruction |
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247 | (1) |
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7.3.5 The RUNBIST Instruction |
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248 | (1) |
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7.3.6 The INTEST Instruction |
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248 | (2) |
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7.4 Other Provisions of 1149.4 |
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250 | (7) |
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7.4.1 Differential ATAP Port |
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250 | (1) |
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251 | (2) |
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7.4.3 Partitioned Internal Test Buses |
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253 | (3) |
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7.4.4 Specifications and Limits |
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256 | (1) |
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7.5 Design for 1149.4 Testability |
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257 | (4) |
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7.5.1 Integrated Circuit Level |
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257 | (2) |
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259 | (1) |
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260 | (1) |
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261 | (1) |
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7.7 Eilog: What Next for 1149.1/1149.4? |
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262 | (1) |
APPENDIX A: BSDL Syntax Specifications |
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263 | (12) |
A.1 Conventions |
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263 | (1) |
A.2 Lexical elements of BSDL |
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264 | (3) |
A.3 Notes on syntax definition |
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267 | (2) |
A.4 BSDL Syntax |
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269 | (4) |
A.5 User Package Syntax |
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273 | (2) |
Bibliography |
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275 | (6) |
Index |
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281 | |