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Circuit Design with VHDL third edition [Kõva köide]

(UTFPR Federal Technological University of Parana State)
  • Formaat: Hardback, 608 pages, kõrgus x laius x paksus: 229x178x32 mm, 276 b&w illus.; 552 Illustrations
  • Sari: The MIT Press
  • Ilmumisaeg: 14-Apr-2020
  • Kirjastus: MIT Press
  • ISBN-10: 0262042649
  • ISBN-13: 9780262042642
Teised raamatud teemal:
  • Formaat: Hardback, 608 pages, kõrgus x laius x paksus: 229x178x32 mm, 276 b&w illus.; 552 Illustrations
  • Sari: The MIT Press
  • Ilmumisaeg: 14-Apr-2020
  • Kirjastus: MIT Press
  • ISBN-10: 0262042649
  • ISBN-13: 9780262042642
Teised raamatud teemal:
A completely updated and expanded comprehensive treatment of VHDL and its applications to the design and simulation of real, industry-standard circuits.

A completely updated and expanded comprehensive treatment of VHDL and its applications to the design and simulation of real, industry-standard circuits.

This comprehensive treatment of VHDL and its applications to the design and simulation of real, industry-standard circuits has been completely updated and expanded for the third edition. New features include all VHDL-2008 constructs, an extensive review of digital circuits, RTL analysis, and an unequaled collection of VHDL examples and exercises. The book focuses on the use of VHDL rather than solely on the language, with an emphasis on design examples and laboratory exercises.

The third edition begins with a detailed review of digital circuits (combinatorial, sequential, state machines, and FPGAs), thus providing a self-contained single reference for the teaching of digital circuit design with VHDL. In its coverage of VHDL-2008, it makes a clear distinction between VHDL for synthesis and VHDL for simulation. The text offers complete VHDL codes in examples as well as simulation results and comments. The significantly expanded examples and exercises include many not previously published, with multiple physical demonstrations meant to inspire and motivate students.

The book is suitable for undergraduate and graduate students in VHDL and digital circuit design, and can be used as a professional reference for VHDL practitioners. It can also serve as a text for digital VLSI in-house or academic courses.

Preface xv
Acknowledgments xvii
1 Review of Combinational Circuits
1(28)
1.1 Combinational Circuits
1(1)
1.2 Fundamental Logic Gates
2(1)
1.3 Chain-Type versus Tree-Type Structures
3(1)
1.4 Examples of Combinational Logic Circuits
4(6)
1.4.1 Multiplexer
4(1)
1.4.2 Address Decoder
5(1)
1.4.3 Parity Detector
6(1)
1.4.4 Priority Encoder
6(1)
1.4.5 Binary-to-BCD Converters
6(4)
1.5 Examples of Combinational Arithmetic Circuits
10(6)
1.5.1 Full-Adder Unit
10(1)
1.5.2 Carry-Ripple Adder
11(1)
1.5.3 Faster Adders (Manchester, Carry-Lookahead, and Kogge-Stone Tree)
11(1)
1.5.4 Adder Arrays
12(1)
1.5.5 Subtracters
13(1)
1.5.6 Incrementer, Decrementer, and Two's Complementer
14(1)
1.5.7 Parallel Multiplier
14(1)
1.5.8 Comparators (Equality and Greater-than/Equal-to)
14(1)
1.5.9 Arithmetic Logic Unit
15(1)
1.6 Binary Arithmetic
16(13)
1.6.1 Carry Bit and Overflow Flag
16(1)
1.6.2 Unsigned Integer Arithmetic
17(2)
1.6.3 Signed Integer Arithmetic
19(2)
1.6.4 Extension, Truncation, Rounding, and Saturation
21(3)
1.6.5 Floating-Point Arithmetic
24(5)
2 Review of Sequential Circuits
29(38)
2.1 Sequential Circuits
29(1)
2.2 Latches
29(2)
2.3 Flip-Flops
31(3)
2.4 Glitch Analysis and Prevention
34(1)
2.5 Register Transfer Level of Abstraction
35(1)
2.6 Initial Examples of Sequential Circuits
36(6)
2.6.1 Shift Registers
36(1)
2.6.2 Synchronous Modulo-2N Counters
37(1)
2.6.3 Synchronous Modulo-M Counters
38(1)
2.6.4 Asynchronous Counters
38(1)
2.6.5 Gray, Johnson, and One-Hot Counters
39(2)
2.6.6 Signal Generators
41(1)
2.6.7 Clock Dividers
41(1)
2.6.8 Timers and Sequential Binary-to-BCD Converters
41(1)
2.6.9 Tapped Delay Line
41(1)
2.7 Clock Division
42(4)
2.7.1 Common Clock Division Cases
42(1)
2.7.2 Clock Division by Any Integer with Symmetric Phase
43(1)
2.7.3 The Cost of Clock Division by an Even Integer
44(2)
2.7.4 Breaking a Large Clock Divider into Smaller Serial Clock Dividers
46(1)
2.8 Clock Multiplication and Phase-Locked Loops (PLLs)
46(2)
2.9 Asynchronous Data and Synchronizers
48(5)
2.9.1 Clock-Domain Crossing
49(1)
2.9.2 A Practical Example: Frequency Meters
49(3)
2.9.3 Dealing with Reset
52(1)
2.10 Clock Gating
53(1)
2.11 Additional Examples of Sequential Circuits
54(13)
2.11.1 One-Shot and Pulse-Capturer Circuits
54(1)
2.11.2 Switch Debouncers
55(3)
2.11.3 Reference-Value Generators
58(1)
2.11.4 Pulse Width Modulator
59(1)
2.11.5 Pseudo-Random Sequence Generators
60(1)
2.11.6 Digital Finite Impulse Response (FIR) Filters
61(3)
2.11.7 Digital Infinite Impulse Response (IIR) Filters
64(1)
2.11.8 Serializer and Deserializer Circuits
65(2)
3 Review of Finite State Machines
67(34)
3.1 Finite State Machines
67(1)
3.2 State Transition Diagram and Machine Types
68(2)
3.3 Representing versus Implementing
70(1)
3.4 Moore-to-Mealy and Mealy-to-Moore Conversion
70(1)
3.5 Time Behavior of Moore versus Mealy Machines
71(2)
3.6 Choosing between Moore and Mealy Machines
73(1)
3.7 Transition Types
74(1)
3.8 Incorrect State Transition Diagrams
75(3)
3.9 Safe State Machines
78(1)
3.10 Fundamental Hardware Architectures for FSMs
78(1)
3.11 Encoding Styles
79(1)
3.12 Fundamental Design Technique for FSMs
79(3)
3.13 State Machine Categories
82(1)
3.14 Dealing with Time
83(2)
3.15 Dealing with Repetitive States
85(1)
3.16 Pointer-Based FSM Implementation
86(1)
3.17 Dealing with Recursivity
86(2)
3.18 Number of Flip-Flops in FSMs
88(1)
3.19 Examples of Category 1 (Regular) State Machines
88(5)
3.19.1 Arbiter
89(1)
3.19.2 Garage Door Controller
89(1)
3.19.3 Datapath Control for a Greatest Common Divisor
90(3)
3.20 Examples of Category 2 (Timed) State Machines
93(3)
3.20.1 Car Alarm
93(1)
3.20.2 Password Decoder
94(1)
3.20.3 Serial Peripheral Interface for an A/D Converter
95(1)
3.21 Examples of Category 3 (Recursive) State Machines
96(5)
3.21.1 SRAM Memory Interface
97(1)
3.21.2 Datapath Controller for a Serial Multiplier
97(2)
3.21.3 Reference-Value Definer with Embedded Debouncers
99(2)
4 Review of Field Programmable Gate Arrays (FPGAs)
101(14)
4.1 Programmable Logic Devices
101(2)
4.2 PLD Configuration Memories
103(1)
4.3 PAL and PLA Devices
104(1)
4.4 GAL Devices
104(1)
4.5 CPLD Devices
105(2)
4.6 FPGA Devices
107(8)
5 Introduction to VHDL
115(14)
5.1 About VHDL
115(1)
5.2 Translation of VHDL Code into a Circuit
115(2)
5.3 Design Flow
117(2)
5.4 Commercial VHDL Tools
119(1)
5.5 RTL Design Approach
119(1)
5.6 Concurrent versus Sequential Statements
119(1)
5.7 Lexical Elements of VHDL
120(3)
5.7.1 Assignment Symbols
120(1)
5.7.2 Comments
120(1)
5.7.3 Bit and Bit String
121(1)
5.7.4 Integers
121(1)
5.7.5 Character and Character String
122(1)
5.7.6 Identifiers
122(1)
5.7.7 Delimiters
122(1)
5.7.8 Reserved VHDL Words
123(1)
5.8 Choosing Good Names for Your Design
123(6)
5.8.1 Naming an Entity Declaration ("The Design")
124(1)
5.8.2 Naming an Architecture Body
124(1)
5.8.3 Naming Constants
124(1)
5.8.4 Naming Signals and Variables
125(1)
5.8.5 Naming Functions and Procedures
125(1)
5.8.6 Naming Types
126(1)
5.8.7 Naming Files
127(2)
6 Code Structure and Composition
129(24)
6.1 Design Units and Code Structure
129(1)
6.2 Libraries and Packages
130(4)
6.3 Packages List in the Code
134(1)
6.4 Entity Declaration
135(3)
6.5 Architecture Body
138(1)
6.6 Object Classes
138(5)
6.6.1 Constant
139(1)
6.6.2 Signal
140(1)
6.6.3 Variable
141(1)
6.6.4 File
142(1)
6.7 Generics
143(2)
6.8 Entity-Architecture Binding
145(1)
6.9 Introductory VHDL Examples
145(8)
7 Predefined Data Types
153(40)
7.1 Predefined VHDL Types
153(1)
7.2 Type Classes
154(2)
7.3 Type Declarations
156(2)
7.4 Subtypes
158(1)
7.5 A Note on Operators and Attributes
159(1)
7.6 Study of Predefined Data Types
159(13)
7.6.1 Standard Types
160(2)
7.6.2 Standard-Logic Types
162(3)
7.6.3 Unsigned and Signed Types
165(1)
7.6.4 Fixed-Point Types
166(2)
7.6.5 Floating-Point Types
168(2)
7.6.6 Type real
170(2)
7.7 Record Types
172(1)
7.8 Access Types, File Types, and Protected Types
173(1)
7.9 Aggregation, Concatenation, and Resizing
173(5)
7.9.1 Data Aggregation
173(2)
7.9.2 Data Concatenation
175(1)
7.9.3 Resizing Data Arrays
175(3)
7.10 Type Conversion
178(5)
7.10.1 Automatic Conversion
178(1)
7.10.2 Type Cast
179(1)
7.10.3 Type-Conversion Functions
179(3)
7.10.4 Strength-Stripping Functions
182(1)
7.11 Type-Qualification Expressions
183(1)
7.12 Additional Examples
183(2)
7.13 Exercises
185(8)
8 User-Defined Data Types
193(20)
8.1 Review of Synthesizable Predefined Types
193(1)
8.2 User-Defined Types
193(3)
8.2.1 Integer Types
193(2)
8.2.2 Enumeration Types
195(1)
8.2.3 Array Types
195(1)
8.3 Building and Addressing Complex Array Types
196(3)
8.3.1 Array Dimensionality
196(1)
8.3.2 Predefined 1D Arrays
197(1)
8.3.3 Building 1D×1D Arrays
197(1)
8.3.4 Building 2D Arrays
198(1)
8.3.5 Building 1D×1D×1D Arrays
199(1)
8.3.6 Building 3D Arrays
199(1)
8.4 Checking and Resetting Data Arrays
199(2)
8.4.1 Zeroing Entire Data Arrays
200(1)
8.4.2 Checking Whether Data Arrays Contain Only Zeros
200(1)
8.5 Classical Mistakes in Assignments
201(3)
8.6 Additional Examples
204(4)
8.7 Exercises
208(5)
9 Operators and Attributes
213(30)
9.1 Predefined Operators
213(15)
9.1.1 Logical Operators
214(4)
9.1.2 Arithmetic Operators
218(5)
9.1.3 Comparison (Relational) Operators
223(3)
9.1.4 Shift Operators
226(1)
9.1.5 Concatenation Operator
227(1)
9.1.6 Condition Operator
227(1)
9.2 User-Defined Overloaded Operators
228(1)
9.3 Predefined Attributes
229(3)
9.3.1 Attributes of Scalar Types
229(1)
9.3.2 Attributes of Array Types and Objects
230(1)
9.3.3 Attributes of Signals
231(1)
9.3.4 Attributes of Named Entities
231(1)
9.4 User-Defined Attributes
232(2)
9.5 Synthesis Attributes
234(3)
9.5.1 State Machine Encoding Attributes
234(1)
9.5.2 Safe State Machine Attributes
235(1)
9.5.3 Keep-Logic Attribute
236(1)
9.5.4 ROM and RAM Implementation Attributes
237(1)
9.6 Group
237(1)
9.7 Alias
238(1)
9.8 Exercises
239(4)
10 Concurrent Code
243(22)
10.1 Concurrent Statements
243(3)
10.2 The when Statement
246(2)
10.3 The select Statement
248(1)
10.4 The generate Statement
249(3)
10.5 Component Instantiation Statements
252(4)
10.5.1 Component Instantiation
252(1)
10.5.2 Design Entity Instantiation
253(3)
10.6 Avoiding Multiple Assignments to the Same Signal
256(3)
10.7 Suggested Approaches for Arithmetic Circuits
259(5)
10.8 Additional Examples and Exercises
264(1)
11 Concurrent Code: Practice
265(18)
11.1 Additional Design Examples Using Concurrent Code
265(8)
Example 11.1 Vectors Absolute Difference Calculator
265(3)
Example 11.2 Programmable Combinational Delay Line (Structural)
268(2)
Example 11.3 Sine Calculator with Integers and ROM-Type Memory
270(3)
11.2 Exercises
273(10)
Part 1 Combinational Logic Circuits
274(3)
Part 2 Combinational Arithmetic Circuits
277(4)
Part 3 With Component Instantiation (Structural Code)
281(2)
12 Sequential Code
283(32)
12.1 Concurrent Code versus Sequential Code
283(1)
12.2 Detecting Clock Transitions: clk'event or rising_edge(clk)?
284(1)
12.3 The process Statement
285(3)
12.4 The if Statement
288(3)
12.5 The case Statement
291(3)
12.6 The waif Statement
294(1)
12.7 The loop Statement
295(2)
12.8 The Sequential when and select Statements
297(1)
12.9 Signal versus Variable
298(3)
12.10 More about the Updating Rule of Signals and Variables
301(6)
12.11 More about the Inference of Registers Rule
307(5)
12.12 The Problem of Combinational Loops
312(1)
12.13 Additional Examples and Exercises
313(2)
13 Sequential Code: Practice
315(11)
13.1 Additional Design Examples Using Sequential Code
315(11)
Example 13.1 Generic Tree-Type Adder Array
315(3)
Example 13.2 Single-Switch Debouncer
318(2)
Example 13.3 FIR Filter with Fixed Coefficients
320(2)
Example 13.4 Sequential Square-Root Calculator
322(4)
13.2 Exercises
326(1)
Part 1 Signal versus Variable
326(4)
Part 2 Combinational Circuits
330(1)
Part 3 Counters and Clock Dividers
330(2)
Part 4 Timers and Associated Circuits
332(5)
Part 5 Synchronism
337(2)
Part 6 Shifters
339(1)
Part 7 Controllers
340(3)
Part 8 Serial Arithmetic Circuits
343(4)
Part 9 Filters
347(1)
Part 10 With Component Instantiation (Structural Code)
347(150)
14 Packages and Subprograms
349(24)
14.1 Package
349(2)
14.2 Package with Generics
351(2)
14.3 Function
353(6)
14.4 Procedure
359(4)
14.5 Function versus Procedure Summary
363(1)
14.6 Subprogram with Generics and Generic Subprograms
364(2)
14.7 Overloaded Subprograms
366(1)
14.8 Assert and Report Statements
367(2)
14.9 Exercises
369(4)
15 The Case of State Machines
373(34)
15.1 The Finite State Machine Approach
373(2)
15.2 State Encoding Styles
375(1)
15.3 VHDL for Regular (Category 1) State Machines
375(12)
15.3.1 Hardware Architecture of Regular State Machines
376(1)
15.3.2 Simple Moore-to-Mealy Conversion
376(2)
15.3.3 VHDL Templates for Regular State Machines
378(9)
15.4 VHDL for Timed (Category 2) State Machines
387(8)
15.4.1 Hardware Architecture of Timed State Machines
387(1)
15.4.2 VHDL Templates for Timed State Machines
388(7)
15.5 VHDL for Recursive (Category 3) State Machines
395(7)
15.5.1 Hardware Architecture of Recursive State Machines
395(1)
15.5.2 VHDL Templates for Recursive State Machines
395(7)
15.6 Summarizing (and Simplifying) Things
402(1)
15.7 Exercises
402(5)
16 The Case of State Machines: Practice
407(20)
16.1 Design Examples of Regular (Category 1) State Machines
407(5)
16.2 Design Examples of Timed (Category 2) State Machines
412(4)
16.3 Design Examples of Recursive (Category 3) State Machines
416(5)
16.4 Exercises
421(5)
Part 1 Exercises with Regular FSMs
421(1)
Part 2 Exercises with Timed FSMs
422(3)
Part 3 Exercises with Recursive FSMs
425(1)
16.5 Exercises with SPI, I2C, and LCD Interfaces
426(1)
17 Additional Design Examples
427(48)
17.1 Additional Design Examples
427(41)
Example 17.1 SPI Interface for an EEPROM Device (with FSM)
428(6)
Example 17.2 SPI Interface for an EEPROM Device (with Pointer)
434(6)
Example 17.3 I2C Interface for an A/D Converter (with Pointer)
440(4)
Example 17.4 I2C Interface for an A/D Converter (with Pointer Built with FSM)
444(3)
Example 17.5 Digital Watch with Liquid Crystal Display (LCD)
447(7)
Example 17.6 VGA Video Interface for a Hardware-Generated Image
454(4)
Example 17.7 DVI Video Interface for a Hardware-Generated Image
458(6)
Example 17.8 TMDS 8B/10B Encoder
464(4)
17.2 Exercises
468(7)
Part 1 Exercises with SPI Protocol
468(1)
Part 2 Exercises with I2C Protocol
469(2)
Part 3 Exercises with Alphanumeric LCD
471(1)
Part 4 Exercises with VGA Video Driver
472(1)
Part 5 Exercises with DVI Video Driver
473(2)
18 Introduction to Simulation with Testbenches
475(22)
18.1 Testbenches
475(1)
18.2 Dealing with Time in VHDL
476(2)
18.3 Stimuli Generation
478(4)
18.4 Complete Testbenches
482(7)
18.5 Practical Considerations on Functional and Timing Simulations
489(1)
18.6 Dealing with Data Files
490(5)
18.7 Running Simulation with Tel Scripts
495(1)
18.8 Exercises
495(2)
Appendix A Vivado Tutorial 497(14)
Appendix B Quartus Prime Tutorial 511(10)
Appendix C ModelSim Tutorial 521(10)
Appendix D Simulation Analysis and Recommendations 531(2)
Appendix E Using Seven-Segment Displays with VHDL 533(4)
Appendix F Serial Peripheral Interface 537(4)
Appendix G I2C (Inter Integrated Circuits) Interface 541(4)
Appendix H Alphanumeric LCD 545(6)
Appendix I VGA Video Interface 551(4)
Appendix J DVI Video Interface 555(4)
Appendix K TMDS Link 559(4)
Appendix L Using Phase-Locked Loops with VHDL 563(8)
Appendix M List of Enumerated Examples and Exercises 571(10)
Bibliography 581(2)
Index 583