Preface |
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xv | |
Acknowledgments |
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xvii | |
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1 Review of Combinational Circuits |
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1 | (28) |
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1.1 Combinational Circuits |
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1 | (1) |
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1.2 Fundamental Logic Gates |
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2 | (1) |
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1.3 Chain-Type versus Tree-Type Structures |
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3 | (1) |
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1.4 Examples of Combinational Logic Circuits |
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4 | (6) |
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4 | (1) |
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5 | (1) |
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6 | (1) |
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6 | (1) |
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1.4.5 Binary-to-BCD Converters |
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6 | (4) |
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1.5 Examples of Combinational Arithmetic Circuits |
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10 | (6) |
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10 | (1) |
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11 | (1) |
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1.5.3 Faster Adders (Manchester, Carry-Lookahead, and Kogge-Stone Tree) |
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11 | (1) |
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12 | (1) |
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13 | (1) |
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1.5.6 Incrementer, Decrementer, and Two's Complementer |
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14 | (1) |
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1.5.7 Parallel Multiplier |
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14 | (1) |
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1.5.8 Comparators (Equality and Greater-than/Equal-to) |
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14 | (1) |
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1.5.9 Arithmetic Logic Unit |
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15 | (1) |
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16 | (13) |
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1.6.1 Carry Bit and Overflow Flag |
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16 | (1) |
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1.6.2 Unsigned Integer Arithmetic |
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17 | (2) |
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1.6.3 Signed Integer Arithmetic |
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19 | (2) |
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1.6.4 Extension, Truncation, Rounding, and Saturation |
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21 | (3) |
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1.6.5 Floating-Point Arithmetic |
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24 | (5) |
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2 Review of Sequential Circuits |
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29 | (38) |
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29 | (1) |
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29 | (2) |
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31 | (3) |
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2.4 Glitch Analysis and Prevention |
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34 | (1) |
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2.5 Register Transfer Level of Abstraction |
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35 | (1) |
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2.6 Initial Examples of Sequential Circuits |
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36 | (6) |
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36 | (1) |
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2.6.2 Synchronous Modulo-2N Counters |
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37 | (1) |
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2.6.3 Synchronous Modulo-M Counters |
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38 | (1) |
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2.6.4 Asynchronous Counters |
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38 | (1) |
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2.6.5 Gray, Johnson, and One-Hot Counters |
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39 | (2) |
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41 | (1) |
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41 | (1) |
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2.6.8 Timers and Sequential Binary-to-BCD Converters |
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41 | (1) |
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41 | (1) |
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42 | (4) |
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2.7.1 Common Clock Division Cases |
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42 | (1) |
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2.7.2 Clock Division by Any Integer with Symmetric Phase |
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43 | (1) |
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2.7.3 The Cost of Clock Division by an Even Integer |
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44 | (2) |
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2.7.4 Breaking a Large Clock Divider into Smaller Serial Clock Dividers |
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46 | (1) |
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2.8 Clock Multiplication and Phase-Locked Loops (PLLs) |
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46 | (2) |
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2.9 Asynchronous Data and Synchronizers |
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48 | (5) |
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2.9.1 Clock-Domain Crossing |
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49 | (1) |
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2.9.2 A Practical Example: Frequency Meters |
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49 | (3) |
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52 | (1) |
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53 | (1) |
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2.11 Additional Examples of Sequential Circuits |
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54 | (13) |
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2.11.1 One-Shot and Pulse-Capturer Circuits |
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54 | (1) |
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55 | (3) |
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2.11.3 Reference-Value Generators |
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58 | (1) |
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2.11.4 Pulse Width Modulator |
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59 | (1) |
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2.11.5 Pseudo-Random Sequence Generators |
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60 | (1) |
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2.11.6 Digital Finite Impulse Response (FIR) Filters |
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61 | (3) |
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2.11.7 Digital Infinite Impulse Response (IIR) Filters |
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64 | (1) |
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2.11.8 Serializer and Deserializer Circuits |
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65 | (2) |
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3 Review of Finite State Machines |
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67 | (34) |
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3.1 Finite State Machines |
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67 | (1) |
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3.2 State Transition Diagram and Machine Types |
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68 | (2) |
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3.3 Representing versus Implementing |
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70 | (1) |
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3.4 Moore-to-Mealy and Mealy-to-Moore Conversion |
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70 | (1) |
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3.5 Time Behavior of Moore versus Mealy Machines |
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71 | (2) |
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3.6 Choosing between Moore and Mealy Machines |
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73 | (1) |
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74 | (1) |
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3.8 Incorrect State Transition Diagrams |
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75 | (3) |
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78 | (1) |
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3.10 Fundamental Hardware Architectures for FSMs |
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78 | (1) |
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79 | (1) |
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3.12 Fundamental Design Technique for FSMs |
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79 | (3) |
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3.13 State Machine Categories |
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82 | (1) |
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83 | (2) |
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3.15 Dealing with Repetitive States |
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85 | (1) |
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3.16 Pointer-Based FSM Implementation |
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86 | (1) |
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3.17 Dealing with Recursivity |
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86 | (2) |
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3.18 Number of Flip-Flops in FSMs |
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88 | (1) |
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3.19 Examples of Category 1 (Regular) State Machines |
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88 | (5) |
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89 | (1) |
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3.19.2 Garage Door Controller |
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89 | (1) |
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3.19.3 Datapath Control for a Greatest Common Divisor |
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90 | (3) |
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3.20 Examples of Category 2 (Timed) State Machines |
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93 | (3) |
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93 | (1) |
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94 | (1) |
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3.20.3 Serial Peripheral Interface for an A/D Converter |
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95 | (1) |
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3.21 Examples of Category 3 (Recursive) State Machines |
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96 | (5) |
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3.21.1 SRAM Memory Interface |
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97 | (1) |
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3.21.2 Datapath Controller for a Serial Multiplier |
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97 | (2) |
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3.21.3 Reference-Value Definer with Embedded Debouncers |
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99 | (2) |
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4 Review of Field Programmable Gate Arrays (FPGAs) |
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101 | (14) |
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4.1 Programmable Logic Devices |
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101 | (2) |
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4.2 PLD Configuration Memories |
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103 | (1) |
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104 | (1) |
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104 | (1) |
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105 | (2) |
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107 | (8) |
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115 | (14) |
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115 | (1) |
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5.2 Translation of VHDL Code into a Circuit |
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115 | (2) |
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117 | (2) |
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5.4 Commercial VHDL Tools |
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119 | (1) |
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119 | (1) |
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5.6 Concurrent versus Sequential Statements |
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119 | (1) |
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5.7 Lexical Elements of VHDL |
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120 | (3) |
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120 | (1) |
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120 | (1) |
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121 | (1) |
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121 | (1) |
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5.7.5 Character and Character String |
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122 | (1) |
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122 | (1) |
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122 | (1) |
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5.7.8 Reserved VHDL Words |
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123 | (1) |
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5.8 Choosing Good Names for Your Design |
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123 | (6) |
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5.8.1 Naming an Entity Declaration ("The Design") |
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124 | (1) |
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5.8.2 Naming an Architecture Body |
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124 | (1) |
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124 | (1) |
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5.8.4 Naming Signals and Variables |
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125 | (1) |
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5.8.5 Naming Functions and Procedures |
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125 | (1) |
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126 | (1) |
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127 | (2) |
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6 Code Structure and Composition |
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129 | (24) |
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6.1 Design Units and Code Structure |
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129 | (1) |
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6.2 Libraries and Packages |
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130 | (4) |
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6.3 Packages List in the Code |
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134 | (1) |
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135 | (3) |
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138 | (1) |
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138 | (5) |
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139 | (1) |
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140 | (1) |
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141 | (1) |
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142 | (1) |
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143 | (2) |
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6.8 Entity-Architecture Binding |
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145 | (1) |
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6.9 Introductory VHDL Examples |
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145 | (8) |
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153 | (40) |
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7.1 Predefined VHDL Types |
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153 | (1) |
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154 | (2) |
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156 | (2) |
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158 | (1) |
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7.5 A Note on Operators and Attributes |
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159 | (1) |
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7.6 Study of Predefined Data Types |
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159 | (13) |
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160 | (2) |
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7.6.2 Standard-Logic Types |
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162 | (3) |
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7.6.3 Unsigned and Signed Types |
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165 | (1) |
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166 | (2) |
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7.6.5 Floating-Point Types |
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168 | (2) |
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170 | (2) |
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172 | (1) |
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7.8 Access Types, File Types, and Protected Types |
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173 | (1) |
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7.9 Aggregation, Concatenation, and Resizing |
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173 | (5) |
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173 | (2) |
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175 | (1) |
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7.9.3 Resizing Data Arrays |
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175 | (3) |
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178 | (5) |
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7.10.1 Automatic Conversion |
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178 | (1) |
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179 | (1) |
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7.10.3 Type-Conversion Functions |
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179 | (3) |
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7.10.4 Strength-Stripping Functions |
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182 | (1) |
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7.11 Type-Qualification Expressions |
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183 | (1) |
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183 | (2) |
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185 | (8) |
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8 User-Defined Data Types |
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193 | (20) |
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8.1 Review of Synthesizable Predefined Types |
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193 | (1) |
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193 | (3) |
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193 | (2) |
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195 | (1) |
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195 | (1) |
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8.3 Building and Addressing Complex Array Types |
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196 | (3) |
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8.3.1 Array Dimensionality |
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196 | (1) |
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8.3.2 Predefined 1D Arrays |
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197 | (1) |
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8.3.3 Building 1D×1D Arrays |
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197 | (1) |
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198 | (1) |
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8.3.5 Building 1D×1D×1D Arrays |
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199 | (1) |
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199 | (1) |
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8.4 Checking and Resetting Data Arrays |
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199 | (2) |
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8.4.1 Zeroing Entire Data Arrays |
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200 | (1) |
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8.4.2 Checking Whether Data Arrays Contain Only Zeros |
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200 | (1) |
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8.5 Classical Mistakes in Assignments |
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201 | (3) |
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204 | (4) |
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208 | (5) |
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9 Operators and Attributes |
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213 | (30) |
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213 | (15) |
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214 | (4) |
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9.1.2 Arithmetic Operators |
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218 | (5) |
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9.1.3 Comparison (Relational) Operators |
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223 | (3) |
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226 | (1) |
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9.1.5 Concatenation Operator |
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227 | (1) |
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227 | (1) |
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9.2 User-Defined Overloaded Operators |
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228 | (1) |
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9.3 Predefined Attributes |
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229 | (3) |
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9.3.1 Attributes of Scalar Types |
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229 | (1) |
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9.3.2 Attributes of Array Types and Objects |
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230 | (1) |
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9.3.3 Attributes of Signals |
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231 | (1) |
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9.3.4 Attributes of Named Entities |
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231 | (1) |
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9.4 User-Defined Attributes |
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232 | (2) |
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234 | (3) |
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9.5.1 State Machine Encoding Attributes |
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234 | (1) |
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9.5.2 Safe State Machine Attributes |
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235 | (1) |
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9.5.3 Keep-Logic Attribute |
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236 | (1) |
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9.5.4 ROM and RAM Implementation Attributes |
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237 | (1) |
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237 | (1) |
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238 | (1) |
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239 | (4) |
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243 | (22) |
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10.1 Concurrent Statements |
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243 | (3) |
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246 | (2) |
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10.3 The select Statement |
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248 | (1) |
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10.4 The generate Statement |
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249 | (3) |
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10.5 Component Instantiation Statements |
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252 | (4) |
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10.5.1 Component Instantiation |
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252 | (1) |
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10.5.2 Design Entity Instantiation |
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253 | (3) |
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10.6 Avoiding Multiple Assignments to the Same Signal |
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256 | (3) |
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10.7 Suggested Approaches for Arithmetic Circuits |
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259 | (5) |
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10.8 Additional Examples and Exercises |
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264 | (1) |
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11 Concurrent Code: Practice |
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265 | (18) |
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11.1 Additional Design Examples Using Concurrent Code |
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265 | (8) |
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Example 11.1 Vectors Absolute Difference Calculator |
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265 | (3) |
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Example 11.2 Programmable Combinational Delay Line (Structural) |
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268 | (2) |
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Example 11.3 Sine Calculator with Integers and ROM-Type Memory |
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270 | (3) |
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273 | (10) |
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Part 1 Combinational Logic Circuits |
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274 | (3) |
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Part 2 Combinational Arithmetic Circuits |
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277 | (4) |
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Part 3 With Component Instantiation (Structural Code) |
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281 | (2) |
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283 | (32) |
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12.1 Concurrent Code versus Sequential Code |
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283 | (1) |
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12.2 Detecting Clock Transitions: clk'event or rising_edge(clk)? |
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284 | (1) |
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12.3 The process Statement |
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285 | (3) |
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288 | (3) |
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291 | (3) |
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294 | (1) |
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295 | (2) |
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12.8 The Sequential when and select Statements |
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297 | (1) |
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12.9 Signal versus Variable |
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298 | (3) |
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12.10 More about the Updating Rule of Signals and Variables |
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301 | (6) |
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12.11 More about the Inference of Registers Rule |
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307 | (5) |
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12.12 The Problem of Combinational Loops |
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312 | (1) |
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12.13 Additional Examples and Exercises |
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313 | (2) |
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13 Sequential Code: Practice |
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315 | (11) |
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13.1 Additional Design Examples Using Sequential Code |
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315 | (11) |
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Example 13.1 Generic Tree-Type Adder Array |
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315 | (3) |
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Example 13.2 Single-Switch Debouncer |
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318 | (2) |
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Example 13.3 FIR Filter with Fixed Coefficients |
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320 | (2) |
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Example 13.4 Sequential Square-Root Calculator |
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322 | (4) |
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326 | (1) |
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Part 1 Signal versus Variable |
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326 | (4) |
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Part 2 Combinational Circuits |
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330 | (1) |
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Part 3 Counters and Clock Dividers |
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330 | (2) |
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Part 4 Timers and Associated Circuits |
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332 | (5) |
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337 | (2) |
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339 | (1) |
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340 | (3) |
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Part 8 Serial Arithmetic Circuits |
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343 | (4) |
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347 | (1) |
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Part 10 With Component Instantiation (Structural Code) |
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347 | (150) |
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14 Packages and Subprograms |
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349 | (24) |
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349 | (2) |
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14.2 Package with Generics |
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351 | (2) |
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353 | (6) |
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359 | (4) |
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14.5 Function versus Procedure Summary |
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363 | (1) |
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14.6 Subprogram with Generics and Generic Subprograms |
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364 | (2) |
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14.7 Overloaded Subprograms |
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366 | (1) |
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14.8 Assert and Report Statements |
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367 | (2) |
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369 | (4) |
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15 The Case of State Machines |
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373 | (34) |
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15.1 The Finite State Machine Approach |
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373 | (2) |
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15.2 State Encoding Styles |
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375 | (1) |
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15.3 VHDL for Regular (Category 1) State Machines |
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375 | (12) |
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15.3.1 Hardware Architecture of Regular State Machines |
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376 | (1) |
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15.3.2 Simple Moore-to-Mealy Conversion |
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376 | (2) |
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15.3.3 VHDL Templates for Regular State Machines |
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378 | (9) |
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15.4 VHDL for Timed (Category 2) State Machines |
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387 | (8) |
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15.4.1 Hardware Architecture of Timed State Machines |
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387 | (1) |
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15.4.2 VHDL Templates for Timed State Machines |
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388 | (7) |
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15.5 VHDL for Recursive (Category 3) State Machines |
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395 | (7) |
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15.5.1 Hardware Architecture of Recursive State Machines |
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395 | (1) |
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15.5.2 VHDL Templates for Recursive State Machines |
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395 | (7) |
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15.6 Summarizing (and Simplifying) Things |
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402 | (1) |
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402 | (5) |
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16 The Case of State Machines: Practice |
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407 | (20) |
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16.1 Design Examples of Regular (Category 1) State Machines |
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407 | (5) |
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16.2 Design Examples of Timed (Category 2) State Machines |
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412 | (4) |
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16.3 Design Examples of Recursive (Category 3) State Machines |
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416 | (5) |
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421 | (5) |
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Part 1 Exercises with Regular FSMs |
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421 | (1) |
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Part 2 Exercises with Timed FSMs |
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422 | (3) |
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Part 3 Exercises with Recursive FSMs |
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425 | (1) |
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16.5 Exercises with SPI, I2C, and LCD Interfaces |
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426 | (1) |
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17 Additional Design Examples |
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427 | (48) |
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17.1 Additional Design Examples |
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427 | (41) |
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Example 17.1 SPI Interface for an EEPROM Device (with FSM) |
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428 | (6) |
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Example 17.2 SPI Interface for an EEPROM Device (with Pointer) |
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434 | (6) |
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Example 17.3 I2C Interface for an A/D Converter (with Pointer) |
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440 | (4) |
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Example 17.4 I2C Interface for an A/D Converter (with Pointer Built with FSM) |
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444 | (3) |
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Example 17.5 Digital Watch with Liquid Crystal Display (LCD) |
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447 | (7) |
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Example 17.6 VGA Video Interface for a Hardware-Generated Image |
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454 | (4) |
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Example 17.7 DVI Video Interface for a Hardware-Generated Image |
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458 | (6) |
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Example 17.8 TMDS 8B/10B Encoder |
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464 | (4) |
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468 | (7) |
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Part 1 Exercises with SPI Protocol |
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468 | (1) |
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Part 2 Exercises with I2C Protocol |
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469 | (2) |
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Part 3 Exercises with Alphanumeric LCD |
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471 | (1) |
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Part 4 Exercises with VGA Video Driver |
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472 | (1) |
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Part 5 Exercises with DVI Video Driver |
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473 | (2) |
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18 Introduction to Simulation with Testbenches |
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475 | (22) |
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475 | (1) |
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18.2 Dealing with Time in VHDL |
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476 | (2) |
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478 | (4) |
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18.4 Complete Testbenches |
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482 | (7) |
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18.5 Practical Considerations on Functional and Timing Simulations |
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489 | (1) |
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18.6 Dealing with Data Files |
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490 | (5) |
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18.7 Running Simulation with Tel Scripts |
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495 | (1) |
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495 | (2) |
Appendix A Vivado Tutorial |
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497 | (14) |
Appendix B Quartus Prime Tutorial |
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511 | (10) |
Appendix C ModelSim Tutorial |
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521 | (10) |
Appendix D Simulation Analysis and Recommendations |
|
531 | (2) |
Appendix E Using Seven-Segment Displays with VHDL |
|
533 | (4) |
Appendix F Serial Peripheral Interface |
|
537 | (4) |
Appendix G I2C (Inter Integrated Circuits) Interface |
|
541 | (4) |
Appendix H Alphanumeric LCD |
|
545 | (6) |
Appendix I VGA Video Interface |
|
551 | (4) |
Appendix J DVI Video Interface |
|
555 | (4) |
Appendix K TMDS Link |
|
559 | (4) |
Appendix L Using Phase-Locked Loops with VHDL |
|
563 | (8) |
Appendix M List of Enumerated Examples and Exercises |
|
571 | (10) |
Bibliography |
|
581 | (2) |
Index |
|
583 | |