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CMOS: Circuit Design, Layout, and Simulation 3rd edition [Kõva köide]

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  • Formaat: Hardback, 1208 pages, kõrgus x laius x paksus: 236x158x46 mm, kaal: 1565 g, Drawings: 1000 B&W, 0 Color
  • Sari: IEEE Press Series on Microelectronic Systems
  • Ilmumisaeg: 01-Oct-2010
  • Kirjastus: Wiley-IEEE Press
  • ISBN-10: 0470881321
  • ISBN-13: 9780470881323
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CMOS: Circuit Design, Layout, and Simulation 3rd editionSuurem pilt
  • Formaat: Hardback, 1208 pages, kõrgus x laius x paksus: 236x158x46 mm, kaal: 1565 g, Drawings: 1000 B&W, 0 Color
  • Sari: IEEE Press Series on Microelectronic Systems
  • Ilmumisaeg: 01-Oct-2010
  • Kirjastus: Wiley-IEEE Press
  • ISBN-10: 0470881321
  • ISBN-13: 9780470881323
Teised raamatud teemal:
Püsilink: https://www.kriso.ee/db/9780470881323.html
Märksõnad:
The third edition of CMOS: Circuit Design, Layout, and Simulation continues to cover the practical design of both analog and digital integrated circuits, offering a vital, contemporary view of a wide range of analog/digital circuit blocks, the BSIM model, data converter architectures, and much more-- The third edition of CMOS: Circuit Design, Layout, and Simulation continues to cover the practical design of both analog and digital integrated circuits, offering a vital, contemporary view of a wide range of analog/digital circuit blocks, the BSIM model, data converter architectures, and much more. The 3rd edition completes the revised 2nd edition by adding one more chapter (chapter 30) at the end, which describes on implementing the data converter topologies discussed in Chapter 29. This additional,practical information should make the book even more useful as an academic text and companion for the working design engineer. Images, data presented throughout the book were updated, and more practical examples, problems are presented in this new eition to enhance the practicality of the book-- Provided by publisher. The Third Edition of CMOS Circuit Design, Layout, and Simulation continues to cover the practical design of both analog and digital integrated circuits, offering a vital, contemporary view of a wide range of analog/digital circuit blocks including: phase-locked-loops, delta-sigma sensing circuits, voltage/current references, op-amps, the design of data converters, and much more. Regardless of ones integrated circuit (IC) design skill level, this book allows readers to experience both the theory behind, and the hands-on implementation of, complementary metal oxide semiconductor (CMOS)IC design via detailed derivations, discussions, and hundreds of design, layout, and simulation examples.Inside, readers will continue to find the relevant and practical material that made the first two editions bestsellers. The Third Edition has been updated and includes new chapters covering the implementation of data converters and the analysis/design of feedback amplifiers. The additional material makes the book even more useful as an academic text and companion for the working design engineer.The books accompanying Web site, CMOSedu.com, offers numerous examples for many computer-aided design (CAD) tools including Cadence, Electric, HSPICE, LASI, LTspice, Spectre, and WinSpice, Readers can recreate, modify, or simulate the design examples presented in the book. In addition, the solutions to the books end-of-chapter problems, the books figures, and additional homework problems without solutions are found at CMOSedu.com.This Third Editiono CMOS: Circuit Design, Layout, and Simulation is the ideal companion for undergraduate and graduate students in electrical and computer engineering as well as both novice and senior engineers working on transistor-level integrated circuit design. The third edition of CMOS: Circuit Design, Layout, and Simulation continues to cover the practical design of both analog and digital integrated circuits, offering a vital, contemporary view of a wide range of analog/digital circuit blocks, the BSIM model, data converter architectures, and much more. The 3rd edition completes the revised 2nd edition by adding one more chapter (Chapter 30) at the end, which describes on implementing the data converter topologies discussed in Chapter 29. This additional, practical information should make the book even more useful as an academic text and companion for the working design engineer.  Images, data presented throughout the book were updated, and more practical examples, problems are presented in this new eition to enhance the practicality of the book.
Preface xxxi
Chapter 1 Introduction to CMOS Design
1(30)
1.1 The CMOS IC Design Process
1(5)
1.1.1 Fabrication
3(1)
Layout and Cross-Sectional Views
4(2)
1.2 CMOS Background
6(2)
The CMOS Acronym
6(1)
CMOS Inverter
7(1)
The First CMOS Circuits
7(1)
Analog Design in CMOS
8(1)
1.3 An Introduction to Spice
8(23)
Generating a Netlist File
8(1)
Operating Point
9(1)
Transfer Function Analysis
10(1)
The Voltage-Controlled Voltage Source
11(1)
An Ideal Op-Amp
12(1)
The Subcircuit
13(1)
DC Analysis
13(1)
Plotting IV Curves
14(1)
Dual Loop DC Analysis
15(1)
Transient Analysis
15(1)
The SIN Source
16(1)
An RC Circuit Example
17(1)
Another RC Circuit Example
18(1)
AC Analysis
19(1)
Decades and Octaves
20(1)
Decibels
20(1)
Pulse Statement
21(1)
Finite Pulse Rise time
21(1)
Step Response
22(1)
Delay and Rise time in RC Circuits
22(1)
Piece-Wise Linear (PWL) Source
23(1)
Simulating Switches
24(1)
Initial Conditions on a Capacitor
24(1)
Initial Conditions in an Inductor
25(1)
Q of an LC Tank
25(1)
Frequency Response of an Ideal Integrator
26(1)
Unity-Gain Frequency
26(1)
Time-Domain Behavior of the Integrator
27(1)
Convergence
28(1)
Some Common Mistakes and Helpful Techniques
29(2)
Chapter 2 The Well
31(28)
The Substrate (The Unprocessed Wafer)
31(1)
A Parasitic Diode
31(1)
Using the N-well as a Resistor
32(1)
2.1 Patterning
32(4)
2.1.1 Patterning the N-well
35(1)
2.2 Laying Out the N-well
36(1)
2.2.1 Design Rules for the N-well
36(1)
2.3 Resistance Calculation
37(2)
Layout of Corners
38(1)
2.3.1 The N-well Resistor
38(1)
2.4 The N-well/Substrate Diode
39(10)
2.4.1 A Brief Introduction to PN Junction Physics
39(1)
Carrier Concentrations
40(2)
Fermi Energy Level
42(1)
2.4.2 Depletion Layer Capacitance
43(2)
2.4.3 Storage or Diffusion Capacitance
45(2)
2.4.4 SPICE Modeling
47(2)
2.5 The RC Delay through the N-well
49(3)
RC Circuit Review
50(1)
Distributed RC Delay
50(2)
Distributed RC Rise Time
52(1)
2.6 Twin Well Processes
52(7)
Design Rules for the Well
53(2)
SEM Views of Wells
55(4)
Chapter 3 The Metal Layers
59(24)
3.1 The Bonding Pad
59(4)
3.1.1 Laying Out the Pad I
60(1)
Capacitance of Metal-to-Substrate
60(2)
Passivation
62(1)
An Important Note
62(1)
3.2 Design and Layout Using the Metal Layers
63(8)
3.2.1 Metal1 and Via1
63(1)
An Example Layout
63(1)
3.2.2 Parasitics Associated with the Metal Layers
64(1)
Intrinsic Propagation Delay
65(3)
3.2.3 Current-Carrying Limitations
68(1)
3.2.4 Design Rules for the Metal Layers
69(1)
Layout of Two Shapes or a Single Shape
69(1)
A Layout Trick for the Metal Layers
69(1)
3.2.5 Contact Resistance
70(1)
3.3 Crosstalk and Ground Bounce
71(4)
3.3.1 Crosstalk
71(1)
3.3.2 Ground Bounce
72(1)
DC Problems
72(1)
AC Problems
72(2)
A Final Comment
74(1)
3.4 Layout Examples
75(8)
3.4.1 Laying Out the Pad II
75(3)
3.4.2 Laying Out Metal Test Structures
78(1)
SEM View of Metal
79(4)
Chapter 4 The Active and Poly Layers
83(22)
4.1 Layout Using the Active and Poly Layers
83(9)
The Active Layer
83(1)
The P- and N-Select Layers
84(2)
The Poly Layer
86(1)
Self-Aligned Gate
86(2)
The Poly Wire
88(1)
Silicide Block
89(1)
4.1.1 Process Flow
89(1)
Damascene Process Steps
90(2)
4.2 Connecting Wires to Poly and Active
92(8)
Connecting the P-Substrate to Ground
93(1)
Layout of an N-Well Resistor
94(1)
Layout of an NMOS Device
95(1)
Layout of a PMOS Device
96(1)
A Comment Concerning MOSFET Symbols
96(1)
Standard Cell Frame
97(1)
Design Rules
98(2)
4.3 Electrostatic Discharge (ESD) Protection
100(5)
Layout of the Diodes
100(5)
Chapter 5 Resistors, Capacitors, MOSFETs
105(26)
5.1 Resistors
105(8)
Temperature Coefficient (Temp Co)
105(1)
Polarity of the Temp Co
106(1)
Voltage Coefficient
107(2)
Using Unit Elements
109(1)
Guard Rings
110(1)
Interdigitated Layout
110(1)
Common-Centroid Layout
111(2)
Dummy Elements
113(1)
5.2 Capacitors
113(3)
Layout of the Poly-Poly Capacitor
114(1)
Parasitics
115(1)
Temperature Coefficient (Temp Co)
116(1)
Voltage Coefficient
116(1)
5.3 MOSFETs
116(9)
Lateral Diffusion
116(1)
Oxide Encroachment
116(1)
Source/Drain Depletion Capacitance
117(1)
Source/Drain Parasitic Resistance
118(2)
Layout of Long-Length MOSFETs
120(1)
Layout of Large-Width MOSFETs
121(2)
A Qualitative Description of MOSFET Capacitances
123(2)
5.4 Layout Examples
125(6)
Metal Capacitors
125(2)
Polysilicon Resistors
127(4)
Chapter 6 MOSFET Operation
131(30)
6.1 MOSFET Capacitance Overview/Review
132(3)
Case I Accumulation
132(1)
Case II Depletion
133(1)
Case III Strong Inversion
133(2)
Summary
135(1)
6.2 The Threshold Voltage
135(5)
Contact Potentials
137(3)
Threshold Voltage Adjust
140(1)
6.3 IV Characteristics of MOSFETs
140(5)
6.3.1 MOSFET Operation in the Triode Region
141(2)
6.3.2 The Saturation Region
143(2)
Cgs Calculation in the Saturation Region
145(1)
6.4 SPICE Modeling of the MOSFET
145(6)
Model Parameters Related to VTHN
146(1)
Long-Channel MOSFET Models
146(1)
Model Parameters Related to the Drain Current
146(1)
SPICE Modeling of the Source and Drain Implants
147(1)
Summary
147(1)
6.4.1 Some SPICE Simulation Examples
148(1)
Threshold Voltage and Body Effect
148(1)
6.4.2 The Subthreshold Current
149(2)
6.5 Short-Channel MOSFETs
151(10)
Hot Carriers
151(1)
Lightly Doped Drain (LDD)
151(1)
6.5.1 MOSFET Scaling
152(1)
6.5.2 Short-Channel Effects
153(1)
Negative Bias Temperature Instability (NBTI)
153(1)
Oxide Breakdown
154(1)
Drain-Induced Barrier Lowering
154(1)
Gate-Induced Drain Leakage
154(1)
Gate Tunnel Current
154(1)
6.5.3 SPICE Models for Our Short-Channel CMOS Process
154(1)
BSIM4 Model Listing (NMOS)
154(2)
BSIM4 Model Listing (PMOS)
156(1)
Simulation Results
157(4)
Chapter 7 CMOS Fabrication
161(52)
Jeff Jessing
7.1 CMOS Unit Processes
161(16)
7.1.1 Wafer Manufacture
161(1)
Metallurgical Grade Silicon (MGS)
162(1)
Electronic Grade Silicon (EGS)
162(1)
Czochralski (CZ) Growth and Wafer Formation
162(1)
7.1.2 Thermal Oxidation
163(2)
7.1.3 Doping Processes
165(1)
Ion Implantation
165(1)
Solid State Diffusion
166(1)
7.1.4 Photolithography
167(1)
Resolution
168(1)
Depth of Focus
168(2)
Aligning Masks
170(1)
7.1.5 Thin Film Removal
170(1)
Thin Film Etching
170(1)
Wet Etching
171(1)
Dry Etching
171(2)
Chemical Mechanical Polishing
173(1)
7.1.6 Thin Film Deposition
173(2)
Physical Vapor Deposition (PVD)
175(1)
Chemical Vapor Depositon (CVD)
176(1)
7.2 CMOS Process Integration
177(32)
FEOL
177(1)
BEOL
177(1)
CMOS Process Description
178(2)
7.2.1 Frontend-of-the-Line Integration
180(1)
Shallow Trench Isolation Module
181(6)
Twin Tub Module
187(3)
Gate Module
190(3)
Source/Drain Module
193(6)
7.2.2 Backend-of-the-Line Integration
199(1)
Self-Aligned Silicide (Salicide) Module
199(1)
Pre-Metal Dielectric
200(2)
Contact Module
202(1)
Metallization 1
203(2)
Intra-Metal Dielectric 1 Deposition
205(1)
Via 1 Module
205(2)
Metallization 2
207(1)
Additional Metal/Dieletric Layers
208(1)
Final Passivation
208(1)
7.3 Backend Processes
209(2)
Wafer Probe
209(2)
Die Separation
211(1)
Packaging
211(1)
Final Test and Burn-In
211(1)
7.4 Summary
211(2)
Chapter 8 Electrical Noise: An Overview
213(56)
8.1 Signals
213(6)
8.1.1 Power and Energy
213(2)
Comments
215(1)
8.1.2 Power Spectral Density
215(1)
Spectrum Analyzers
216(3)
8.2 Circuit Noise
219(35)
8.2.1 Calculating and Modeling Circuit Noise
219(1)
Input-Referred Noise I
220(1)
Noise Equivalent Bandwidth
220(3)
Input-Referred Noise in Cascaded Amplifiers
223(1)
Calculating Vonoise, RMS from a Spectrum: A Summary
224(1)
8.2.2 Thermal Noise
225(5)
8.2.3 Signal-to-Noise Ratio
230(1)
Input-Referred Noise II
231(2)
Noise Figure
233(1)
An Important Limitation of the Noise Figure
233(3)
Optimum Source Resistance
236(1)
Simulating Noiseless Resistors
236(3)
Noise Temperature
239(1)
Averaging White Noise
240(2)
8.2.4 Shot Noise
242(2)
8.2.5 Flicker Noise
244(8)
8.2.6 Other Noise Sources
252(1)
Random Telegraph Signal Noise
252(1)
Excess Noise (Flicker Noise)
253(1)
Avalanche Noise
253(1)
8.3 Discussion
254(15)
8.3.1 Correlation
254(2)
Correlation of Input-Referred Noise Sources
256(1)
Complex Input Impedance
256(3)
8.3.2 Noise and Feedback
259(1)
Op-Amp Noise Modeling
259(3)
8.3.3 Some Final Notes Concerning Notation
262(7)
Chapter 9 Models for Analog Design
269(42)
9.1 Long-Channel MOSFETs
269(28)
9.1.1 The Square-Law Equations
271(1)
PMOS Square-Law Equations
272(1)
Qualitative Discussion
272(4)
Threshold Voltage and Body Effect
276(1)
Qualitative Discussion
276(2)
The Triode Region
278(1)
The Cutoff and Subthreshold Regions
278(1)
9.1.2 Small Signal Models
279(1)
Transconductance
280(5)
AC Analysis
285(1)
Transient Analysis
286(1)
Body Effect Transconductance, gmb
287(1)
Output Resistance
288(2)
MOSFET Transition Frequency, fT
290(1)
General Device Sizes for Analog Design
291(1)
Subthreshold gm and VTHN
292(1)
9.1.3 Temperature Effects
293(1)
Threshold Variation and Temperature
293(2)
Mobility Variation with Temperature
295(1)
Drain Current Change with Temperature
295(2)
9.2 Short-Channel MOSFETs
297(5)
9.2.1 General Design (A Starting Point)
297(1)
Output Resistance
298(1)
Forward Transconductance
298(1)
Transition Frequency
299(1)
9.2.2 Specific Design (A Discussion)
300(2)
9.3 MOSFET Noise Modeling
302(9)
Drain Current Noise Model
302(9)
Chapter 10 Models for Digital Design
311(20)
Miller Capacitance
311(1)
10.1 The Digital MOSFET Model
312(9)
Effective Switching Resistance
312(2)
Short-Channel MOSFET Effective Switching Resistance
314(1)
10.1.1 Capacitive Effects
315(1)
10.1.2 Process Characteristic Time Constant
316(1)
10.1.3 Delay and Transition Times
317(3)
10.1.4 General Digital Design
320(1)
10.2 The MOSFET Pass Gate
321(5)
The PMOS Pass Gate
322(1)
10.2.1 Delay through a Pass Gate
323(1)
The Transmission Gate (The TG)
324(1)
10.2.2 Delay through Series-Connected PGs
325(1)
10.3 A Final Comment Concerning Measurements
326(5)
Chapter 11 The Inverter
331(22)
11.1 DC Characteristics
331(6)
Noise Margins
333(1)
Inverter Switching Point
334(1)
Ideal Inverter VTC and Noise Margins
334(3)
11.2 Switching Characteristics
337(4)
The Ring Oscillator
339(1)
Dynamic Power Dissipation
339(2)
11.3 Layout of the Inverter
341(3)
Latch-Up
341(3)
11.4 Sizing for Large Capacitive Loads
344(5)
Buffer Topology
344(3)
Distributed Drivers
347(1)
Driving Long Lines
348(1)
11.5 Other Inverter Configurations
349(4)
NMOS-Only Output Drivers
350(1)
Inverters with Tri-State Outputs
351(1)
Additional Examples
351(2)
Chapter 12 Static Logic Gates
353(22)
12.1 DC Characteristics of the NAND and NOR Gates
353(5)
12.1.1 DC Characteristics of the NAND Gate
353(3)
12.1.2 DC Characteristics of the NOR Gates
356(1)
A Practical Note Concerning Vsp and Pass Gates
357(1)
12.2 Layout of the NAND and NOR Gates
358(1)
12.3 Switching Characteristics
358(6)
Parallel Connection of MOSFETs
358(1)
Series Connection of MOSFETs
359(1)
12.3.1 NAND Gate
360(2)
Quick Estimate of Delays
362(1)
12.3.2 Number of Inputs
363(1)
12.4 Complex CMOS Logic Gates
364(11)
Cascode Voltage Switch Logic
369(1)
Differential Split-Level Logic
370(1)
Tri-State Outputs
370(1)
Additional Examples
370(5)
Chapter 13 Clocked Circuits
375(22)
13.1 The CMOS TG
375(3)
Series Connection of TGs
377(1)
13.2 Applications of the Transmission Gate
378(2)
Path Selector
378(1)
Static Circuits
379(1)
13.3 Latches and Flip-Flops
380(9)
Basic Latches
380(3)
An Arbiter
383(1)
Flip-Flops and Flow-through Latches
383(3)
An Edge-Triggered D-FF
386(2)
Flip-Flop Timing
388(1)
13.4 Examples
389(8)
Chapter 14 Dynamic Logic Gates
397(14)
14.1 Fundamentals of Dynamic Logic
397(6)
14.1.1 Charge Leakage
398(3)
14.1.2 Simulating Dynamic Circuits
401(1)
14.1.3 Nonoverlapping Clock Generation
401(1)
14.1.4 CMOS TG in Dynamic Circuits
402(1)
14.2 Clocked CMOS Logic
403(8)
Clocked CMOS Latch
403(1)
An Important Note
403(1)
PE Logic
404(1)
Domino Logic
405(2)
NP Logic (Zipper Logic)
407(1)
Pipelining
407(4)
Chapter 15 VLSI Layout Examples
411(22)
15.1 Chip Layout
412(10)
Regularity
412(1)
Standard Cell Examples
413(4)
Power and Ground Considerations
417(2)
An Adder Example
419(3)
A 4-to-1 MUX/DEMUX
422(1)
15.2 Layout Steps
422(11)
Dean Moriarty
Planning and Stick Diagrams
422(2)
Device Placement
424(3)
Polish
427(1)
Standard Cells Versus Full-Custom Layout
427(6)
Chapter 16 Memory Circuits
433(50)
16.1 Array Architectures
434(14)
16.1.1 Sensing Basics
435(1)
NMOS Sense Amplifier (NSA)
435(1)
The Open Array Architecture
436(4)
PMOS Sense Amplifier (PSA)
440(1)
Refresh Operation
441(1)
16.1.2 The Folded Array
441(2)
Layout of the DRAM Memory Bit (Mbit)
443(4)
16.1.3 Chip Organization
447(1)
16.2 Peripheral Circuits
448(15)
16.2.1 Sense Amplifier Design
448(1)
Kickback Noise and Clock Feedthrough
449(1)
Memory
450(1)
Current Draw
450(1)
Contention Current (Switching Current)
450(1)
Removing Sense Amplifier Memory
451(1)
Creating an Imbalance and Reducing Kickback Noise
451(3)
Increasing the Input Range
454(1)
Simulation Examples
454(3)
16.2.2 Row/Column Decoders
457(1)
Global and Local Decoders
458(2)
Reducing Decoder Layout Area
460(1)
16.2.3 Row Drivers
461(2)
16.3 Memory Cells
463(20)
16.3.1 The SRAM Cell
463(1)
16.3.2 Read-Only Memory (ROM)
464(2)
16.3.3 Floating Gate Memory
466(1)
The Threshold Voltage
467(1)
Erasable Programmable Read-Only Memory
468(1)
Two Important Notes
468(1)
Flash Memory
469(14)
Chapter 17 Sensing Using ΔΣ Modulation
483(40)
17.1 Qualitative Discussion
484(13)
17.1.1 Examples of DSM
484(1)
The Counter
485(1)
Cup Size
486(1)
Another Example
486(1)
17.1.2 Using DSM for Sensing in Flash Memory
487(1)
The Basic Idea
487(5)
The Feedback Signal
492(4)
Incomplete Settling
496(1)
17.2 Sensing Resistive Memory
497(7)
The Bit Line Voltage
497(1)
Adding an Offset to the Comparator
498(1)
Schematic and Design Values
499(3)
A Couple of Comments
502(2)
17.3 Sensing in CMOS Imagers
504(19)
Resetting the Pixel
504(1)
The Intensity Level
504(1)
Sampling the Reference and Intensity Signals
505(1)
Noise Issues
506(2)
Subtracting VR from Vs
508(9)
Sensing Circuit Mismatches
517(6)
Chapter 18 Special Purpose CMOS Circuits
523(28)
18.1 The Schmitt Trigger
523(6)
18.1.1 Design of the Schmitt Trigger
524(2)
Switching Characteristics
526(1)
18.1.2 Applications of the Schmitt Trigger
527(2)
18.2 Multivibrator Circuits
529(2)
18.2.1 The Monostable Multivibrator
529(1)
18.2.2 The Astable Multivibrator
530(1)
18.3 Input Buffers
531(11)
18.3.1 Basic Circuits
531(2)
Skew in Logic Gates
533(1)
18.3.2 Differential Circuits
534(1)
Transient Response
535(3)
18.3.3 DC Reference
538(3)
18.3.4 Reducing Buffer Input Resistance
541(1)
18.4 Charge Pumps (Voltage Generators)
542(9)
Negative Voltages
543(1)
Using MOSFETs for the Capacitors
544(1)
18.4.1 Increasing the Output Voltage
544(1)
18.4.2 Generating Higher Voltages: The Dickson Charge Pump
544(2)
Clock Driver with a Pumped Output Voltage
546(1)
NMOS Clock Driver
546(1)
18.4.3 Example
547(4)
Chapter 19 Digital Phase-Locked Loops
551(62)
19.1 The Phase Detector
553(8)
19.1.1 The XOR Phase Detector
553(4)
19.1.2 The Phase Frequency Detector
557(4)
19.2 The Voltage-Controlled Oscillator
561(6)
19.2.1 The Current-Starved VCO
561(3)
Linearizing the VCO's Gain
564(1)
19.2.2 Source-Coupled VCOs
565(2)
19.3 The Loop Filter
567(15)
19.3.1 XOR DPLL
568(5)
Active-PI Loop Filter
573(2)
19.3.2 PFD DPLL
575(1)
Tri-State Output
575(1)
Implementing the PFD in CMOS
576(2)
PFD with a Charge Pump Output
578(1)
Practical Implementation of the Charge Pump
579(2)
Discussion
581(1)
19.4 System Concerns
582(10)
19.4.1 Clock Recovery from NRZ Data
584(4)
The Hogge Phase Detector
588(1)
Jitter
588(4)
19.5 Delay-Locked Loops
592(4)
Delay Elements
595(1)
Practical VCO and VCDL Design
596(1)
19.6 Some Examples
596(17)
19.6.1 A 2 GHz DLL
596(6)
19.6.2 A 1 Gbit/s Clock-Recovery Circuit
602(11)
Chapter 20 Current Mirrors
613(44)
20.1 The Basic Current Mirror
613(23)
20.1.1 Long-Channel Design
614(2)
20.1.2 Matching Currents in the Mirror
616(1)
Threshold Voltage Mismatch
616(1)
Transconductance Parameter Mismatch
616(1)
Drain-to-Source Voltage and Lambda
617(1)
Layout Techniques to Improve Matching
617(3)
Layout of the Mirror with Different Widths
620(1)
20.1.3 Biasing the Current Mirror
621(1)
Using a MOSFET-Only Reference Circuit
622(2)
Supply Independent Biasing
624(3)
20.1.4 Short-Channel Design
627(3)
An Important Note
630(1)
20.1.5 Temperature Behavior
631(1)
Resistor-MOSFET Reference Circuit
631(2)
MOSFET-Only Reference Circuit
633(1)
Temperature Behavior of the Beta-Multiplier
634(1)
Voltage Reference Using the Beta-Multiplier
634(1)
20.1.6 Biasing in the Subthreshold Region
635(1)
20.2 Cascoding the Current Mirror
636(11)
20.2.1 The Simple Cascode
636(1)
DC Operation
637(1)
Cascode Output Resistance
637(2)
20.2.2 Low-Voltage (Wide-Swing) Cascode
639(2)
An Important Practical Note
641(1)
Layout Concerns
642(1)
20.2.3 Wide-Swing, Short-Channel Design
642(3)
20.2.4 Regulated Drain Current Mirror
645(2)
20.3 Biasing Circuits
647(10)
20.3.1 Long-Channel Biasing Circuits
647(1)
Basic Cascode Biasing
648(1)
The Folded-Cascode Structure
648(2)
20.3.2 Short-Channel Biasing Circuits
650(1)
Floating Current Sources
651(1)
20.3.3 A Final Comment
651(6)
Chapter 21 Amplifiers
657(54)
21.1 Gate-Drain Connected Loads
657(14)
21.1.1 Common-Source (CS) Amplifiers
657(3)
Miller's Theorem
660(1)
Frequency Response
661(1)
The Right-Hand Plane Zero
662(4)
A Common-Source Current Amplifier
666(1)
Common-Source Amplifier with Source Degeneration
667(2)
Noise Performance of the CS Amplifier with Gate-Drain Load
669(1)
21.1.2 The Source Follower (Common-Drain Amplifier)
670(1)
21.1.3 Common Gate Amplifier
671(1)
21.2 Current Source Loads
671(27)
21.2.1 Common-Source Amplifier
671(1)
Class A Operation
672(1)
Small-Signal Gain
673(1)
Open Circuit Gain
673(1)
High-Impedance and Low-Impedance Nodes
673(1)
Frequency Response
674(2)
Pole Splitting
676(3)
Pole Splitting Summary
679(6)
Canceling the RHP Zero
685(1)
Noise Performance of the CS Amplifier with Current Source Load
686(1)
21.2.2 The Cascode Amplifier
686(1)
Frequency Response
687(1)
Class A Operation
688(1)
Noise Performance of the Cascode Amplifier
688(1)
Operation as a Transimpedance Amplifier
688(1)
21.2.3 The Common-Gate Amplifier
689(1)
21.2.4 The Source Follower (Common-Drain Amplifier)
690(1)
Body Effect and Gain
691(1)
Level Shifting
692(1)
Input Capacitance
693(1)
Noise Performance of the SF Amplifier
694(1)
Frequency Behavior
694(2)
SF as an Output Buffer
696(1)
A Class AB Output Buffer Using SFs
697(1)
21.3 The Push-Pull Amplifier
698(13)
21.3.1 DC Operation and Biasing
699(1)
Power Conversion Efficiency
699(3)
21.3.2 Small-Signal Analysis
702(2)
21.3.3 Distortion
704(1)
Modeling Distortion with SPICE
705(6)
Chapter 22 Differential Amplifiers
711(34)
22.1 The Source-Coupled Pair
711(16)
22.1.1 DC Operation
711(1)
Maximum and Minimum Differential Input Voltage
712(1)
Maximum and Minimum Common-Mode Input Voltage
713(2)
Current Mirror Load
715(2)
Biasing from the Current Mirror Load
717(1)
Minimum Power Supply Voltage
717(1)
22.1.2 AC Operation
718(1)
AC Gain with a Current Mirror Load
719(2)
22.1.3 Common-Mode Rejection Ratio
721(2)
Input-Referred Offset from Finite CMRR
723(1)
22.1.4 Matching Considerations
724(1)
Input-Referred Offset with a Current Mirror Load
725(1)
22.1.5 Noise Performance
726(1)
22.1.6 Slew-Rate Limitations
727(1)
22.2 The Source Cross-Coupled Pair
727(6)
Operation of the Diff-Amp
728(1)
Input Signal Range
729(2)
22.2.1 Current Source Load
731(1)
Input Signal Range
732(1)
22.3 Cascode Loads (The Telescopic Diff-Amp)
733(3)
22.4 Wide-Swing Differential Amplifiers
736(9)
22.4.1 Current Differential Amplifier
737(1)
22.4.2 Constant Transconductance Diff-Amp
738(2)
Discussion
740(5)
Chapter 23 Voltage References
745(28)
23.1 MOSFET-Resistor Voltage References
746(11)
23.1.1 The Resistor-MOSFET Divider
746(3)
23.1.2 The MOSFET-Only Voltage Divider
749(1)
23.1.3 Self-Biased Voltage References
750(1)
Forcing the Same Current through Each Side of the Reference
751(5)
An Alternate Topology
756(1)
23.2 Parasitic Diode-Based References
757(16)
Diode Behavior
758(1)
The Bandgap Energy of Silicon
759(1)
Lower Voltage Reference Design
760(1)
23.2.1 Long-Channel BGR Design
761(1)
Diode-Referenced Self-Biasing (CTAT)
761(1)
Thermal Voltage-Referenced Self-Biasing (PTAT)
762(3)
Bandgap Reference Design
765(1)
Alternative BGR Topologies
766(2)
23.2.2 Short-Channel BGR Design
768(2)
The Added Amplifier
770(1)
Lower Voltage Operation
770(3)
Chapter 24 Operational Amplifiers I
773(56)
24.1 The Two-Stage Op-Amp
774(19)
Low-Frequency, Open Loop Gain, AOLDC
774(1)
Input Common-Mode Range
774(1)
Power Dissipation
775(1)
Output Swing and Current Source/Sinking Capability
775(1)
Offsets
775(1)
Compensating the Op-Amp
776(5)
Gain and Phase Margins
781(1)
Removing the Zero
782(1)
Compensation for High-Speed Operation
783(4)
Slew-Rate Limitations
787(2)
Common-Mode Rejection Ratio (CMRR)
789(1)
Power Supply Rejection Ratio (PSRR)
790(1)
Increasing the Input Common-Mode Voltage Range
791(1)
Estimating Bandwidth in Op-Amps Circuits
792(1)
24.2 An Op-Amp with Output Buffer
793(3)
Compensating the Op-Amp
794(2)
24.3 The Operational Transconductance Amplifier (OTA)
796(12)
Unity-Gain Frequency, fun
797(1)
Increasing the OTA Output Resistance
798(1)
An Important Note
799(1)
OTA with an Output Buffer (An Op-Amp)
800(3)
The Folded-Cascode OTA and Op-Amp
803(5)
24.4 Gain-Enhancement
808(4)
Bandwidth of the Added GE Amplifiers
809(2)
Compensating the Added GE Amplifiers
811(1)
24.5 Some Examples and Discussions
812(17)
A Voltage Regulator
812(5)
Bad Output Stage Design
817(3)
Three-Stage Op-Amp Design
820(9)
Chapter 25 Dynamic Analog Circuits
829(34)
25.1 The MOSFET Switch
829(7)
Charge Injection
830(1)
Capacitive Feedthrough
831(1)
Reduction of Charge Injection and Clock Feedthrough
832(1)
kT/C Noise
833(1)
25.1.1 Sample-and-Hold Circuits
834(2)
25.2 Fully-Differential Circuits
836(7)
Gain
836(1)
Common-Mode Feedback
837(1)
Coupled Noise Rejection
838(1)
Other Benefits of Fully-Differential Op-Amps
838(1)
25.2.1 A Fully-Differential Sample-and-Hold
838(2)
Connecting the Inputs to the Bottom (Poly1) Plate
840(1)
Bottom Plate Sampling
841(1)
SPICE Simulation
841(2)
25.3 Switched-Capacitor Circuits
843(10)
25.3.1 Switched-Capacitor Integrator
845(1)
Parasitic Insensitive
846(1)
Other Integrator Configurations
846(3)
Exact Frequency Response of a Switched-Capacitor Integrator
849(2)
Capacitor Layout
851(1)
Op-Amp Settling Time
852(1)
25.4 Circuits
853(10)
Reducing Offset Voltage of an Op-Amp
853(1)
Dynamic Comparator
854(2)
Dynamic Current Mirrors
856(2)
Dynamic Amplifiers
858(5)
Chapter 26 Operational Amplifiers II
863(46)
26.1 Biasing for Power and Speed
863(4)
26.1.1 Device Characteristics
864(1)
26.1.2 Biasing Circuit
865(1)
Layout of Differential Op-Amps
865(1)
Self-Biased Reference
866(1)
26.2 Basic Concepts
867(9)
Modeling Offset
867(1)
A Diff-Amp
867(1)
A Single Bias Input Diff-Amp
868(1)
The Diff-Amp's Tail Current Source
868(1)
Using a CMFB Amplifier
869(2)
Compensating the CMFB Loop
871(2)
Extending the CMFB Amplifier Input Range
873(1)
Dynamic CMFB
874(2)
26.3 Basic Op-Amp Design
876(20)
The Differential Amplifier
877(1)
Adding a Second Stage (Making an Op-Amp)
878(2)
Step Response
880(1)
Adding CMFB
881(1)
CMFB Amplifier
882(1)
The Two-Stage Op-Amp with CMFB
883(1)
Origin of the Problem
884(2)
Simulation Results
886(1)
Using MOSFETs Operating in the Triode Region
887(1)
Start-up Problems
887(1)
Lowering Input Capacitance
887(1)
Making the Op-Amp More Practical
888(1)
Increasing the Op-Amp's Open-Loop Gain
889(3)
Offsets
892(1)
Op-Amp Offset Effects on Outputs
893(1)
Single-Ended to Differential Conversion
894(1)
CMFB Settling Time
895(1)
CMFB in the Output Buffer (Fig. 26.43) or the Diff-Amp (Fig. 26.40)?
895(1)
26.4 Op-Amp Design Using Switched-Capacitor CMFB
896(13)
Clock Signals
896(1)
Switched-Capacitor CMFB
896(2)
The Op-Amp's First Stage
898(2)
The Output Buffer
900(1)
An Application of the Op-Amp
901(1)
Simulation Results
902(2)
A Final Note Concerning Biasing
904(5)
Chapter 27 Nonlinear Analog Circuits
909(22)
27.1 Basic CMOS Comparator Design
909(11)
Preamplification
910(1)
Decision Circuit
910(3)
Output Buffer
913(2)
27.1.1 Characterizing the Comparator
915(1)
Comparator DC Performance
915(1)
Transient Response
916(2)
Propagation Delay
918(1)
Minimum Input Slew Rate
918(1)
27.1.2 Clocked Comparators
918(2)
27.1.3 Input Buffers Revisited
920(1)
27.2 Adaptive Biasing
920(3)
27.3 Analog Multipliers
923(8)
27.3.1 The Multiplying Quad
924(2)
Simulating the Operation of the Multiplier
926(2)
27.3.2 Multiplier Design Using Squaring Circuits
928(3)
Chapter 28 Data Converter Fundamentals
931(34)
Harry Li
28.1 Analog Versus Discrete Time Signals
931(1)
28.2 Converting Analog Signals to Digital Signals
932(3)
28.3 Sample-and-Hold (S/H) Characteristics
935(3)
Sample Mode
936(1)
Hold Mode
937(1)
Aperture Error
937(1)
28.4 Digital-to-Analog Converter (DAC) Specifications
938(9)
Differential Nonlinearity
941(2)
Integral Nonlinearity
943(2)
Offset
945(1)
Gain Error
945(1)
Latency
945(1)
Signal-to-Noise Ratio (SNR)
945(2)
Dynamic Range
947(1)
28.5 Analog-to-Digital Converter (ADC) Specifications
947(10)
Quantization Error
948(2)
Differential Nonlinearity
950(1)
Missing Codes
951(1)
Integral Nonlinearity
951(2)
Offset and Gain Error
953(1)
Aliasing
953(3)
Signal-to-Noise Ratio
956(1)
Aperture Error
956(1)
28.6 Mixed-Signal Layout Issues
957(8)
Floorplanning
958(1)
Power Supply and Ground Issues
958(2)
Fully Differential Design
960(1)
Guard Rings
960(1)
Shielding
961(1)
Other Interconnect Considerations
962(3)
Chapter 29 Data Converter Architectures
965(58)
Harry Li
29.1 DAC Architectures
965(20)
29.1.1 Digital Input Code
965(1)
29.1.2 Resistor String
966(1)
Mismatch Errors Related to the Resistor-String DAC
967(2)
Integral Nonlinearity of the Resistor-String DAC
969(1)
Differential Nonlinearity of the Worst-Case Resistor-String DAC
970(1)
29.1.3 R-2R Ladder Networks
971(2)
29.1.4 Current Steering
973(3)
Mismatch Errors Related to Current-Steering DACs
976(2)
29.1.5 Charge-Scaling DACs
978(2)
Layout Considerations for a Binary-Weighted Capacitor Array
980(1)
The Split Array
980(2)
29.1.6 Cyclic DAC
982(2)
29.1.7 Pipeline DAC
984(1)
29.2 ADC Architectures
985(38)
29.2.1 Flash
985(3)
Accuracy Issues for the Flash ADC
988(2)
29.2.2 The Two-Step Flash ADC
990(2)
Accuracy Issues Related to the Two-Step Flash Converter
992(1)
Accuracy Issues Related to Operational Amplifiers
992(2)
29.2.3 The Pipeline ADC
994(2)
Accuracy Issues Related to the Pipeline Converter
996(2)
29.2.4 Integrating ADCs
998(1)
Single-Slope Architecture
998(2)
Accuracy Issues Related to the Single-Slope ADC
1000(1)
Dual-Slope Architecture
1000(2)
Accuracy Issues Related to the Dual-Slope ADC
1002(1)
29.2.5 The Successive Approximation ADC
1003(2)
The Charge-Redistribution Successive Approximation ADC
1005(2)
29.2.6 The Oversampling ADC
1007(1)
Differences in Nyquist Rate and Oversampled ADCs
1007(1)
The First-Order ΔΣ Modulator
1008(2)
The Higher Order ΔΣ Modulators
1010(13)
Chapter 30 Implementing Data Converters
1023(76)
30.1 R-2R Topologies for DACs
1024(21)
30.1.1 The Current-Mode R-2R DAC
1024(1)
30.1.2 The Voltage-Mode R-2R DAC
1025(1)
30.1.3 A Wide-Swing Current-Mode R-2R DAC
1026(3)
DNL Analysis
1029(1)
INL Analysis
1029(1)
Switches
1030(1)
Experimental Results
1030(2)
Improving DNL (Segmentation)
1032(2)
Trimming DAC Offset
1034(2)
Trimming DAC Gain
1036(1)
Improving INL by Calibration
1037(1)
30.1.4 Topologies Without an Op-Amp
1038(1)
The Voltage-Mode DAC
1038(3)
Two Important Notes Concerning Glitches
1041(1)
The Current-Mode (Current Steering) DAC
1042(3)
30.2 Op-Amps in Data Converters
1045(7)
Gain Bandwidth Product of the Noninverting Op-Amp Topology
1045(1)
Gain Bandwidth Product of the Inverting Op-Amp Topology
1046(1)
30.2.1 Op-Amp Gain
1047(1)
30.2.2 Op-Amp Unity Gain Frequency
1048(1)
30.2.3 Op-Amp Offset
1049(1)
Adding an Auxiliary Input Port
1049(3)
30.3 Implementing ADCs
1052(47)
30.3.1 Implementing the S/H
1052(2)
A Single-Ended to Differential Output S/H
1054(5)
30.3.2 The Cyclic ADC
1059(2)
Comparator Placement
1061(1)
Implementing Subtraction in the S/H
1062(3)
Understanding Output Swing
1065(2)
30.3.3 The Pipeline ADC
1067(1)
Using 1.5 Bits/Stage
1068(7)
Capacitor Error Averaging
1075(7)
Comparator Placement
1082(1)
Clock Generation
1082(2)
Offsets and Alternative Design Topologies
1084(5)
Dynamic CMFB
1089(1)
Layout of Pipelined ADCs
1090(9)
Chapter 31 Feedback Amplifiers
1099(58)
Harry Li
31.1 The Feedback Equation
1100(1)
31.2 Properties of Negative Feedback on Amplifier Design
1101(4)
31.2.1 Gain Desensitivity
1101(1)
31.2.2 Bandwidth Extension
1101(2)
31.2.3 Reduction in Nonlinear Distortion
1103(1)
31.2.4 Input and Output Impedance Control
1104(1)
31.3 Recognizing Feedback Topologies
1105(8)
31.3.1 Input Mixing
1106(1)
31.3.2 Output Sampling
1106(1)
31.3.3 The Feedback Network
1107(1)
An Important Assumption
1107(1)
Counting Inversions Around the Loop
1108(1)
Examples of Recognizing Feedback Topologies
1109(1)
31.3.4 Calculating Open-Loop Parameters
1110(2)
31.3.5 Calculating Closed-Loop Parameters
1112(1)
31.4 The Voltage Amp (Series-Shunt Feedback)
1113(6)
31.5 The Transimpedance Amp (Shunt-Shunt Feedback)
1119(9)
31.5.1 Simple Feedback Using a Gate-Drain Resistor
1125(3)
31.6 The Transconductance Amp (Series-Series Feedback)
1128(4)
31.7 The Current Amplifier (Shunt-Series Feedback)
1132(3)
31.8 Stability
1135(6)
31.8.1 The Return Ratio
1139(2)
31.9 Design Examples
1141(16)
31.9.1 Voltage Amplifiers
1141(2)
Amplifiers with Gain
1143(2)
31.9.2 A Transimpedance Amplifier
1145(12)
Index 1157(17)
About the Author 1174
R. JACOB (JAKE) BAKER, PhD, is an engineer, educator, and inventor. He has more than twenty years of engineering experience and holds more than 200 granted or pending patents in integrated circuit design. Jake is the author of several circuit design books for Wiley-IEEE Press. In 2007, he received the Hewlett-Packard Frederick Emmons Terman Award, which is presented annually to an outstanding young electrical engineering educator by the Electrical and Computer Engineering Division of the American Society for Engineering Education.