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CMOS: Circuit Design, Layout, and Simulation 4th edition [Kõva köide]

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(Boise State University, Micron Technology, Inc., Boise, Idaho)
  • Formaat: Hardback, 1280 pages, kõrgus x laius x paksus: 277x221x53 mm, kaal: 2744 g
  • Sari: IEEE Press Series on Microelectronic Systems
  • Ilmumisaeg: 06-Aug-2019
  • Kirjastus: Wiley-IEEE Press
  • ISBN-10: 1119481511
  • ISBN-13: 9781119481515
Teised raamatud teemal:
CMOS: Circuit Design, Layout, and Simulation 4th editionSuurem pilt
  • Formaat: Hardback, 1280 pages, kõrgus x laius x paksus: 277x221x53 mm, kaal: 2744 g
  • Sari: IEEE Press Series on Microelectronic Systems
  • Ilmumisaeg: 06-Aug-2019
  • Kirjastus: Wiley-IEEE Press
  • ISBN-10: 1119481511
  • ISBN-13: 9781119481515
Teised raamatud teemal:
Püsilink: https://www.kriso.ee/db/9781119481515.html
Märksõnad:

A revised guide to the theory and implementation of CMOS analog and digital IC design

The fourth edition of CMOS: Circuit Design, Layout, and Simulation is an updated guide to the practical design of both analog and digital integrated circuits. The author—a noted expert on the topic—offers a contemporary review of a wide range of analog/digital circuit blocks including: phase-locked-loops, delta-sigma sensing circuits, voltage/current references, op-amps, the design of data converters, and switching power supplies.

CMOS includes discussions that detail the trade-offs and considerations when designing at the transistor-level. The companion website contains numerous examples for many computer-aided design (CAD) tools. Using the website enables readers to recreate, modify, or simulate the design examples presented throughout the book. In addition, the author includes hundreds of end-of-chapter problems to enhance understanding of the content presented. This newly revised edition:

•    Provides in-depth coverage of both analog and digital transistor-level design techniques

•    Discusses the design of phase- and delay-locked loops, mixed-signal circuits, data converters, and circuit noise

•    Explores real-world process parameters, design rules, and layout examples

•    Contains a new chapter on Power Electronics

Written for students in electrical and computer engineering and professionals in the field, the fourth edition of CMOS: Circuit Design, Layout, and Simulation is a practical guide to understanding analog and digital transistor-level design theory and techniques.

Preface xxxiii
Chapter 1 Introduction to CMOS Design 1(30)
1.1 The CMOS IC Design Process
1(4)
1.1.1 Fabrication
2(30)
Layout and Cross-Sectional Views
5(1)
1.2 CMOS Background
5(3)
The CMOS Acronym
6(1)
CMOS Inverter
6(1)
The First CMOS Circuits
7(1)
Analog Design in CMOS
7(1)
1.3 An Introduction to SPICE
8(23)
Generating a Netlist File
8(1)
Operating Point
8(2)
Transfer Function Analysis
10(1)
The Voltage-Controlled Voltage Source
10(1)
An Ideal Op-Amp
11(1)
The Subcircuit
12(1)
DC Analysis
13(1)
Plotting IV Curves
13(1)
Dual Loop DC Analysis
14(1)
Transient Analysis
14(1)
The SIN Source
15(1)
An RC Circuit Example
16(1)
Another RC Circuit Example
17(1)
AC Analysis
18(1)
Decades and Octaves
19(1)
Decibels
19(1)
Pulse Statement
20(1)
Finite Pulse Rise time
20(1)
Step Response
21(1)
Delay and Rise time in RC Circuits
21(1)
Piece-Wise Linear (PWL) Source
22(1)
Simulating Switches
22(1)
Initial Conditions on a Capacitor
23(1)
Initial Conditions in an Inductor
23(1)
Q of an LC Tank
24(1)
Frequency Response of an Ideal Integrator
24(2)
Unity-Gain Frequency
26(1)
Time-Domain Behavior of the Integrator
26(1)
Convergence
26(1)
Some Common Mistakes and Helpful Techniques
27(4)
Chapter 2 The Well 31(28)
The Substrate (The Unprocessed Wafer)
31(1)
A Parasitic Diode
31(1)
Using the N-well as a Resistor
32(1)
2.1 Patterning
32(3)
2.1.1 Patterning the N-well
35(1)
2.2 Laying Out the N-well
35(1)
2.2.1 Design Rules for the N-well
36(1)
2.3 Resistance Calculation
36(3)
Layout of Corners
38(1)
2.3.1 The N-well Resistor
38(1)
2.4 The N-well/Substrate Diode
39(9)
2.4.1 A Brief Introduction to PN Junction Physics
39(3)
Carrier Concentrations
40(1)
Fermi Energy Level
41(1)
2.4.2 Depletion Layer Capacitance
42(3)
2.4.3 Storage or Diffusion Capacitance
45(1)
2.4.4 SPICE Modeling
46(2)
2.5 The RC Delay through the N-well
48(3)
RC Circuit Review
48(2)
Distributed RC Delay
50(1)
Distributed RC Rise Time
51(1)
2.6 Twin Well Processes
51(8)
Design Rules for the Well
52(2)
SEM Views of Wells
54(5)
Chapter 3 The Metal Layers 59(24)
3.1 The Bonding Pad
59(4)
3.1.1 Laying Out the Pad I
60(3)
Capacitance of Metal-to-Substrate
60(2)
Passivation
62(1)
An Important Note
62(1)
3.2 Design and Layout Using the Metal Layers
63(7)
3.2.1 Metall and Vial
63(1)
An Example Layout
63(1)
3.2.2 Parasitics Associated with the Metal Layers
63(4)
Intrinsic Propagation Delay
65(2)
3.2.3 Current-Carrying Limitations
67(1)
3.2.4 Design Rules for the Metal Layers
68(1)
Layout of Two Shapes or a Single Shape
68(1)
A Layout Trick for the Metal Layers
68(1)
3.2.5 Contact Resistance
69(1)
3.3 Crosstalk and Ground Bounce
70(4)
3.3.1 Crosstalk
71(1)
3.3.2 Ground Bounce
72(2)
DC Problems
72(1)
AC Problems
72(2)
A Final Comment
74(1)
3.4 Layout Examples
74(9)
3.4.1 Laying Out the Pad II
74(2)
3.4.2 Laying Out Metal Test Structures
76(7)
SEM View of Metal
79(4)
Chapter 4 The Active and Poly Layers 83(24)
4.1 Layout Using the Active and Poly Layers
83(10)
The Active Layer
83(1)
The P- and N-Select Layers
84(2)
The Poly Layer
86(1)
Self-Aligned Gate
86(2)
The FinFET
88(1)
The Poly Wire
89(1)
Silicide Block
90(1)
4.1.1 Process Flow
90(54)
Damascene Process Steps
91(2)
4.2 Connecting Wires to Poly and Active
93(6)
Connecting the P-Substrate to Ground
94(1)
Layout of an N-Well Resistor
94(1)
Layout of an NMOS Device
95(1)
Layout of a PMOS Device
96(1)
A Comment Concerning MOSFET Symbols
97(1)
Standard Cell Frame
97(1)
Design Rules
98(1)
4.3 Electrostatic Discharge (ESD) Protection
99(8)
Layout of the Diodes
101(6)
Chapter 5 Resistors, Capacitors, MOSFETs 107(28)
5.1 Resistors
107(8)
Temperature Coefficient (Temp Co)
107(1)
Polarity of the Temp Co
108(1)
Voltage Coefficient
109(1)
Using Unit Elements
110(1)
Guard Rings
111(1)
Interdigitated Layout
112(1)
Common-Centroid Layout
112(2)
Dummy Elements
114(1)
5.2 Capacitors
115(3)
Layout of the Poly-Poly Capacitor
115(2)
Parasitics
117(1)
Temperature Coefficient (Temp Co)
117(1)
Voltage Coefficient
117(1)
5.3 MOSFETs
118(7)
Lateral Diffusion
118(1)
Oxide Encroachment
119(1)
Source/Drain Depletion Capacitance
119(1)
Source/Drain Parasitic Resistance
119(2)
Layout of Long-Length MOSFETs
121(1)
Layout of Large-Width MOSFETs
122(1)
A Qualitative Description of MOSFET Capacitances
123(2)
5.4 Layout Examples
125(10)
Metal Capacitors
126(2)
Polysilicon Resistors
128(7)
Chapter 6 MOSFET Operation 135(30)
6.1 MOSFET Capacitance Overview/Review
136(3)
Case I: Accumulation
136(1)
Case II: Depletion
137(1)
Case Ill: Strong Inversion
137(2)
Summary
139(1)
6.2 The Threshold Voltage
139(5)
Contact Potentials
141(2)
Threshold Voltage Adjust
143(1)
6.3 IV Characteristics of MOSFETs
144(5)
6.3.1 MOSFET Operation in the Triode Region
144(2)
6.3.2 The Saturation Region
146(3)
Cgs Calculation in the Saturation Region
148(1)
6.4 SPICE Modeling of the MOSFET
149(5)
Model Parameters Related to VTHN
149(1)
Long-Channel MOSFET Models
149(1)
Model Parameters Related to the Drain Current
150(1)
SPICE Modeling of the Source and Drain Implants
150(1)
Summary
151(1)
6.4.1 Some SPICE Simulation Examples
151(1)
Threshold Voltage and Body Effect
151(1)
6.4.2 The Subthreshold Current
152(2)
6.5 Short-Channel MOSFETs
154(11)
Hot Carriers
154(1)
Lightly Doped Drain (LDD)
155(1)
6.5.1 MOSFET Scaling
155(1)
6.5.2 Short-Channel Effects
156(1)
Negative Bias Temperature Instability (NBTI)
156(1)
Oxide Breakdown
157(1)
Drain-Induced Barrier Lowering
157(1)
Gate-Induced Drain Leakage
157(1)
Gate Tunnel Current
157(1)
6.5.3 SPICE Models for Our Short-Channel CMOS Process
157(8)
BSIM4 Model Listing (NMOS)
157(2)
BSIM4 Model Listing (PMOS)
159(1)
Simulation Results
160(5)
Chapter 7 CMOS Fabrication 165(56)
Jeff Jessing
7.1 CMOS Unit Processes
165(15)
7.1.1 Wafer Manufacture
165(2)
Metallurgical Grade Silicon (MGS)
166(1)
Electronic Grade Silicon (EGS)
166(1)
Czochralski (CZ) Growth and Wafer Formation
166(1)
7.1.2 Thermal Oxidation
167(1)
7.1.3 Doping Processes
168(2)
Ion Implantation
169(1)
Solid State Diffusion
170(1)
7.1.4 Photolithography
170(3)
Resolution
172(1)
Depth of Focus
173(1)
Aligning Masks
173(1)
7.1.5 Thin Film Removal
173(4)
Thin Film Etching
174(1)
Wet Etching
174(1)
Dry Etching
175(1)
Chemical Mechanical Polishing
176(1)
7.1.6 Thin Film Deposition
177(3)
Physical Vapor Deposition (PVD)
178(1)
Chemical Vapor Depositon (CVD)
179(1)
7.2 CMOS Process Integration
180(30)
FEOL
181(1)
BEOL
181(1)
CMOS Process Description
181(1)
7.2.1 Frontend-of-the-Line Integration
182(14)
Starting Material
182(2)
Shallow Trench Isolation Module
184(4)
Twin Tub Module
188(4)
Gate Module
192(2)
Source/Drain Module
194(2)
7.2.2 Backend-of-the-Line Integration
196(16)
Self-Aligned Silicide (Salicide) Module
197(2)
Pre-Metal Dielectric
199(1)
Contact Module
200(2)
Metallization 1
202(2)
Intra-Metal Dielectric 1 Deposition
204(1)
Via 1 Module
205(1)
Metallization 2
205(1)
Additional Metal/Dieletric Layers
206(3)
Final Passivation
209(1)
7.3 Backend Processes
210(2)
Wafer Probe
210(2)
Die Separation
212(1)
Packaging
212(1)
Final Test and Burn-In
212(1)
7.4 Advanced CMOS Process Integration
212(7)
7.4.1 FinFETs
213(3)
7.4.2 Dual Damascene Low-k/Cu Interconnects
216(3)
7.5 Summary
219(2)
Chapter 8 Electrical Noise: An Overview 221(56)
8.1 Signals
221(5)
8.1.1 Power and Energy
221(2)
Comments
223(1)
8.1.2 Power Spectral Density
223(3)
Spectrum Analyzers
223(3)
8.2 Circuit Noise
226(34)
8.2.1 Calculating and Modeling Circuit Noise
227(4)
Input-Referred Noise I
227(1)
Noise Equivalent Bandwidth
228(2)
Input-Referred Noise in Cascaded Amplifiers
230(1)
Calculating Vonoise,RMS from a Spectrum: A Summary
231(1)
8.2.2 Thermal Noise
231(6)
8.2.3 Signal-to-Noise Ratio
237(10)
Input-Referred Noise II
238(2)
Noise Figure
240(1)
An Important Limitation of the Noise Figure
240(3)
Optimum Source Resistance
243(1)
Simulating Noiseless Resistors
243(2)
Noise Temperature
245(1)
Averaging White Noise
246(1)
8.2.4 Shot Noise
247(4)
8.2.5 Flicker Noise
251(7)
8.2.6 Other Noise Sources
258(2)
Random Telegraph Signal Noise
258(1)
Excess Noise (Flicker Noise)
259(1)
Avalanche Noise
259(1)
8.3 Discussion
260(17)
8.3.1 Correlation
260(4)
Correlation of Input-Referred Noise Sources
261(1)
Complex Input Impedance
262(2)
8.3.2 Noise and Feedback
264(3)
Op-Amp Noise Modeling
265(2)
8.3.3 Some Final Notes Concerning Notation
267(10)
Chapter 9 Models for Analog Design 277(50)
9.1 Long-Channel MOSFETs
277(25)
9.1.1 The Square-Law Equations
279(7)
PMOS Square-Law Equations
280(1)
Qualitative Discussion
280(3)
Threshold Voltage and Body Effect
283(1)
Qualitative Discussion
284(1)
The Triode Region
285(1)
The Cutoff and Subthreshold Regions
286(1)
9.1.2 Small Signal Models
286(14)
Transconductance
287(5)
AC Analysis
292(1)
Transient Analysis
293(1)
Body Effect Transconductance, gmb
294(1)
Output Resistance
295(2)
MOSFET Transition Frequency, fT
297(1)
General Device Sizes for Analog Design
298(1)
Subthreshold gn, and VTHN
299(1)
9.1.3 Temperature Effects
300(2)
Threshold Variation and Temperature
300(1)
Mobility Variation with Temperature
301(1)
Drain Current Change with Temperature
302(1)
9.2 Short-Channel MOSFETs
302(6)
9.2.1 General Design (A Starting Point)
303(3)
Output Resistance
304(1)
Forward Transconductance
304(1)
Transition Frequency
305(1)
9.2.2 Specific Design (A Discussion)
306(2)
9.3 MOSFET Noise Modeling
308(19)
Drain Current Noise Model
308(19)
Chapter 10 Models for Digital Design 327(20)
Miller Capacitance
327(1)
10.1 The Digital MOSFET Model
328
Effective Switching Resistance
328(2)
Short-Channel MOSFET Effective Switching Resistance
330(1)
10.1.1 Capacitive Effects
331(1)
10.1.2 Process Characteristic Time Constant
331(2)
10.1.3 Delay and Transition Times
333
10.1.4 General Digital Design
326(1)
10.2 The MOSFET Pass Gate
326(15)
The PMOS Pass Gate
337(1)
10.2.1 Delay through a Pass Gate
338(2)
The Transmission Gate (The TG)
340(1)
10.2.2 Delay through Series-Connected PGs
340(1)
10.3 A Final Comment Concerning Measurements
341(6)
Chapter 11 The Inverter 347(22)
11.1 DC Characteristics
347(5)
Noise Margins
349(1)
Inverter Switching Point
350(1)
Ideal Inverter VTC and Noise Margins
350(2)
11.2 Switching Characteristics
352(4)
The Ring Oscillator
354(1)
Dynamic Power Dissipation
355(1)
11.3 Layout of the Inverter
356(2)
Latch-Up
356(2)
11.4 Sizing for Large Capacitive Loads
358(6)
Buffer Topology
359(3)
Distributed Drivers
362(1)
Driving Long Lines
363(1)
11.5 Other Inverter Configurations
364(5)
NMOS-Only Output Drivers
365(1)
Inverters with Tri-State Outputs
366(1)
Additional Examples
366(3)
Chapter 12 Static Logic Gates 369(20)
12.1 DC Characteristics of the NAND and NOR Gates
369(4)
12.1.1 DC Characteristics of the NAND Gate
369(3)
12.1.2 DC Characteristics of the NOR Gate
372(2)
A Practical Note Concerning Vsp and Pass Gates
373(1)
12.2 Layout of the NAND and NOR Gates
373(1)
12.3 Switching Characteristics
374(5)
Parallel Connection of MOSFETs
374(1)
Series Connection of MOSFETs
374(1)
12.3.1 NAND Gate
375(3)
Quick Estimate of Delays
377(1)
12.3.2 Number of Inputs
378(1)
12.4 Complex CMOS Logic Gates
379(10)
Cascode Voltage Switch Logic
383(1)
Differential Split-Level Logic
383(1)
Tri-State Outputs
383(1)
Additional Examples
384(5)
Chapter 13 Clocked Circuits 389(22)
13.1 The CMOS TG
389(2)
Series Connection of TGs
390(1)
13.2 Applications of the Transmission Gate
391(4)
Path Selector
391(3)
Static Circuits
394(1)
13.3 Latches and Flip-Flops
395(7)
Basic Latches
395(1)
An Arbiter
396(1)
Flip-Flops and Flow-through Latches
397(2)
An Edge-Triggered D-FF
399(1)
Flip-Flop Timing
400(2)
13.4 Examples
402(9)
Chapter 14 Dynamic Logic Gates 411(14)
14.1 Fundamentals of Dynamic Logic
411(6)
14.1.1 Charge Leakage
411(3)
14.1.2 Simulating Dynamic Circuits
414(1)
14.1.3 Nonoverlapping Clock Generation
415(1)
14.1.4 CMOS TG in Dynamic Circuits
416(1)
14.2 Clocked CMOS Logic
417(8)
Clocked CMOS Latch
417(1)
An Important Note
417(1)
PE Logic
418(1)
Domino Logic
419(1)
NP Logic (Zipper Logic)
420(1)
Pipelining
421(4)
Chapter 15 CMOS Layout Examples 425(20)
15.1 Chip Layout
426(8)
Regularity
426(1)
Standard Cell Examples
426(2)
Power and Ground Considerations
428(3)
An Adder Example
431(2)
A 4-to-1 MUX/DEMUX
433(1)
15.2 Layout Steps
434(11)
Dean Moriarty
Planning and Stick Diagrams
434(3)
Device Placement
437(1)
Polish
437(1)
Standard Cells Versus Full-Custom Layout
437(8)
Chapter 16 Memory Circuits 445(48)
16.1 Array Architectures
446(12)
16.1.1 Sensing Basics
446(6)
NMOS Sense Amplifier (NSA)
447(1)
The Open Array Architecture
447(3)
PMOS Sense Amplifier (PSA)
450(2)
Refresh Operation
452(1)
16.1.2 The Folded Array
452(6)
Layout of the DRAM Memory Bit (Mbit)
453(5)
16.1.3 Chip Organization
458(1)
16.2 Peripheral Circuits
458(13)
16.2.1 Sense Amplifier Design
458(9)
Kickback Noise and Clock Feedthrough
459(2)
Memory
461(1)
Current Draw
461(1)
Contention Current (Switching Current)
461(1)
Removing Sense Amplifier Memory
462(1)
Creating an Imbalance and Reducing Kickback Noise
462(3)
Increasing the Input Range
465(1)
Simulation Examples
466(1)
16.2.2 Row/Column Decoders
467(3)
Global and Local Decoders
468(2)
Reducing Decoder Layout Area
470(1)
16.2.3 Row Drivers
470(1)
16.3 Memory Cells
471(22)
16.3.1 The SRAM Cell
473(1)
16.3.2 Read-Only Memory (ROM)
473(1)
16.3.3 Floating Gate Memory
473(21)
The Threshold Voltage
474(3)
Erasable Programmable Read-Only Memory
477(1)
Two Important Notes
478(1)
Flash Memory
479(14)
Chapter 17 Sensing Using ΔΣ Modulation 493(40)
17.1 Qualitative Discussion
494(12)
17.1.1 Examples of DSM
494(2)
The Counter
495(1)
Cup Size
496(1)
Another Example
496(1)
17.1.2 Using DSM for Sensing in Flash Memory
496(37)
The Basic Idea
497(4)
The Feedback Signal
501(4)
Incomplete Settling
505(1)
17.2 Sensing Resistive Memory
506(7)
The Bit Line Voltage
507(1)
Adding an Offset to the Comparator
507(1)
Schematic and Design Values
508(3)
A Couple of Comments
511(2)
17.3 Sensing in CMOS Imagers
513(20)
Resetting the Pixel
513(1)
The Intensity Level
514(1)
Sampling the Reference and Intensity Signals
514(1)
Noise Issues
514(2)
Subtracting VR from VS
516(10)
Sensing Circuit Mismatches
526(7)
Chapter 18 Special Purpose CMOS Circuits 533(28)
18.1 The Schmitt Trigger
533(5)
18.1.1 Design of the Schmitt Trigger
534(2)
Switching Characteristics
536(1)
18.1.2 Applications of the Schmitt Trigger
536(2)
18.2 Multivibrator Circuits
538(3)
18.2.1 The Monostable Multivibrator
539(1)
18.2.2 The Astable Multivibrator
540(1)
18.3 Input Buffers
541(10)
18.3.1 Basic Circuits
541(2)
Skew in Logic Gates
542(1)
18.3.2 Differential Circuits
543(4)
Transient Response
544(3)
18.3.3 DC Reference
547(3)
18.3.4 Reducing Buffer Input Resistance
550(1)
18.4 Charge Pumps (Voltage Generators)
551(10)
Negative Voltages
552(1)
Using MOSFETs for the Capacitors
553(1)
18.4.1 Increasing the Output Voltage
553(1)
18.4.2 Generating Higher Voltages: The Dickson Charge Pump
553(3)
Clock Driver with a Pumped Output Voltage
554(1)
NMOS Clock Driver
555(1)
18.4.3 Example
556(5)
Chapter 19 Digital Phase-Locked Loops 561(60)
19.1 The Phase Detector
563(7)
19.1.1 The XOR Phase Detector
563(4)
19.1.2 The Phase Frequency Detector
567(3)
19.2 The Voltage-Controlled Oscillator
570(6)
19.2.1 The Current-Starved VCO
570(4)
Linearizing the VCO's Gain
573(1)
19.2.2 Source-Coupled VCOs
574(2)
19.3 The Loop Filter
576(14)
19.3.1 XOR DPLL
577(6)
Active-PI Loop Filter
581(2)
19.3.2 PFD DPLL583
583(7)
Tri-State Output
583(1)
Implementing the PFD in CMOS
584(3)
PFD with a Charge Pump Output
587(1)
Practical Implementation of the Charge Pump
588(1)
Discussion
589(1)
19.4 System Concerns
590(10)
19.4.1 Clock Recovery from NRZ Data
593(10)
The Hogge Phase Detector
596(2)
Jitter
598(2)
19.5 Delay-Locked Loops
600(3)
Delay Elements
602(1)
Practical VCO and VCDL Design
602(1)
19.6 Some Examples
603(18)
19.6.1 A 2 GHz DLL
603(6)
19.6.2 A 1 Gbit/s Clock-Recovery Circuit
609(12)
Chapter 20 Current Mirrors 621(50)
20.1 The Basic Current Mirror
621(22)
20.1.1 Long-Channel Design
622(2)
20.1.2 Matching Currents in the Mirror
624(4)
Threshold Voltage Mismatch
624(1)
Transconductance Parameter Mismatch
624(1)
Drain-to-Source Voltage and Lambda
625(1)
Layout Techniques to Improve Matching
625(2)
Layout of the Mirror with Different Widths
627(1)
20.1.3 Biasing the Current Mirror
628(6)
Using a MOSFET-Only Reference Circuit
629(2)
Supply Independent Biasing
631(3)
20.1.4 Short-Channel Design
634(4)
An Important Note
637(1)
20.1.5 Temperature Behavior
638(4)
Resistor-MOSFET Reference Circuit
638(1)
MOSFET-Only Reference Circuit
639(2)
Temperature Behavior of the Beta-Multiplier
641(1)
Voltage Reference Using the Beta-Multiplier
641(1)
20.1.6 Biasing in the Subthreshold Region
642(1)
20.2 Cascoding the Current Mirror
643(10)
20.2.1 The Simple Cascode
643(2)
DC Operation
643(1)
Cascode Output Resistance
644(1)
20.2.2 Low-Voltage (Wide-Swing) Cascode
645(3)
An Important Practical Note
647(1)
Layout Concerns
648(1)
20.2.3 Wide-Swing, Short-Channel Design
648(3)
20.2.4 Regulated Drain Current Mirror
651(2)
20.3 Biasing Circuits
653(18)
20.3.1 Long-Channel Biasing Circuits
653(3)
Basic Cascode Biasing
653(1)
The Folded-Cascode Structure
653(3)
20.3.2 Short-Channel Biasing CirCuits
656(1)
Floating Current Sources
656(1)
20.3.3 A Final Comment
657(14)
Chapter 21 Amplifiers 671(64)
21.1 Gate-Drain Connected Loads
671(14)
21.1.1 Common-Source (CS) Amplifiers
671(12)
Miller's Theorem
674(1)
Frequency Response
675(1)
The Right-Hand Plane Zero
675(4)
A Common-Source Current Amplifier
679(2)
Common-Source Amplifier with Source Degeneration
681(2)
Noise Performance of the CS Amplifier with Gate-Drain Load
683(1)
21.1.2 The Source Follower (Common-Drain Amplifier)
683(1)
21.1.3 Common Gate Amplifier
684(1)
21.2 Current Source Loads
685(25)
21.2.1 Common-Source Amplifier
685(13)
Class A Operation
685(1)
Small-Signal Gain
686(1)
Open Circuit Gain
686(1)
High-Impedance and Low-Impedance Nodes
687(1)
Frequency Response
687(2)
Pole Splitting
689(3)
Pole Splitting Summary
692(5)
Canceling the RHP Zero
697(1)
Noise Performance of the CS Amplifier with Current Source Load
698(1)
21.2.2 The Cascode Amplifier
698(4)
Frequency Response
699(1)
Class A Operation
700(1)
Noise Performance of the Cascode Amplifier
700(1)
Operation as a Transimpedance Amplifier
701(1)
21.2.3 The Common-Gate Amplifier
702(1)
21.2.4 The Source Follower (Common-Drain Amplifier)
702(8)
Body Effect and Gain
703(1)
Level Shifting
704(1)
Input Capacitance
705(1)
Noise Performance of the SF Amplifier
706(1)
Frequency Behavior
706(2)
SF as an Output Buffer
708(1)
A Class AB Output Buffer Using SFs
709(1)
21.3 The Push-Pull Amplifier
710(25)
21.3.1 DC Operation and Biasing
711(3)
Power Conversion Efficiency
711(3)
21.3.2 Small-Signal Analysis
714(2)
21.3.3 Distortion
716(19)
Modeling Distortion with SPICE
717(18)
Chapter 22 Differential Amplifiers 735(38)
22.1 The Source-Coupled Pair
735(15)
22.1.1 DC Operation
735(6)
Maximum and Minimum Differential Input Voltage
736(1)
Maximum and Minimum Common-Mode Input Voltage
737(2)
Current Mirror Load
739(1)
Biasing from the Current Mirror Load
740(1)
Minimum Power Supply Voltage
741(1)
22.1.2 AC Operation
741(4)
AC Gain with a Current Mirror Load
742(3)
22.1.3 Common-Mode Rejection Ratio
745(1)
Input-Referred Offset from Finite CMRR
746(1)
22.1.4 Matching Considerations
746(3)
Input-Referred Offset with a Current Mirror Load
749(1)
22.1.5 Noise Performance
749(1)
22.1.6 Slew-Rate Limitations
750(1)
22.2 The Source Cross-Coupled Pair
750(6)
Operation of the Diff-Amp
751(1)
Input Signal Range
752(2)
22.2.1 Current Source Load
754(4)
Input Signal Range
755(1)
22.3 Cascode Loads (The Telescopic Diff-Amp)
756(2)
22.4 Wide-Swing Differential Amplifiers
758(15)
22.4.1 Current Differential Amplifier
760(1)
22.4.2 Constant Transconductance Diff-Amp
760(14)
Discussion
761(12)
Chapter 23 Voltage References 773(30)
23.1 MOSFET-Resistor Voltage References
774(10)
23.1.1 The Resistor-MOSFET Divider
774(3)
23.1.2 The MOSFET-Only Voltage Divider
777(1)
23.1.3 Self-Biased Voltage References
778(6)
Forcing the Same Current through Each Side of the Reference
778(5)
An Alternate Topology
783(1)
23.2 Parasitic Diode-Based References
784(19)
Diode Behavior
785(1)
The Bandgap Energy of Silicon
786(1)
Lower Voltage Reference Design
787(1)
23.2.1 Long-Channel BGR Design
787(8)
Diode-Referenced Self-Biasing (CTAT)
787(2)
Thermal Voltage-Referenced Self-Biasing (PTAT)
789(3)
Bandgap Reference Design
792(1)
Alternative BGR Topologies
793(2)
23.2.2 Short-Channel BGR Design
795(62)
The Added Amplifier
796(1)
Lower Voltage Operation
797(6)
Chapter 24 Operational Amplifiers I 803(54)
24.1 The Two-Stage Op-Amp
804(18)
Low-Frequency, Open Loop Gain, AoLDc
804(1)
Input Common-Mode Range
804(1)
Power Dissipation
805(1)
Output Swing and Current Source/Sinking Capability
805(1)
Offsets
805(1)
Compensating the Op-Amp
806(4)
Gain and Phase Margins
810(1)
Removing the Zero
811(1)
Compensation for High-Speed Operation
812(4)
Slew-Rate Limitations
816(2)
Common-Mode Rejection Ratio (CMRR)
818(1)
Power Supply Rejection Ratio (PSBR)
819(1)
Increasing the Input Common-Mode Voltage Range
820(1)
Estimating Bandwidth in Op-Amps Circuits
821(1)
24.2 An Op-Amp with Output Buffer
822(2)
Compensating the Op-Amp
822(2)
24.3 The Operational Transconductance Amplifier (OTA)
824(11)
Unity-Gain Frequency, fun
825(1)
Increasing the OTA Output Resistance
826(1)
An Important Note
827(1)
OTA with an Output Buffer (An Op-Amp)
828(2)
The Folded-Cascode OTA and Op-Amp
830(5)
24.4 Gain-Enhancement
835(4)
Bandwidth of the Added GE Amplifiers
837(1)
Compensating the Added GE Amplifiers
838(1)
24.5 Some Examples and Discussions
839(18)
A Voltage Regulator
839(5)
Bad Output Stage Design
844(2)
Three-Stage Op-Amp Design
846(11)
Chapter 25 Dynamic Analog Circuits 857(32)
25.1 The MOSFET Switch
857(7)
Charge Injection
858(1)
Capacitive Feedthrough
859(1)
Reduction of Charge Injection and Clock Feedthrough
860(1)
kT/C Noise
861(1)
25.1.1 Sample-and-Hold Circuits
861(3)
25.2 Fully-Differential Circuits
864(5)
Gain
864(1)
Common-Mode Feedback
864(1)
Coupled Noise Rejection
865(1)
Other Benefits of Fully-Differential Op-Amps
865(1)
25.2.1 A Fully-Differential Sample-and-Hold
866(3)
Connecting the Inputs to the Bottom (Poly1) Plate
867(1)
Bottom Plate Sampling
868(1)
SPICE Simulation
868(1)
25.3 Switched-Capacitor Circuits
869(10)
25.3.1 Switched-Capacitor Integrator
871(18)
Parasitic Insensitive
872(1)
Other Integrator Configurations
872(4)
Exact Frequency Response of a Switched-Capacitor Integrator
876(1)
Capacitor Layout
877(1)
Op-Amp Settling Time
878(1)
25.4 Circuits
879(10)
Reducing Offset Voltage of an Op-Amp
879(1)
Dynamic Comparator
880(2)
Dynamic Current Mirrors
882(2)
Dynamic Amplifiers
884(5)
Chapter 26 Operational Amplifiers II 889(44)
26.1 Biasing for Power and Speed
889(3)
26.1.1 Device Characteristics
890(1)
26.1.2 Biasing Circuit
891(42)
Layout of Differential Op-Amps
891(1)
Self-Biased Reference
891(1)
26.2 Basic Concepts
892(8)
Modeling Offset
892(1)
A Diff-Amp
893(1)
A Single Bias Input Diff-Amp
894(1)
The Diff-Amp's Tail Current Source
895(1)
Using a CMFB Amplifier
895(1)
Compensating the CMFB Loop
896(2)
Extending the CMFB Amplifier Input Range
898(1)
Dynamic CMFB
899(1)
26.3 Basic Op-Amp Design
900(20)
The Differential Amplifier
902(1)
Adding a Second Stage (Making an Op-Amp)
903(1)
Step Response
904(1)
Adding CMFB
905(2)
CMFB Amplifier
907(1)
The Two-Stage Op-Amp with CMFB
908(1)
Origin of the Problem
909(1)
Simulation Results
910(1)
Using MOSFETs Operating in the Triode Region
911(1)
Start-up Problems
912(1)
Lowering Input Capacitance
912(1)
Making the Op-Amp More Practical
913(1)
Increasing the Op-Amp's Open-Loop Gain
914(2)
Offsets
916(1)
Op-Amp Offset Effects on Outputs
916(2)
Single-Ended to Differential Conversion
918(1)
CMFB Settling Time
919(1)
CMFB in the Output Buffer (Fig. 26.43) or the Diff-Amp (Fig. 26.40)?
919(1)
26.4 Op-Amp Design Using Switched-Capacitor CMFB
920(13)
Clock Signals
920(1)
Switched-Capacitor CMFB
921(1)
The Op-Amp's First Stage
921(3)
The Output Buffer
924(1)
An Application of the Op-Amp
925(1)
Simulation Results
925(2)
A Final Note Concerning Biasing
927(6)
Chapter 27 Nonlinear Analog Circuits 933(22)
27.1 Basic CMOS Comparator Design
933(10)
Preamplification
934(1)
Decision Circuit
935(2)
Output Buffer
937(2)
27.1.1 Characterizing the Comparator
939(3)
Comparator DC Performance
939(1)
Transient Response
940(1)
Propagation Delay
941(1)
Minimum Input Slew Rate
942(1)
27.1.2 Clocked Comparators
942(1)
27.1.3 Input Buffers Revisited
943(1)
27.2 Adaptive Biasing
943(3)
27.3 Analog Multipliers
946(9)
27.3.1 The Multiplying Quad
947(4)
Simulating the Operation of the Multiplier
949(2)
27.3.2 Multiplier Design Using Squaring Circuits
951(4)
Chapter 28 Data Converter Fundamentals 955(32)
Harry Li
28.1 Analog Versus Discrete Time Signals
955(1)
28.2 Converting Analog Signals to Digital Signals
956(3)
28.3 Sample-and-Hold (S/H) Characteristics
959(2)
Sample Mode
959(1)
Hold Mode
960(1)
Aperture Error
960(1)
28.4 Digital-to-Analog Converter (DAC) Specifications
961(9)
Differential Nonlinearity
964(2)
Integral Nonlinearity
966(2)
Offset
968(1)
Gain Error
969(1)
Latency
969(1)
Signal-to-Noise Ratio (SNR)
969(1)
Dynamic Range
969(1)
28.5 Analog-to-Digital Converter (ADC) Specifications
970(9)
Quantization Error
971(1)
Differential Nonlinearity
972(2)
Missing Codes
974(1)
Integral Nonlinearity
974(1)
Offset and Gain Error
975(1)
Aliasing
976(2)
Signal-to-Noise Ratio
978(1)
Aperture Error
979(1)
28.6 Mixed-Signal Layout Issues
979(8)
Floorplanning
980(1)
Power Supply and Ground Issues
980(2)
Fully Differential Design
982(1)
Guard Rings
982(1)
Shielding
983(1)
Other Interconnect Considerations
984(3)
Chapter 29 Data Converter Architectures 987(56)
Harry Li
29.1 DAC Architectures
987(19)
29.1.1 Digital Input Code
987(1)
29.1.2 Resistor String
987(5)
Mismatch Errors Related to the Resistor-String DAC
990(1)
Integral Nonlinearity of the Resistor-String DAC
991(1)
Differential Nonlinearity of the Worst-Case Resistor String DAC
992(1)
29.1.3 R-2R Ladder Networks
992(3)
29.1.4 Current Steering
995(4)
Mismatch Errors Related to Current-Steering DACs
997(2)
29.1.5 Charge-Scaling DACs
999(4)
Layout Considerations for a Binary-Weighted Capacitor Array
1001(1)
The Split Array
1002(1)
29.1.6 Cyclic DAC
1003(2)
29.1.7 Pipeline DAC
1005(1)
29.2 ADC Architectures
1006(37)
29.2.1 Flash
1006(4)
Accuracy Issues for the Flash ADC
1007(3)
29.2.2 The Two-Step Flash ADC
1010(4)
Accuracy Issues Related to the Two-Step Flash Converter
1012(1)
Accuracy Issues Related to Operational Amplifiers
1013(1)
29.2.3 The Pipeline ADC
1014(4)
Accuracy Issues Related to the Pipeline Converter
1016(2)
29.2.4 Integrating ADCs
1018(4)
Single-Slope Architecture
1018(2)
Accuracy Issues Related to the Single-Slope ADC
1020(1)
Dual-Slope Architecture
1020(2)
Accuracy Issues Related to the Dual-Slope ADC
1022(1)
29.2.5 The Successive Approximation ADC
1022(5)
The Charge-Redistribution Successive Approximation ADC
1025(1)
Accuracy Issues Related to the Charge Redistribution, Successive-Approximation ADC
1026(1)
29.2.6 The Oversampling ADC
1027(20)
Differences in Nyquist Rate and Oversampled ADCs
1027(2)
The First-Order ΣΔ Modulator
1029(4)
The Higher Order ΣΔ Modulators
1033(10)
Chapter 30 Implementing Data Converters 1043(72)
30.1 R-2R Topologies for DACs
1043(20)
30.1.1 The Current-Mode R-2R DAC
1044(1)
30.1.2 The Voltage-Mode R-2R DAC
1045(2)
30.1.3 A Wide-Swing Current-Mode R-2R DAC
1047(10)
DNL Analysis
1048(1)
INL Analysis
1049(1)
Switches
1049(1)
Experimental Results
1050(1)
Improving DNL (Segmentation)
1051(1)
Trimming DAC Offset
1052(3)
Trimming DAC Gain
1055(1)
Improving INL by Calibration
1055(2)
30.1.4 Topologies Without an Op-Amp
1057(6)
The Voltage-Mode DAC
1057(3)
Two Important Notes Concerning Glitches
1060(1)
The Current-Mode (Current Steering) DAC
1061(2)
30.2 Op-Amps in Data Converters
1063(7)
Gain Bandwidth Product of the Noninverting Op-Amp Topology
1064(1)
Gain Bandwidth Product of the Inverting Op-Amp Topology
1064(2)
30.2.1 Op-Amp Gain
1066(1)
30.2.2 Op-Amp Unity Gain Frequency
1067(1)
30.2.3 Op-Amp Offset
1067(3)
Adding an Auxiliary Input Port
1067(3)
30.3 Implementing ADCs
1070(45)
30.3.1 Implementing the S/H
1071(6)
A Single-Ended to Differential Output S/H
1073(4)
30.3.2 The Cyclic ADC
1077(7)
Comparator Placement
1078(2)
Implementing Subtraction in the S/H
1080(2)
Understanding Output Swing
1082(2)
30.3.3 The Pipeline ADC
1084(31)
Using 1.5 Bits/Stage
1085(7)
Capacitor Error Averaging
1092(6)
Comparator Placement
1098(1)
Clock Generation
1099(1)
Offsets and Alternative Design Topologies
1100(5)
Dynamic CMFB
1105(2)
Layout of Pipelined ADCs
1107(8)
Chapter 31 Feedback Amplifiers 1115(60)
Harry Li
31.1 The Feedback Equation
1115(2)
31.2 Properties of Negative Feedback on Amplifier Design
1117(3)
31.2.1 Gain Desensitivity
1117(1)
31.2.2 Bandwidth Extension
1117(1)
31.2.3 Reduction in Nonlinear Distortion
1118(2)
31.2.4 Input and Output Impedance Control
1120(1)
31.3 Recognizing Feedback Topologies
1120(8)
31.3.1 Input Mixing
1121(1)
31.3.2 Output Sampling
1121(1)
31.3.3 The Feedback Network
1122(3)
An Important Assumption
1123(1)
Counting Inversions Around the Loop
1124(1)
Examples of Recognizing Feedback Topologies
1124(1)
31.3.4 Calculating Open-Loop Parameters
1125(2)
31.3.5 Calculating Closed-Loop Parameters
1127(1)
31.4 The Voltage Amp (Series-Shunt Feedback)
1128(6)
31.5 The Transimpedance Amp (Shunt-Shunt Feedback)
1134(8)
31.5.1 Simple Feedback Using a Gate-Drain Resistor
1140(2)
31.6 The Transconductance Amp (Series-Series Feedback)
1142(4)
31.7 The Current Amplifier (Shunt-Series Feedback)
1146(2)
31.8 Stability
1148(6)
31.8.1 The Return Ratio
1151(3)
31.9 Design Examples
1154(22)
31.9.1 Voltage Amplifiers
1154(4)
Amplifiers with Gain
1156(2)
31.9.2 A Transimpedance Amplifier
1158(17)
Chapter 32 Hysteretic Power Converters 1175(44)
32.1 A Review of Power and Energy Basics
1176(13)
An Analogy
1177(1)
32.1.1 Energy Storage in Inductors and Capacitors
1177(3)
Energy Storage in an Inductor
1178(1)
Energy Storage in a Capacitor
1178(2)
32.1.2 Energy Use in Transmitting Data
1180(1)
32.1.3 Selection and use of Switches
1181(8)
Using an NMOS Pull-Up
1183(1)
Effective Digital Resistance, A Comment
1184(1)
Driver Optimization
1184(1)
Higher Voltage Switches
1184(5)
32.2 Switching Power Supplies: Some Examples
1189(21)
32.2.1 The Buck SPS
1189(7)
Selecting the Inductor
1191(1)
Selecting the Capacitor
1191(4)
Power Supply Efficiency
1195(1)
32.2.2 The Boost SPS
1196(4)
Selecting the Inductor
1197(1)
Selecting the Capacitor
1197(3)
32.2.3 The Flyback SPS
1200(4)
Quick Review of Transformers
1200(1)
Operation of the Flyback SPS
1201(3)
32.2.4 Pulse Width Modulation: A Control Loop Example
1204(6)
Buck SPS Control Loop
1206(1)
Boost SPS Control Loop
1207(1)
Flyback SPS Control Loop
1208(1)
Effective Series Resistance
1209(1)
Some Comments
1210(1)
32.3 Hysteretic Control
1210(9)
32.3.1 Topologies
1211(1)
32.3.2 Examples
1212(7)
Buck HPS Control Loop
1212(1)
Boost HPS Control Loop
1213(1)
Flyback HPS Control Loop
1214(2)
Some Final Comments
1216(3)
Index 1219(16)
About the Author 1235
R. JACOB (JAKE) BAKER, PHD, is an engineer, educator, and inventor. He has more than twenty years of engineering experience and holds more than 200 granted or pending patents in integrated circuit design. Jake is the author of several circuit design books for Wiley-IEEE Press. In 2007, he received the Hewlett-Packard Frederick Emmons Terman Award.