This book provides a comprehensive overview of flow-based, microfluidic VLSI. The authors describe and solve in a comprehensive and holistic manner practical challenges such as control synthesis, wash optimization, design for testability, and diagnosis of modern flow-based microfluidic biochips. They introduce practical solutions, based on rigorous optimization and formal models. The technical contributions presented in this book will not only shorten the product development cycle, but also accelerate the adoption and further development of modern flow-based microfluidic biochips, by facilitating the full exploitation of design complexities that are possible with current fabrication techniques.
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1 | (24) |
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1.1 Introduction of Microfluidic Biochip Platforms |
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2 | (4) |
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1.2 Overview of Flow-Based Microfluidic Biochips |
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6 | (9) |
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1.2.1 Structure and Fabrication |
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7 | (1) |
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8 | (4) |
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12 | (3) |
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1.3 Challenges and Motivation |
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15 | (4) |
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16 | (1) |
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1.3.2 Contamination Removal |
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16 | (1) |
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1.3.3 Defects and Erroneous Operations |
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17 | (2) |
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19 | (6) |
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20 | (5) |
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2 Control-Layer Optimization |
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25 | (28) |
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2.1 Motivation and Related Prior Work |
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26 | (1) |
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2.2 Problem Description, Design Requirements, and Challenges |
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26 | (9) |
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2.2.1 Pressure-Propagation Delay |
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26 | (1) |
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2.2.2 Requirements in Control-Layer Design |
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27 | (3) |
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30 | (3) |
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2.2.4 Routing of Control Channels |
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33 | (1) |
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2.2.5 Placement of Control Pins |
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34 | (1) |
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2.2.6 Relationship Between Control-Layer Optimization and Clock-Tree Design in VLSI Circuits |
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34 | (1) |
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35 | (1) |
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36 | (9) |
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2.4.1 Routing Algorithm 1 |
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37 | (4) |
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2.4.2 Routing Algorithm 2 |
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41 | (4) |
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45 | (5) |
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2.5.1 Experiments with Two Fabricated Biochips |
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46 | (4) |
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2.5.2 Experiments with Synthetic Benchmarks |
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50 | (1) |
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50 | (3) |
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51 | (2) |
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3 Wash Optimization for Cross-Contamination Removal |
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53 | (28) |
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3.1 Motivation and Challenges |
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54 | (1) |
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3.2 Problem Description and Formulation |
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55 | (7) |
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3.2.1 Physical Implementability of a Wash Path |
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55 | (2) |
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3.2.2 Execution Time for a Wash Path |
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57 | (5) |
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3.3 Search for a Set of Washing Paths |
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62 | (10) |
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3.3.1 Generation of the Path Dictionary |
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62 | (2) |
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3.3.2 Storage of the Path Dictionary |
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64 | (1) |
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3.3.3 Identification of Washing-Path Set |
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65 | (4) |
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3.3.4 Washing of Multiple Contaminant Species |
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69 | (2) |
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3.3.5 Complexity Analysis |
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71 | (1) |
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3.4 Results: Application to Fabricated Biochips |
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72 | (6) |
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73 | (4) |
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3.4.2 A Programmable Microfluidic Device with an 8-by-8 Grid |
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77 | (1) |
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78 | (3) |
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79 | (2) |
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4 Fault Modeling, Testing, and Design for Testability |
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81 | (36) |
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4.1 Motivation and Challenges |
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82 | (1) |
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4.2 Defects and Fault Modeling |
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83 | (3) |
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86 | (4) |
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4.4 Applications to Fabricated Biochip |
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90 | (2) |
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4.4.1 Logic Circuit Model |
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90 | (1) |
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4.4.2 Test-Pattern Generation and Results |
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91 | (1) |
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4.5 Automated Generation of Logic-Circuit Model |
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92 | (5) |
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4.5.1 Physical Representation of Boolean Gates in Netlists |
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92 | (2) |
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4.5.2 Hierarchical Modeling |
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94 | (3) |
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4.5.3 Fault Analysis Based on ATPG Results |
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97 | (1) |
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4.6 Other Practical Concerns |
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97 | (2) |
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98 | (1) |
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98 | (1) |
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99 | (1) |
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4.7 Experimental Demonstration |
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99 | (8) |
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4.7.1 Experimental Feasibility Demonstration |
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99 | (2) |
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4.7.2 Pattern Set-up Time, Measurement Time and Refresh Time |
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101 | (2) |
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4.7.3 Experimental Demonstration I: Cell Culture Chip |
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103 | (3) |
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4.7.4 Experimental Demonstration II: WGA Chip |
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106 | (1) |
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4.8 Untestable Faults and Design-For-Testability |
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107 | (7) |
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4.8.1 Causes of Untestable Faults |
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109 | (1) |
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4.8.2 DfT for Flow-Based Microfluidic Biochips |
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110 | (2) |
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4.8.3 Demonstration of Proposed DfT Approach |
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112 | (2) |
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114 | (3) |
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114 | (3) |
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5 Techniques for Fault Diagnosis |
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117 | (20) |
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5.1 Motivation and Challenges |
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117 | (1) |
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118 | (9) |
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5.2.1 Single-Defect-Type Assumption |
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118 | (1) |
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119 | (2) |
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5.2.3 Formulation as a Hitting-Set Problem |
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121 | (6) |
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127 | (4) |
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5.3.1 Complexity Analysis |
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130 | (1) |
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5.4 Results: Application to Fabricated Biochips |
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131 | (5) |
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5.4.1 Results for ChIP Chip |
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132 | (1) |
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5.4.2 Results for WGA Chip |
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133 | (2) |
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5.4.3 Results for Cell Culture Chip |
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135 | (1) |
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136 | (1) |
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136 | (1) |
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6 Conclusions and New Directions |
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137 | (4) |
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137 | (1) |
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6.2 Opportunities and New Directions |
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138 | (3) |
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6.2.1 Fault-Tolerant Design |
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139 | (1) |
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6.2.2 Programmable Multipurpose Biochip Platforms |
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139 | (1) |
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6.2.3 Balancing Control Channels by Modifying Channel Width |
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139 | (1) |
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6.2.4 Washing in Parallel |
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140 | (1) |
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6.2.5 Testing for Dynamic Defects |
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140 | (1) |
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140 | (1) |
| Index |
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141 | |
Kai Hu received his B. Sci. degree from Fudan University, Shanghai, China, in 2009, and the M.S. and Ph.D. degree from Duke University, NC, USA, in 2011 and 2015, respectively. He was the recipient of the VLSI Test Symposium (VTS) Best Paper Award in 2013, IEEE Transactions on Computer-Aided Design Donald O. Pederson Best Paper Award in 2015, and European Design and Automation Association (EDAA) Outstanding Dissertation Award in 2016.
He is currently a Senior Engineer with Oracle. Inc., Santa Clara, CA, USA. His current research interests include algorithms for computer-aided design and testing of flow-based microfluidic biochips.
Krishnendu Chakrabarty is the William H. Younger Distinguished Professor of Engineering in the Department of Electrical and Computer Engineering, at Duke University in Durham, NC. He has been at Duke University since 1998. His current research is focused on: testing and design-for-testability of integrated circuits (especially 3D and multicore chips); digital microfluidics, biochips, and cyberphysical systems; optimization of digital print and production system infrastructure. His research projects in the recent past have also included chip cooling using digital microfluidics, wireless sensor networks, and real-time embedded systems. Research support is provided by the National Science Foundation, the Semiconductor Research Corporation, Cisco Systems, HP Labs, Huawei Technologies, and Intel Corporation through Intel Lab's Academic Research Office. Other sponsors in the past have included National Institutes of Health , DARPA and the Office of Naval Research.
Prof. Chakrabarty received the B. Tech. degree from the Indian Institute of Technology, Kharagpur, India in 1990, and the M.S.E. and Ph.D. degrees from the University of Michigan, Ann Arbor in 1992 and 1995, respectively, all in Computer Science and Engineering . During 1990-95, he was a research assistant at the Advanced Computer Architecture Laboratory of the Department of Electrical Engineering and Computer Science, University of Michigan. During 1995-1998, he was an Assistant Professor of Electrical and Computer Engineering at Boston University.
Prof. Chakrabarty is a Fellow of ACM, a Fellow of IEEE, and a Golden Core Member of the IEEE Computer Society. He is also an Invitational Fellow of the Japan Society for the Promotion of Science (JSPS), 2009. He is a recipient of the IEEE Computer Society Meritorious Service Award. Prof. Chakrabarty was a Chair Professor in the School of Software in Tsinghua University, Beijing, China (2009-2013), and a Visiting Chair Professor in Computer Science and Information Engineering at National Cheng Kung University in Taiwan (2012-2013). He has held Visiting Professor positions at University of Tokyo (Japan), Nara Institute of Science and Technology (Japan), and University of Potsdam (Germany), and a Guest Professor position at University of Bremen (Germany).
Tsung-Yi Ho received his Ph.D. in Electrical Engineering from National Taiwan University in 2005. He is a Professor with the Department of Computer Science of National Tsing Hua University, Hsinchu, Taiwan. His research interests include design automation and test for microfluidic biochips and nanometer integrated circuits. He has presented 10 tutorials and contributed 10 special sessions in ACM/IEEE conferences, all in design automation for microfluidic biochips. He has been the recipient of the Invitational Fellowship of the Japan Society for the Promotion of Science (JSPS), the Humboldt Research Fellowship by the Alexander von Humboldt Foundation, and the Hans Fischer Fellow by the Institute of Advanced Study of the Technical University of Munich. He was a recipient of the Best Paper Awards at the VLSI Test Symposium (VTS) in 2013 and IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems in 2015. He served as a Distinguished Visitor ofthe IEEE Computer Society for 2013-2015, the Chair of the IEEE Computer Society Tainan Chapter for 2013-2015, and the Chair of the ACM SIGDA Taiwan Chapter for 2014-2015. Currently he serves as an ACM Distinguished Speaker, a Distinguished Lecturer of the IEEE Circuits and Systems Society, and Associate Editor of the ACM Journal on Emerging Technologies in Computing Systems, ACM Transactions on Design Automation of Electronic Systems, ACM Transactions on Embedded Computing Systems, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, and IEEE Transactions on Very Large Scale Integration Systems, Guest Editor of IEEE Design & Test of Computers, and the Technical Program Committees of major conferences, including DAC, ICCAD, DATE, ASP-DAC, ISPD, ICCD, etc.
