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Computer Architecture: A Minimalist Perspective 2003 ed. [Kõva köide]

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Computer Architecture: A Minimalist Perspective is designed to meet the needs of a professional audience composed of researchers, computer hardware engineers, software engineers, computational theorists, and systems engineers. The book is also intended for use by upper division undergraduate students and early graduate students studying computer architecture or embedded systems. It is an excellent text for use as a supplement or alternative in traditional Computer Architecture Courses or in courses entitled "Special Topics in Computer Architecture."

Suitable for use as a supplemental text in a graduate course, this book examines the history and architectures of single instruction set computers, then maps other processor architectures and instruction sets into single instructions for benchmarking purposes. Applications of one instruction processors to genetic algorithms and imaging are discussed. An appendix shows how a MOVE-based single instruction set computer can make use of an existing MOS Technology 6502 processor. Annotation (c) Book News, Inc., Portland, OR (booknews.com)

The one instruction set computer (OISC) is the ultimate reduced instruction set computer (RISC). In OISC, the instruction set consists of only one instruction, and then by composition, all other necessary instructions are synthesized. This is an approach completely opposite to that of a complex instruction set computer (CISC), which incorporates complex instructions as microprograms within the processor. Computer Architecture: A Minimalist Perspective examines computer architecture, computability theory, and the history of computers from the perspective of one instruction set computing - a novel approach in which the computer supports only one, simple instruction. This bold, new paradigm offers significant promise in biological, chemical, optical, and molecular scale computers. Features include: - Provides a comprehensive study of computer architecture using computability theory as a base. - Provides a fresh perspective on computer architecture not found in any other text. - Covers history, theory, and practice of computer architecture from a minimalist perspective. Includes a complete implementation of a one instruction computer.- Includes exercises and programming assignments. Computer Architecture: A Minimalist Perspective is designed to meet the needs of a professional audience composed of researchers, computer hardware engineers, software engineers computational theorists, and systems engineers. The book is also intended for use in upper division undergraduate students and early graduate students studying computer architecture or embedded systems. It is an excellent text for use as a supplement or alternative in traditional Computer Architecture Courses, or in courses entitled "Special Topics in Computer Architecture".

Arvustused

`This book gives a fine introduction to basic computer architecture. A few years ago, this book would have interested only graduate computer science and engineering students. These days, some high school students even create Linux clusters, and interest in it may be even more widespread.' R.P. Sarna, Maine Maritime Academy in Choice, December 2003

Muu info

Springer Book Archives
1. One Instruction Set Computing.- 1.1 What is One Instruction Set
Computing?.- 1.2 Why Study OISC?.- 1.3 A Look Ahead.- 1.4 Exercises.- 2
Instruction Sets.- 2.1 Elements of an Instruction.- 2.2 Operands.- 2.3
Instruction Formats.- 2.4 Core Set of Instructions.- 2.5 Addressing Modes.-
2.6 Exercises.- 3 Types of Computer Architectures.- 3.1 Overview.- 3.2 A
Simple Taxonomy.- 3.3 Accumulator.- 3.4 Register-Memory.- 3.5
Register-Oriented.- 3.6 Exercises.- 4 Evolution of Instruction Sets.- 4.1
Motivation.- 4.2 Evolution of Microprocessors.- 4.3 Timeline.- 4.4
Exercises.- 5 CISC, RISC, OISC.- 5.1 CISC versus RISC.- 5.2 Is OISC a CISC or
RISC?.- 5.3 Processor Complexity.- 5.4 Exercises.- 6 OISC Architectures.- 6.1
Single Instruction Types.- 6.2 MOVE.- 6.3 Comparing OISC Models.- 6.4
Variants of SBN and MOVE.- 6.5 OISC Continuum.- 6.6 Exercises.- 7 Historical
Review of OISC.- 7.1 Subtract and Branch if Negative (SBN).- 7.2 MOVE-based.-
7.3 Timeline.- 7.4 Exercises.- 8 Instruction Set Completeness.- 8.1
Instruction Set Completeness.- 8.2 A Practical Approach to Determining
Completeness.- 8.3 Completeness of Two OISCs.- 8.4 Exercises.- 9 OISC
Mappings.- 9.1 Mapping OISC to Conventional Architectures.- 9.2 Synthesizing
Instructions.- 9.3 Code Fragments.- 9.4 Implementing OISC using OISC.- 9.5
Exercises.- 10 Parallel Architectures.- 10.1 Von Neumann Bottleneck.- 10.2
Parallel Processing.- 10.3 Flynns Taxonomy for Parallelism.- 10.4
Exercises.- 11 Applications and Implementations.- 11.1 OlSC-like
Phenomena.- 11.2 Field Programmable Gate Arrays.- 11.3 Applications.- 11.4
Image Processing.- 11.5 Future Work with OISC.- 11.6 Exercises.- Appendix A:
A Generic Microprocessor and OISC.- Appendix B: One Instruction Set Computer
Implementation.- B.1 6502 Opcodes Summary.- B.2 6502Opcodes Mapped to MOVE
OISC.- B.3 6502 Addressing as MOVE-based OISC.- B.4 6502 Addressing Modes and
MOVE-based OISC.- Appendix C: Dilation Code Implementation.- Appendix D:
Compiler Output for Dilation.- Appendix E: OISC Equivalent of Dilation.-
References.- About the Authors.