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Computer Architecture: A Quantitative Approach 6th edition [Pehme köide]

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(Departments of Electrical Engineering and Computer Science, Stanford University, USA), (Pardee Professor of Computer Science, Emeritus, University of California at Berkeley, USA)
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For over 20 years, Computer Architecture: A Quantitative Approach has been considered essential reading by instructors, students, and practitioners of computer design. The latest edition of this classic textbook is fully revised with the latest developments in processor and system architecture. It now features examples from the RISC-V ("RISC Five") instruction set architecture, a modern RISC instruction set developed and designed to be a free and openly adoptable standard. It also includes a new chapter on domain-specific architectures and an updated chapter on warehouse-scale computing that features the first public information on Google's newest WSC. True to its original mission of demystifying computer architecture, the sixth edition of Computer Architecture: A Quantitative Approach continues its longstanding tradition of focusing on the areas where the most exciting computing innovation is happening, while always keeping an emphasis on good engineering design.

  • Includes a new chapter on domain-specific architectures, explaining how they are only path forward for improved performance and energy efficiency given the end of Moore’s Law and Dinnard scaling. Features first publication of several DSAs from industry.
  • Features extensive updates to the chapter on warehouse-scale computing, with first public information on the newest Google WSC.
  • Updates to other chapters include new material dealing with the use of stacked DRAM; data on the performance of new Nvidia Pascal GPU vs new AVX/512 Intel Skylake CPU; and extensive additions to content covering multicore architecture and organization.
  • Trademark Putting It All Together sections appear near the end of every chapter, providing real-world technology examples that demonstrated the principles covered in each chapter.
  • Includes review appendices in the printed text and additional reference appendices available online
  • Includes updated and improved case studies and exercises.

Arvustused

"What has made this book an enduring classic is that each edition is not an update, but an extensive revision that presents the most current information and unparalleled insight into this fascinating and fast changing field. For me, after over twenty years in this profession, it is also another opportunity to experience that student-grade admiration for two remarkable teachers." --From the Foreword by Luiz Andre Barroso, Google, Inc.

Muu info

Fully updated fifth edition covers the twin shifts to mobile and cloud computing, with new material, exercises, and case studies
Foreword ix
Preface xvii
Acknowledgments xxv
Chapter 1 Fundamentals of Quantitative Design and Analysis
1.1 Introduction
2(4)
1.2 Classes of Computers
6(5)
1.3 Defining Computer Architecture
11(7)
1.4 Trends in Technology
18(5)
1.5 Trends in Power and Energy in Integrated Circuits
23(6)
1.6 Trends in Cost
29(7)
1.7 Dependability
36(3)
1.8 Measuring, Reporting, and Summarizing Performance
39(9)
1.9 Quantitative Principles of Computer Design
48(7)
1.10 Putting It All Together: Performance, Price, and Power
55(3)
1.11 Fallacies and Pitfalls
58(6)
1.12 Concluding Remarks
64(3)
1.13 Historical Perspectives and References
67(11)
Case Studies and Exercises
67(11)
Diana Franklin
Chapter 2 Memory Hierarchy Design
2.1 Introduction
78(6)
2.2 Memory Technology and Optimizations
84(10)
2.3 Ten Advanced Optimizations of Cache Performance
94(24)
2.4 Virtual Memory and Virtual Machines
118(8)
2.5 Cross-Cutting Issues: The Design of Memory Hierarchies
126(3)
2.6 Putting It All Together: Memory Hierarchies in the ARM Cortex-A53 and Intel Core i7 6700
129(13)
2.7 Fallacies and Pitfalls
142(4)
2.8 Concluding Remarks: Looking Ahead
146(2)
2.9 Historical Perspectives and References
148(20)
Case Studies and Exercises
148(20)
Norman P. Jouppi
Rajeev Balasubramonian
Naveen Muralimanohar
Sheng Li
Chapter 3 Instruction-Level Parallelism and Its Exploitation
3.1 Instruction-Level Parallelism: Concepts and Challenges
168(8)
3.2 Basic Compiler Techniques for Exposing ILP
176(6)
3.3 Reducing Branch Costs With Advanced Branch Prediction
182(9)
3.4 Overcoming Data Hazards With Dynamic Scheduling
191(10)
3.5 Dynamic Scheduling: Examples and the Algorithm
201(7)
3.6 Hardware-Based Speculation
208(10)
3.7 Exploiting ILP Using Multiple Issue and Static Scheduling
218(4)
3.8 Exploiting ILP Using Dynamic Scheduling, Multiple Issue, and Speculation
222(6)
3.9 Advanced Techniques for Instruction Delivery and Speculation
228(12)
3.10 Cross-Cutting Issues
240(2)
3.11 Multithreading: Exploiting Thread-Level Parallelism to Improve Uniprocessor Throughput
242(5)
3.12 Putting It All Together: The Intel Core i7 6700 and ARM Cortex-A53
247(11)
3.13 Fallacies and Pitfalls
258(6)
3.14 Concluding Remarks: What's Ahead?
264(2)
3.15 Historical Perspective and References
266(16)
Case Studies and Exercises
266(16)
Jason D. Bakos
Robert P. Colwell
Chapter 4 Data-Level Parallelism in Vector, SIMD, and GPU Architectures
4.1 Introduction
282(1)
4.2 Vector Architecture
283(21)
4.3 SIMD Instruction Set Extensions for Multimedia
304(6)
4.4 Graphics Processing Units
310(26)
4.5 Detecting and Enhancing Loop-Level Parallelism
336(9)
4.6 Cross-Cutting Issues
345(1)
4.7 Putting It All Together: Embedded Versus Server GPUs and Tesla Versus Core i7
346(7)
4.8 Fallacies and Pitfalls
353(4)
4.9 Concluding Remarks
357(1)
4.10 Historical Perspective and References
357(11)
Case Study and Exercises
357(11)
Jason D. Bakos
Chapter 5 Thread-Level Parallelism
5.1 Introduction
368(9)
5.2 Centralized Shared-Memory Architectures
377(16)
5.3 Performance of Symmetric Shared-Memory Multiprocessors
393(11)
5.4 Distributed Shared-Memory and Directory-Based Coherence
404(8)
5.5 Synchronization: The Basics
412(5)
5.6 Models of Memory Consistency: An Introduction
417(5)
5.7 Cross-Cutting Issues
422(4)
5.8 Putting It All Together: Multicore Processors and Their Performance
426(12)
5.9 Fallacies and Pitfalls
438(4)
5.10 The Future of Multicore Scaling
442(2)
5.11 Concluding Remarks
444(1)
5.12 Historical Perspectives and References
445(21)
Case Studies and Exercises
446(20)
Amr Zaky
David A. Wood
Chapter 6 Warehouse-Scale Computers to Exploit Request-Level and Data-Level Parallelism
6.1 Introduction
466(5)
6.2 Programming Models and Workloads for Warehouse-Scale Computers
471(6)
6.3 Computer Architecture of Warehouse-Scale Computers
477(5)
6.4 The Efficiency and Cost of Warehouse-Scale Computers
482(8)
6.5 Cloud Computing: The Return of Utility Computing
490(11)
6.6 Cross-Cutting Issues
501(2)
6.7 Putting It All Together: A Google Warehouse-Scale Computer
503(11)
6.8 Fallacies and Pitfalls
514(4)
6.9 Concluding Remarks
518(1)
6.10 Historical Perspectives and References
519(21)
Case Studies and Exercises
519(21)
Parthasarathy Ranganathan
Chapter 7 Domain-Specific Architectures
7.1 Introduction
540(3)
7.2 Guidelines for DSAs
543(1)
7.3 Example Domain: Deep Neural Networks
544(13)
7.4 Google's Tensor Processing Unit, an Inference Data Center Accelerator
557(10)
7.5 Microsoft Catapult, a Flexible Data Center Accelerator
567(12)
7.6 Intel Crest, a Data Center Accelerator for Training
579(1)
7.7 Pixel Visual Core, a Personal Mobile Device Image Processing Unit
579(13)
7.8 Cross-Cutting Issues
592(3)
7.9 Putting It All Together: CPUs Versus GPUs Versus DNN Accelerators
595(7)
7.10 Fallacies and Pitfalls
602(2)
7.11 Concluding Remarks
604(2)
7.12 Historical Perspectives and References
606(1)
Case Studies and Exercises
606
Cliff Young
Appendix A Instruction Set Principles
A.1 Introduction
2(1)
A.2 Classifying Instruction Set Architectures
3(4)
A.3 Memory Addressing
7(6)
A.4 Type and Size of Operands
13(2)
A.5 Operations in the Instruction Set
15(1)
A.6 Instructions for Control Flow
16(5)
A.7 Encoding an Instruction Set
21(3)
A.8 Cross-Cutting Issues: The Role of Compilers
24(9)
A.9 Putting It All Together: The RISC-V Architecture
33(9)
A.10 Fallacies and Pitfalls
42(4)
A.11 Concluding Remarks
46(1)
A.12 Historical Perspective and References
47(1)
Exercises
47
Gregory D. Peterson
Appendix B Review of Memory Hierarchy
B.1 Introduction
2(13)
B.2 Cache Performance
15(7)
B.3 Six Basic Cache Optimizations
22(18)
B.4 Virtual Memory
40(9)
B.5 Protection and Examples of Virtual Memory
49(8)
B.6 Fallacies and Pitfalls
57(2)
B.7 Concluding Remarks
59(1)
B.8 Historical Perspective and References
59(1)
Exercises
60
Amr Zaky
Appendix C Pipelining: Basic and Intermediate Concepts
C.1 Introduction
2(8)
C.2 The Major Hurdle of Pipelining---Pipeline Hazards
10(16)
C.3 How Is Pipelining Implemented?
26(11)
C.4 What Makes Pipelining Hard to Implement?
37(8)
C.5 Extending the RISC V Integer Pipeline to Handle Multicycle Operations
45(10)
C.6 Putting It All Together: The MIPS R4000 Pipeline
55(10)
C.7 Cross-Cutting Issues
65(5)
C.8 Fallacies and Pitfalls
70(1)
C.9 Concluding Remarks
71(1)
C.10 Historical Perspective and References
71(1)
Updated Exercises
71
Diana Franklin
Online Appendices
Appendix D Storage Systems
Appendix E Embedded Systems
Thomas M. Conte
Appendix F Interconnection Networks
Timothy M. Pinkston
Jose Duato
Appendix G Vector Processors in More Depth
Krste Asanovic
Appendix H Hardware and Software for VLIW and EPIC
Appendix I Large-Scale Multiprocessors and Scientific Applications
Appendix J Computer Arithmetic
David Goldberg
Appendix K Survey of Instruction Set Architectures
Appendix L Advanced Concepts on Address Translation
Abhishek Bhattacharjee
Appendix M Historical Perspectives and References
References 1(1)
Index 1
ACM named John L. Hennessy a recipient of the 2017 ACM A.M. Turing Award for pioneering a systematic, quantitative approach to the design and evaluation of computer architectures with enduring impact on the microprocessor industry. John L. Hennessy is a Professor of Electrical Engineering and Computer Science at Stanford University, where he has been a member of the faculty since 1977 and was, from 2000 to 2016, its tenth President. Prof. Hennessy is a Fellow of the IEEE and ACM; a member of the National Academy of Engineering, the National Academy of Science, and the American Philosophical Society; and a Fellow of the American Academy of Arts and Sciences. Among his many awards are the 2001 Eckert-Mauchly Award for his contributions to RISC technology, the 2001 Seymour Cray Computer Engineering Award, and the 2000 John von Neumann Award, which he shared with David Patterson. He has also received seven honorary doctorates. David Patterson is the Pardee Professor of Computer Science, Emeritus at the University of California at Berkeley, which he joined after graduating from UCLA in 1977.His teaching has been honored by the Distinguished Teaching Award from the University of California, the Karlstrom Award from ACM, and the Mulligan Education Medal and Undergraduate Teaching Award from IEEE. Prof. Patterson received the IEEE Technical Achievement Award and the ACM Eckert-Mauchly Award for contributions to RISC, and he shared the IEEE Johnson Information Storage Award for contributions to RAID. He also shared the IEEE John von Neumann Medal and the C & C Prize with John Hennessy. Like his co-author, Prof. Patterson is a Fellow of the American Academy of Arts and Sciences, the Computer History Museum, ACM, and IEEE, and he was elected to the National Academy of Engineering, the National Academy of Sciences, and the Silicon Valley Engineering Hall of Fame. He served on the Information Technology Advisory Committee to the U.S. President, as chair of the CS division in the Berkeley EECS department, as chair of the Computing Research Association, and as President of ACM. This record led to Distinguished Service Awards from ACM, CRA, and SIGARCH.