Muutke küpsiste eelistusi

Computer Arithmetic - Volume I [Kõva köide]

Edited by (The Univ Of Texas At Austin, Usa)
  • Formaat: Hardback, 396 pages
  • Ilmumisaeg: 18-May-2015
  • Kirjastus: World Scientific Publishing Co Pte Ltd
  • ISBN-10: 9814651567
  • ISBN-13: 9789814651561
Teised raamatud teemal:
Computer Arithmetic - Volume ISuurem pilt
  • Formaat: Hardback, 396 pages
  • Ilmumisaeg: 18-May-2015
  • Kirjastus: World Scientific Publishing Co Pte Ltd
  • ISBN-10: 9814651567
  • ISBN-13: 9789814651561
Teised raamatud teemal:
Püsilink: https://www.kriso.ee/db/9789814651561.html
Märksõnad:
The book provides many of the basic papers in computer arithmetic. These papers describe the concepts and basic operations (in the words of the original developers) that would be useful to the designers of computers and embedded systems. Although the main focus is on the basic operations of addition, multiplication and division, advanced concepts such as logarithmic arithmetic and the calculations of elementary functions are also covered.
Preface v
Introduction xv
Part I: Overview
Editors' Comments on Papers 1 and 2
1(2)
1 "Arithmetic Operations in a Binary Computer," Review of Scientific Instruments, vol. 21, pp. 687-693, 1950
3(8)
R.F. Shaw
2 "High-Speed Arithmetic in Binary Computers," Proceedings of the IRE, vol. 49, pp. 67-91, 1961
11(26)
O.L. MacSorley
Part II: Addition
Editors' Comments on Papers 3 Through 7
37(2)
3 "Fast Carry Logic for Digital Computers," IRE Transactions on Electronic Computers, vol. EC-4, pp. 133-136, 1955
39(4)
B. Gilchrist
J.H. Pomerene
S.Y. Wong
4 "Skip Techniques for High-Speed Carry-Propagation in Binary Arithmetic Units," IRE Transactions on Electronic Computers, vol. EC-10, pp. 691-698, 1961
43(8)
M. Lehman
N. Burla
5 "A logic for High-Speed Addition," National Bureau of Standards Circular, No. 591, pp. 3-12, 1958
51(10)
A. Weinberger
J.L. Smith
6 "Carry-Select Adder," IRE Transactions on Electronic Computers, vol. EC-11, pp. 340-346, 1962
61(8)
O.J. Bedrij
7 "Conditional-Sum Addition Logic," IRE Transactions on Electronic Computers, vol. EC-9, pp. 226-231, 1960
69(6)
J. Sklansky
Part III: Parallel Prefix Addition
Editors' Comments on Papers 8 Through 10
75(2)
8 "A Regular Layout for Parallel Adders," IEEE Transactions on Computers, vol. C-31, pp. 260-264, 1982
77(6)
R.P. Brent
H.T. Kung
9 "Fast Area-Efficient VLSI Adders," 8th Symposium on Computer Arithmetic, pp. 49-56, 1987
83(8)
T. Han and D.A. Carlson
10 "A Family of Adders," 15th IEEE Symposium on Computer Arithmetic, pp. 277-284, 2001
91(8)
S. Knowles
Part IV: Multi-Operand Addition
Editors' Comments on Papers 11 Through 14
99(2)
11 "Adder with Distributed Control," IEEE Transactions on Computers, vol. C-19, pp. 749-751, 1970
101(4)
A. Svoboda
12 "Multiple Addition by Residue Threshold Functions and Their Representation by Array Logic," IEEE Transactions on Computers, vol. C-22, pp. 762-767, 1973
105(6)
I.T. Ho
T.C. Chen
13 "Counting Responders in an Associative Memory," IEEE Transactions on Computers, vol. C-20, pp. 1580-1583, 1971
111(4)
C.C. Foster
F.D. Stockton
14 "Parallel Counters," IEEE Transactions on Computers, vol. C-22, pp. 1021-1024, 1973
115(4)
E.E. Swartzlander Jr
Part V: Multiplication
Editors' Comments on Papers 15 Through 22
119(4)
15 "A Signed Binary Multiplication Technique," Quarterly Journal of Mechanics and Applied Mathematics, vol. 4, pp. 236-240, 1951
123(6)
A.D. Booth
16 "A Binary Multiplication Scheme Based on Squaring," IEEE Transactions on Computers, vol. C-20, pp. 678-680, 1971
129(4)
T.C. Chen
17 "A Suggestion for a Fast Multiplier," IEEE Transactions on Electronic Computers, vol. EC-13, pp. 14-17, 1964
133(4)
C.S. Wallace
18 "Some Schemes for Parallel Multipliers," Alta Frequenza, vol. 34, pp. 349-356, 1965
137(8)
L. Dadda
19 "A Compact High-Speed Parallel Multiplication Scheme," IEEE Transactions on Computers, vol. C-26, pp. 948-957, 1977
145(10)
W.J. Stenzel
W.J. Kubitz
G.H. Garcia
20A "A Two's Complement Parallel Array Multiplication Algorithm," IEEE Transactions on Computers, vol. C-22, pp. 1045-1047, 1973
155(4)
C.R. Baugh
B.A. Wooley
20B "Comments on "A Two's Complement Parallel Array Multiplication Algorithm," IEEE Transactions on Computers, vol. C-23, p. 1327, 1974
159(2)
P.E. Blankenship
21 "The Quasi-Serial Multiplier," IEEE Transactions on Computers, vol. C-22, pp. 317-321, 1973
161(6)
E.E. Swartzlander Jr
22 "The Two's Complement Quasi-Serial Multiplier," IEEE Transactions on Computers, vol. C-24, pp. 1233-1235, 1975
167(4)
T.G. McDaneld
R.K. Guha
Part VI: Division
Editors' Comments on Papers 23 Through 28
171(2)
23 "A New Class of Digital Division Methods," IRE Transactions on Electronic Computers, vol. EC-7, pp. 218-222, 1958
173(6)
J.E. Robertson
24 "An Algorithm for Rapid Binary Division," IRE Transactions on Electronic Computers, vol. EC-10, pp. 662-670, 1961
179(10)
J.B. Wilson
R.S. Ledley
25 "Higher-Radix Division Using Estimates of the Divisor and Partial Remainders," IEEE Transactions on Computers, vol. C-17, pp. 925-934, 1968
189(10)
D.E. Atkins
26 "An Algorithm for Division," Information Processing Machines, vol. 9, pp. 25-32, 1963
199(8)
A. Svoboda
27 "A Division Method Using a Parallel Multiplier," IEEE Transactions on Electronic Computers, vol. EC-16, pp. 224-226, 1967
207(4)
D. Ferrari
28 "On Division by Functional Iteration," IEEE Transactions on Computers, vol. C-19, pp. 702-706, 1970
211(6)
M.J. Flynn
Part VII: Logarithms
Editors' Comments on Papers 29 Through 33
217(2)
29 "Computation of the Base Two Logarithm of Binary Numbers," IEEE Transactions on Electronic Computers, vol. EC-14, pp. 863-867, 1965
219(6)
M. Combet
H. Van Zonneveld
L. Verbeek
30 "New Algorithms for the Approximate Evaluation in Hardware of Binary Logarithms and Elementary Functions," IEEE Transactions on Computers, vol. C-21, pp. 1416-1421, 1972
225(6)
D. Marino
31 "A Note on Base-2 Logarithm Computations," Proceedings of the IEEE, vol. 61, pp. 1519-1520, 1973
231(2)
J.C. Majithia
D. Levan
32 "Digital Filtering Using Logarithmic Arithmetic," Electronics Letters, vol. 7, pp. 56-58, 1971
233(4)
N.G. Kingsbury
P.J.W. Rayner
33 "The Sign/Logarithm Number System," IEEE Transactions on Computers, vol. C-24, pp. 1238-1242, 1975
237(6)
E.E. Swartzlander Jr
A.G. Alexopoulos
Part VIII: Elementary Functions
Editors' Comments on Papers 34 Through 39
243(2)
34 "The CORDIC Trigonometric Computing Technique, IRE Transactions on Electronic Computers, vol. EC-8, pp. 330-334, 1959
245(6)
J.E. Voider
35 "A Unified Algorithm for Elementary Functions," Proceedings of the Spring Joint Computer Conference, pp. 379-385, 1971
251(8)
J.S. Walther
36 "A Class of Algorithms for Ln x, Exp x, Sin x, Cos x, Tan-1 x, and Cot-1 x," IEEE Transactions on Electronic Computers, vol. EC-14, pp. 85-86, 1965
259(2)
W.H. Specker
37 "Digit-by-Digit Transcendental Function Computation," RCA Review, vol. 30, pp. 209-247, 1969
261(40)
R.J. Linhardt
H.S. Miiller
38 "Some Properties of Iterative Square-Rooting Methods Using High-Speed Multiplication," IEEE Transactions on Computers, vol. C-21, pp. 837-847, 1972
301(12)
C.V. Ramamoorthy
J.R. Goodman
K.H. Kim
39 "Radix-16 Evaluation of Certain Elementary Functions," IEEE Transactions on Computers, vol. C-22, pp. 561-566, 1973
313(6)
M.D. Ercegovac
Part IX: Floating-Point Arithmetic
Editors' Comments on Papers 40 Through 42
319(2)
40 "On the Distribution of Numbers," Bell System Technical Journal, vol. 49, pp. 1609-1625, 1970
321(18)
R.W. Hamming
41 "An Analysis of Floating-Point Addition," IBM System Journal, vol. 4, pp. 31-42, 1965
339(12)
D.W. Sweeney
42 "The IBM System/360 Model 91: Floating-Point Execution Unit," IBM Journal of Research and Development, vol. 11, pp. 34-53, 1967
351(20)
S.F. Anderson
J.G. Earle
R.E. Goldschmidt
D.M. Powers
Bibliography 371