Muutke küpsiste eelistusi

Computer Arithmetic - Volume Ii [Kõva köide]

Edited by (The Univ Of Texas At Austin, Usa)
  • Formaat: Hardback, 484 pages
  • Ilmumisaeg: 18-May-2015
  • Kirjastus: World Scientific Publishing Co Pte Ltd
  • ISBN-10: 9814641464
  • ISBN-13: 9789814641463
Teised raamatud teemal:
Computer Arithmetic - Volume IiSuurem pilt
  • Formaat: Hardback, 484 pages
  • Ilmumisaeg: 18-May-2015
  • Kirjastus: World Scientific Publishing Co Pte Ltd
  • ISBN-10: 9814641464
  • ISBN-13: 9789814641463
Teised raamatud teemal:
Püsilink: https://www.kriso.ee/db/9789814641463.html
Märksõnad:
This is the new edition of the classic book Computer Arithmetic in three volumes published originally in 1990 by IEEE Computer Society Press. As in the original, the book contains many classic papers treating advanced concepts in computer arithmetic, which is very suitable as stand-alone textbooks or complementary materials to textbooks on computer arithmetic for graduate students and research professionals interested in the field.Told in the words of the initial developers, this book conveys the excitement of the creators, and the implementations provide insight into the details necessary to realize real chips. This second volume presents topics on error tolerant arithmetic, digit on-line arithmetic, number systems, and now in this new edition, a topic on implementations of arithmetic operations, all wrapped with an updated overview and a new introduction for each chapter.
About the Editor v
Preface vii
Contents by Author ix
Overview of Computer Arithmetic xvii
PART I ERROR TOLERANT ARITHMETIC
Editors' Comments on Papers 1 Through 5
1(2)
1 "Error Detecting and Error Correcting Codes," Bell System Technical Journal, vol. 29, pp. 147--160, 1950
3(14)
R. W. Hamming
2 "Generalized Parity Checking," IRE Transactions on Electronic Computers, vol. EC-7, pp. 207--213, 1958
17(8)
H. L. Garner
3 "Error-Checking Logic for Arithmetic-Type Operations of a Processor," IEEE Transactions on Computers, vol. C-17, pp. 845--849, 1968
25(6)
T. R. N. Rao
4 "Arithmetic Algorithms for Error-Coded Operands," IEEE Transactions on Computers, vol. C-22, pp. 567--572, 1973
31(6)
A. Avizienis
5 "Error Detection and Correction for Addition and Subtraction, Through Higher Radix Extensions of Hamming Codes," Proceedings of the Eighth Symposium on Computer Arithmetic, pp. 87--94, 1987
37(4)
J. E. Robertson
PART II ON-LINE ARITHMETIC
Editor's Comments on Papers 6 Through 13
41(2)
6 "Signed-Digit Number Representations for Fast Parallel Arithmetic," Proceedings of the IRE Transactions on Electronic Computers, vol. EC-10, pp. 389--400, 1961
43(12)
A. Avizienis
7 "On-Line Arithmetic: A Design Methodology and Applications in Digital Signal Processing," VLSI Signal Processing, III, pp. 252--263, 1988
55(12)
M. D. Ercegovac
T. Lang
8 "On-Line Algorithms for Division and Multiplication," IEEE Transactions on Computers, vol. C-26, pp. 681--687, 1977
67(8)
K. S. Trividi
M. D. Ercegovac
9 "Error Analysis of Certain Floating-Point On-Line Algorithms," IEEE Transactions on Computers, vol. C-32, pp. 352--358, 1983
75(8)
O. Watanuki
M. D. Ercegovac
10 "Improved Normalization Results for Digit On-Line Arithmetic," Proceedings of the Seventh Symposium on Computer Arithmetic, pp. 20--27, 1985., pp. 149-154, 1995
83(8)
R. J. Zaccone
J. L. Barlow
11 "Fully Digit On-Line Networks," IEEE Transactions on Computers, vol. C-32, pp. 402--406, 1983
91(4)
M. J. Irwin
R. M. Owens
12 "On-Line Scheme for Computing Rotation Factors," Journal of Parallel and Distributed Computing, vol. 5, pp. 209--227, 1988
95(20)
M. D. Ercegovac
T. Lang
13 "On-the-Fly Conversion of Redundant into Conventional Representations," IEEE Transactions on Computers, vol. C-36, pp. 895--897, 1987
115(4)
M. D. Ercegovac
T. Lang
PART III VLSI ADDER IMPLEMENTATIONS
Editor's Comments on Papers 14 Through 18
119(2)
14 "Time-Component Complexity of Two Approaches to Multioperand Binary Addition," IEEE Transactions on Computers, vol. C-28, pp. 918--926, 1979
121(10)
D. E. Atkins
S.-C. Ong
15 "Some Optimal Schemes for ALU Implementation in VLSI Technology," Proceedings of the Seventh Symposium on Computer Arithmetic, pp. 2--8, 1985
131(8)
V. G. Oklobdzija
E. R. Barnes
16 "An Area-Time Efficient NMOS Adder," Integration, the VLSI Journal, vol. 1, pp. 317--334, 1983
139(18)
M. A. Bayoumi
G. A. Jullien
W. C. Miller
17 "Regular, Area-Time Efficient Carry-Lookahead Adders," Journal of Parallel and Distributed Computing, vol. 3, pp. 92--105, 1986
157(14)
T.-F. Ngai
M. J. Irwin
S. Rawat
18 "Efficient Use of Time and Hardware Redundancy for Concurrent Error Detection in a 32-bit VLSI Adder," IEEE Journal of Solid-State Circuits, vol. 23, pp. 208--215, 1988
171(8)
B. W. Johnson
J. H. Aylor
H. H. Hana
PART IV VLSI MULTIPLIER IMPLEMENTATIONS
Editor's Comments on Papers 19 Through 24
179(2)
19 "A Monolithic 16 × 16 Digital Multiplier," IEEE International Solid-State Circuits Conference Digest of Technical Papers, pp. 231--233, 1974
181(4)
G. W. McIver
R. W. Miller
T. G. O'Shaughnessy
20 "Optimization of One-Bit Full Adders Embedded in Regular Structures," IEEE Transactions on Acoustics, Speech, and Signal Processing, vol. ASSP-34, pp. 1289--1300, 1986
185(12)
K. Iwano
K. Stiglitz
21 "A VLSI Layout for a Pipelined Dadda Multiplier," ACM Transactions on Computer Systems, vol. 1, pp. 157--174, 1983
197(18)
P. R. Cappello
K. Stiglitz
22 "A Very Fast Multiplication Algorithm for VLSI Implementation," Integration, the VLSI Journal, vol. 1, pp. 39--52, 1983
215(14)
J. Vuillemin
23 "A High-Speed Multiplier Using a Redundant Binary Adder Tree," IEEE Journal of Solid-State Circuits, vol. SC-22, pp. 28--34, 1987
229(8)
Y. Harata
Y. Nakamura
H. Nagase
M. Takagawa
N. Takagi
24 "A Sub-10-ns 16 × 16 Multiplier Using 0.6-μm CMOS Technology," IEEE Journal of Solid-State Circuits, vol. SC-22, pp. 762--767, 1987
237(6)
Y. Oowaki
K. Numata
K. Tsuchiya
K. Tsuda
H. Takato
N. Takenouchi
A. Nitayama
T. Kobayashi
M. Chiba
S. Watanabe
K. Ohuchi
A. Hojo
PART V FLOATING-POINT VLSI CHIPS
Editor's Comments on Papers 25 Through 30
243(2)
25 "A High Performance Floating Point Coprocessor," IEEE Journal of Solid-State Circuits, vol. SC-19, pp. 690--696, 1984
245(8)
G. Wolrich
E. McLellan
L. Harada
J. Montanaro
R. A. J. Yodlowski
26 "64 Bit Monolithic Floating Point Processors," IEEE Journal of Solid-State Circuits, vol. SC-17, pp. 898--907, 1982
253(10)
F. A. Ware
W. H. McAllister
J. R. Carlson
D. K. Sun
R. J. Vlach
27 "A CMOS Floating Point Multiplier," IEEE Journal of Solid-State Circuits, vol. SC-19, pp. 697--702, 1984
263(6)
M. Uya
K. Kaneko
J. Yasui
28 "A Single-Chip 80-Bit Floating Point Processor," IEEE Journal of Solid-State Circuits, vol. SC-20, pp. 986--992, 1985
269(8)
K. Takeda
F. Ishino
Y. Ito
R. Kasai
T. Nakashima
29 "VLSI Floating-Point Processors," Proceedings of the Seventh Symposium on Computer Arithmetic, pp. 93--100, 1985
277(8)
J. Fandrianto
B. Y. Woo
30 "Fast Multiply and Divide for a VLSI Floating-Point Unit," Proceedings of the Eighth Symposium on Computer Arithmetic, pp. 87--94, 1987
285(8)
B. K. Bose
L. Pei
G. S. Taylor
D. A. Patterson
PART VI NUMBER REPRESENTATION
Editor's Comments on Papers 31 Through 37
293(2)
31 "The Residue Number System," IRE Transactions on Electronic Computers, vol. EC-8, pp. 140--147, 1959
295(8)
H. Garner
32 "A Formalization of Floating-Point Numeric Base Conversion," IEEE Transactions on Computers, vol. C-19, pp. 681--692, 1970
303(12)
D. W. Matula
33 "CADAC: A Controlled-Precision Decimal Arithmetic Unit," IEEE Transactions on Computers, vol. C-32, pp. 370--377, 1983
315(8)
M. S. Cohen
T. E. Hull
V. C. Hamacher
34 "Finite Precision Rational Arithmetic: Slash Number Systems," IEEE Transactions on Computers, vol. C-34, pp. 3--18, 1985
323(16)
D. W. Matula
P. Kornerup
35 "Finite Precision Lexicographic Continued Fraction Number Systems," Proceedings of the Seventh Symposium on Computer Arithmetic, pp. 207--214, 1985
339(8)
P. Kornerup
D. W. Matula
36 "An Overflow/Underflow-Free Floating-Point Representation of Numbers," Journal of Information Processing, vol. 4, pp. 123--133, 1981
347(12)
S. Matsui
M. Iri
37 "A Closed Computer Arithmetic," Proceedings of the Eighth Symposium on Computer Arithmetic, pp. 139--143, 1987
359(6)
F. W. J. Olver
PART VII IMPLEMENTATIONS
Editor's Comments on Papers 38 Through 40
365(2)
38 "Applications of Distributed Arithmetic to Digital Signal Processing: A Tutorial Review," IEEE ASSP Magazine, vol. 6, no. 3, pp. 4--19, 1989
367(16)
S. A. White
39 "Designing Low-Power Circuits: Practical Recipes," IEEE Circuits and Systems Magazine, vol. 1, no. 1, pp. 6--25, 2001
383(20)
L. Benini
G. De Micheli
E. Mach
40 "The European Logarithmic Microprocessor," IEEE Transactions on Computers, vol. 57, pp. 532--546, 2008
403(16)
J. N. Coleman
C. L. Softley
J. Kadlec
R. Matuosek
M. Tichy
Z. Pohl
A. Hermanek
N. F. Benschop
Bibliography 419